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Commit | Line | Data |
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06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | ||
20 | #include "msm_drv.h" | |
21 | #include "msm_mmu.h" | |
22 | #include "mdp5_kms.h" | |
23 | ||
87e956e9 SV |
24 | static const char *iommu_ports[] = { |
25 | "mdp_0", | |
26 | }; | |
27 | ||
3d47fd47 SV |
28 | static int mdp5_hw_init(struct msm_kms *kms) |
29 | { | |
30 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
31 | struct drm_device *dev = mdp5_kms->dev; | |
0deed25b | 32 | unsigned long flags; |
3d47fd47 SV |
33 | |
34 | pm_runtime_get_sync(dev->dev); | |
35 | ||
06c0dd96 RC |
36 | /* Magic unknown register writes: |
37 | * | |
38 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
39 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
40 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
41 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
42 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
43 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
44 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
45 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
46 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
47 | * | |
48 | * Downstream fbdev driver gets these register offsets/values | |
49 | * from DT.. not really sure what these registers are or if | |
50 | * different values for different boards/SoC's, etc. I guess | |
51 | * they are the golden registers. | |
52 | * | |
53 | * Not setting these does not seem to cause any problem. But | |
54 | * we may be getting lucky with the bootloader initializing | |
55 | * them for us. OTOH, if we can always count on the bootloader | |
56 | * setting the golden registers, then perhaps we don't need to | |
57 | * care. | |
58 | */ | |
59 | ||
0deed25b | 60 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
f5253812 | 61 | mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); |
0deed25b | 62 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 63 | |
42238da8 | 64 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 65 | |
06c0dd96 RC |
66 | pm_runtime_put_sync(dev->dev); |
67 | ||
3d47fd47 | 68 | return 0; |
06c0dd96 RC |
69 | } |
70 | ||
0b776d45 RC |
71 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
72 | { | |
73 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
74 | mdp5_enable(mdp5_kms); | |
75 | } | |
76 | ||
77 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
78 | { | |
79 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
80 | mdp5_disable(mdp5_kms); | |
81 | } | |
82 | ||
06c0dd96 RC |
83 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
84 | struct drm_encoder *encoder) | |
85 | { | |
86 | return rate; | |
87 | } | |
88 | ||
89 | static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file) | |
90 | { | |
91 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
92 | struct msm_drm_private *priv = mdp5_kms->dev->dev_private; | |
93 | unsigned i; | |
94 | ||
95 | for (i = 0; i < priv->num_crtcs; i++) | |
96 | mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file); | |
97 | } | |
98 | ||
99 | static void mdp5_destroy(struct msm_kms *kms) | |
100 | { | |
101 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
87e956e9 SV |
102 | struct msm_mmu *mmu = mdp5_kms->mmu; |
103 | ||
f6a8eaca RC |
104 | mdp5_irq_domain_fini(mdp5_kms); |
105 | ||
87e956e9 SV |
106 | if (mmu) { |
107 | mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); | |
108 | mmu->funcs->destroy(mmu); | |
109 | } | |
42238da8 RC |
110 | |
111 | if (mdp5_kms->ctlm) | |
112 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
113 | if (mdp5_kms->smp) | |
114 | mdp5_smp_destroy(mdp5_kms->smp); | |
115 | if (mdp5_kms->cfg) | |
116 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
bfcdfb0e | 117 | |
06c0dd96 RC |
118 | kfree(mdp5_kms); |
119 | } | |
120 | ||
121 | static const struct mdp_kms_funcs kms_funcs = { | |
122 | .base = { | |
123 | .hw_init = mdp5_hw_init, | |
124 | .irq_preinstall = mdp5_irq_preinstall, | |
125 | .irq_postinstall = mdp5_irq_postinstall, | |
126 | .irq_uninstall = mdp5_irq_uninstall, | |
127 | .irq = mdp5_irq, | |
128 | .enable_vblank = mdp5_enable_vblank, | |
129 | .disable_vblank = mdp5_disable_vblank, | |
0b776d45 RC |
130 | .prepare_commit = mdp5_prepare_commit, |
131 | .complete_commit = mdp5_complete_commit, | |
06c0dd96 RC |
132 | .get_format = mdp_get_format, |
133 | .round_pixclk = mdp5_round_pixclk, | |
134 | .preclose = mdp5_preclose, | |
135 | .destroy = mdp5_destroy, | |
136 | }, | |
137 | .set_irqmask = mdp5_set_irqmask, | |
138 | }; | |
139 | ||
140 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
141 | { | |
142 | DBG(""); | |
143 | ||
144 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
145 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
146 | clk_disable_unprepare(mdp5_kms->core_clk); | |
147 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
152 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
153 | { | |
154 | DBG(""); | |
155 | ||
156 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
157 | clk_prepare_enable(mdp5_kms->axi_clk); | |
158 | clk_prepare_enable(mdp5_kms->core_clk); | |
159 | clk_prepare_enable(mdp5_kms->lut_clk); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
67ac0a2d SV |
164 | static int construct_encoder(struct mdp5_kms *mdp5_kms, |
165 | enum mdp5_intf_type intf_type, int intf_num) | |
166 | { | |
167 | struct drm_device *dev = mdp5_kms->dev; | |
168 | struct msm_drm_private *priv = dev->dev_private; | |
169 | struct drm_encoder *encoder; | |
170 | struct mdp5_interface intf = { | |
171 | .num = intf_num, | |
172 | .type = intf_type, | |
173 | .mode = MDP5_INTF_MODE_NONE, | |
174 | }; | |
175 | int ret = 0; | |
176 | ||
177 | encoder = mdp5_encoder_init(dev, &intf); | |
178 | if (IS_ERR(encoder)) { | |
179 | ret = PTR_ERR(encoder); | |
180 | dev_err(dev->dev, "failed to construct encoder: %d\n", ret); | |
181 | return ret; | |
182 | } | |
183 | ||
184 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
185 | priv->encoders[priv->num_encoders++] = encoder; | |
186 | ||
187 | if (intf_type == INTF_HDMI) { | |
188 | ret = hdmi_modeset_init(priv->hdmi, dev, encoder); | |
189 | if (ret) | |
190 | dev_err(dev->dev, "failed to init HDMI: %d\n", ret); | |
191 | ||
192 | } else if (intf_type == INTF_eDP) { | |
193 | /* Construct bridge/connector for eDP: */ | |
194 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); | |
195 | if (ret) | |
196 | dev_err(dev->dev, "failed to init eDP: %d\n", ret); | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
06c0dd96 RC |
202 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
203 | { | |
204 | static const enum mdp5_pipe crtcs[] = { | |
3d47fd47 | 205 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, |
06c0dd96 | 206 | }; |
0deed25b SV |
207 | static const enum mdp5_pipe pub_planes[] = { |
208 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, | |
209 | }; | |
06c0dd96 RC |
210 | struct drm_device *dev = mdp5_kms->dev; |
211 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 212 | const struct mdp5_cfg_hw *hw_cfg; |
06c0dd96 RC |
213 | int i, ret; |
214 | ||
42238da8 | 215 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 216 | |
f6a8eaca RC |
217 | /* register our interrupt-controller for hdmi/eDP/dsi/etc |
218 | * to use for irqs routed through mdp: | |
219 | */ | |
220 | ret = mdp5_irq_domain_init(mdp5_kms); | |
221 | if (ret) | |
222 | goto fail; | |
223 | ||
0deed25b | 224 | /* construct CRTCs and their private planes: */ |
2e362e17 | 225 | for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { |
06c0dd96 RC |
226 | struct drm_plane *plane; |
227 | struct drm_crtc *crtc; | |
228 | ||
0deed25b SV |
229 | plane = mdp5_plane_init(dev, crtcs[i], true, |
230 | hw_cfg->pipe_rgb.base[i]); | |
06c0dd96 RC |
231 | if (IS_ERR(plane)) { |
232 | ret = PTR_ERR(plane); | |
233 | dev_err(dev->dev, "failed to construct plane for %s (%d)\n", | |
234 | pipe2name(crtcs[i]), ret); | |
235 | goto fail; | |
236 | } | |
237 | ||
238 | crtc = mdp5_crtc_init(dev, plane, i); | |
239 | if (IS_ERR(crtc)) { | |
240 | ret = PTR_ERR(crtc); | |
241 | dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", | |
242 | pipe2name(crtcs[i]), ret); | |
243 | goto fail; | |
244 | } | |
245 | priv->crtcs[priv->num_crtcs++] = crtc; | |
246 | } | |
247 | ||
0deed25b SV |
248 | /* Construct public planes: */ |
249 | for (i = 0; i < hw_cfg->pipe_vig.count; i++) { | |
250 | struct drm_plane *plane; | |
251 | ||
252 | plane = mdp5_plane_init(dev, pub_planes[i], false, | |
253 | hw_cfg->pipe_vig.base[i]); | |
254 | if (IS_ERR(plane)) { | |
255 | ret = PTR_ERR(plane); | |
256 | dev_err(dev->dev, "failed to construct %s plane: %d\n", | |
257 | pipe2name(pub_planes[i]), ret); | |
258 | goto fail; | |
259 | } | |
260 | } | |
261 | ||
67ac0a2d SV |
262 | /* Construct external display interfaces' encoders: */ |
263 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) { | |
264 | enum mdp5_intf_type intf_type = hw_cfg->intfs[i]; | |
265 | ||
266 | switch (intf_type) { | |
267 | case INTF_DISABLED: | |
268 | break; | |
269 | case INTF_eDP: | |
270 | if (priv->edp) | |
271 | ret = construct_encoder(mdp5_kms, INTF_eDP, i); | |
272 | break; | |
273 | case INTF_HDMI: | |
274 | if (priv->hdmi) | |
275 | ret = construct_encoder(mdp5_kms, INTF_HDMI, i); | |
276 | break; | |
277 | default: | |
278 | dev_err(dev->dev, "unknown intf: %d\n", intf_type); | |
279 | ret = -EINVAL; | |
280 | break; | |
00453981 HL |
281 | } |
282 | ||
67ac0a2d | 283 | if (ret) |
00453981 | 284 | goto fail; |
00453981 HL |
285 | } |
286 | ||
06c0dd96 RC |
287 | return 0; |
288 | ||
289 | fail: | |
290 | return ret; | |
291 | } | |
292 | ||
2e362e17 SV |
293 | static void read_hw_revision(struct mdp5_kms *mdp5_kms, |
294 | uint32_t *major, uint32_t *minor) | |
295 | { | |
296 | uint32_t version; | |
297 | ||
298 | mdp5_enable(mdp5_kms); | |
f5253812 | 299 | version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION); |
2e362e17 SV |
300 | mdp5_disable(mdp5_kms); |
301 | ||
f5253812 SV |
302 | *major = FIELD(version, MDSS_HW_VERSION_MAJOR); |
303 | *minor = FIELD(version, MDSS_HW_VERSION_MINOR); | |
2e362e17 SV |
304 | |
305 | DBG("MDP5 version v%d.%d", *major, *minor); | |
306 | } | |
307 | ||
06c0dd96 RC |
308 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
309 | const char *name) | |
310 | { | |
311 | struct device *dev = &pdev->dev; | |
312 | struct clk *clk = devm_clk_get(dev, name); | |
313 | if (IS_ERR(clk)) { | |
314 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); | |
315 | return PTR_ERR(clk); | |
316 | } | |
317 | *clkp = clk; | |
318 | return 0; | |
319 | } | |
320 | ||
321 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) | |
322 | { | |
323 | struct platform_device *pdev = dev->platformdev; | |
2e362e17 | 324 | struct mdp5_cfg *config; |
06c0dd96 RC |
325 | struct mdp5_kms *mdp5_kms; |
326 | struct msm_kms *kms = NULL; | |
327 | struct msm_mmu *mmu; | |
2e362e17 | 328 | uint32_t major, minor; |
3d47fd47 | 329 | int i, ret; |
06c0dd96 RC |
330 | |
331 | mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); | |
332 | if (!mdp5_kms) { | |
333 | dev_err(dev->dev, "failed to allocate kms\n"); | |
334 | ret = -ENOMEM; | |
335 | goto fail; | |
336 | } | |
337 | ||
0deed25b SV |
338 | spin_lock_init(&mdp5_kms->resource_lock); |
339 | ||
06c0dd96 RC |
340 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); |
341 | ||
342 | kms = &mdp5_kms->base.base; | |
343 | ||
344 | mdp5_kms->dev = dev; | |
06c0dd96 | 345 | |
f5253812 | 346 | /* mdp5_kms->mmio actually represents the MDSS base address */ |
06c0dd96 RC |
347 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
348 | if (IS_ERR(mdp5_kms->mmio)) { | |
349 | ret = PTR_ERR(mdp5_kms->mmio); | |
350 | goto fail; | |
351 | } | |
352 | ||
353 | mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); | |
354 | if (IS_ERR(mdp5_kms->vbif)) { | |
355 | ret = PTR_ERR(mdp5_kms->vbif); | |
356 | goto fail; | |
357 | } | |
358 | ||
359 | mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); | |
360 | if (IS_ERR(mdp5_kms->vdd)) { | |
361 | ret = PTR_ERR(mdp5_kms->vdd); | |
362 | goto fail; | |
363 | } | |
364 | ||
365 | ret = regulator_enable(mdp5_kms->vdd); | |
366 | if (ret) { | |
367 | dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); | |
368 | goto fail; | |
369 | } | |
370 | ||
a0906a02 RC |
371 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); |
372 | if (ret) | |
373 | goto fail; | |
374 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); | |
375 | if (ret) | |
376 | goto fail; | |
377 | ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); | |
378 | if (ret) | |
379 | goto fail; | |
380 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); | |
381 | if (ret) | |
382 | goto fail; | |
383 | ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); | |
384 | if (ret) | |
385 | goto fail; | |
386 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk"); | |
06c0dd96 RC |
387 | if (ret) |
388 | goto fail; | |
389 | ||
ac7a5704 RC |
390 | /* we need to set a default rate before enabling. Set a safe |
391 | * rate first, then figure out hw revision, and then set a | |
392 | * more optimal rate: | |
393 | */ | |
394 | clk_set_rate(mdp5_kms->src_clk, 200000000); | |
395 | ||
2e362e17 | 396 | read_hw_revision(mdp5_kms, &major, &minor); |
42238da8 RC |
397 | |
398 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
399 | if (IS_ERR(mdp5_kms->cfg)) { | |
400 | ret = PTR_ERR(mdp5_kms->cfg); | |
401 | mdp5_kms->cfg = NULL; | |
3d47fd47 | 402 | goto fail; |
2e362e17 | 403 | } |
42238da8 RC |
404 | |
405 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
3d47fd47 | 406 | |
3f307963 | 407 | /* TODO: compute core clock rate at runtime */ |
2e362e17 | 408 | clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); |
3f307963 | 409 | |
42238da8 RC |
410 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); |
411 | if (IS_ERR(mdp5_kms->smp)) { | |
412 | ret = PTR_ERR(mdp5_kms->smp); | |
413 | mdp5_kms->smp = NULL; | |
bfcdfb0e SV |
414 | goto fail; |
415 | } | |
bfcdfb0e | 416 | |
42238da8 RC |
417 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw); |
418 | if (IS_ERR(mdp5_kms->ctlm)) { | |
419 | ret = PTR_ERR(mdp5_kms->ctlm); | |
420 | mdp5_kms->ctlm = NULL; | |
0deed25b SV |
421 | goto fail; |
422 | } | |
0deed25b | 423 | |
06c0dd96 RC |
424 | /* make sure things are off before attaching iommu (bootloader could |
425 | * have left things on, in which case we'll start getting faults if | |
426 | * we don't disable): | |
427 | */ | |
428 | mdp5_enable(mdp5_kms); | |
67ac0a2d SV |
429 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { |
430 | if (!config->hw->intf.base[i] || | |
431 | mdp5_cfg_intf_is_virtual(config->hw->intfs[i])) | |
432 | continue; | |
3d47fd47 | 433 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); |
67ac0a2d | 434 | } |
06c0dd96 RC |
435 | mdp5_disable(mdp5_kms); |
436 | mdelay(16); | |
437 | ||
2e362e17 SV |
438 | if (config->platform.iommu) { |
439 | mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); | |
06c0dd96 RC |
440 | if (IS_ERR(mmu)) { |
441 | ret = PTR_ERR(mmu); | |
87e956e9 | 442 | dev_err(dev->dev, "failed to init iommu: %d\n", ret); |
06c0dd96 RC |
443 | goto fail; |
444 | } | |
87e956e9 | 445 | |
06c0dd96 RC |
446 | ret = mmu->funcs->attach(mmu, iommu_ports, |
447 | ARRAY_SIZE(iommu_ports)); | |
87e956e9 SV |
448 | if (ret) { |
449 | dev_err(dev->dev, "failed to attach iommu: %d\n", ret); | |
450 | mmu->funcs->destroy(mmu); | |
06c0dd96 | 451 | goto fail; |
87e956e9 | 452 | } |
06c0dd96 RC |
453 | } else { |
454 | dev_info(dev->dev, "no iommu, fallback to phys " | |
455 | "contig buffers for scanout\n"); | |
456 | mmu = NULL; | |
457 | } | |
87e956e9 | 458 | mdp5_kms->mmu = mmu; |
06c0dd96 RC |
459 | |
460 | mdp5_kms->id = msm_register_mmu(dev, mmu); | |
461 | if (mdp5_kms->id < 0) { | |
462 | ret = mdp5_kms->id; | |
463 | dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
464 | goto fail; | |
465 | } | |
466 | ||
467 | ret = modeset_init(mdp5_kms); | |
468 | if (ret) { | |
469 | dev_err(dev->dev, "modeset_init failed: %d\n", ret); | |
470 | goto fail; | |
471 | } | |
472 | ||
473 | return kms; | |
474 | ||
475 | fail: | |
476 | if (kms) | |
477 | mdp5_destroy(kms); | |
478 | return ERR_PTR(ret); | |
479 | } |