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Commit | Line | Data |
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06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | ||
20 | #include "msm_drv.h" | |
21 | #include "msm_mmu.h" | |
22 | #include "mdp5_kms.h" | |
23 | ||
87e956e9 SV |
24 | static const char *iommu_ports[] = { |
25 | "mdp_0", | |
26 | }; | |
27 | ||
3d47fd47 SV |
28 | static int mdp5_hw_init(struct msm_kms *kms) |
29 | { | |
30 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
31 | struct drm_device *dev = mdp5_kms->dev; | |
0deed25b | 32 | unsigned long flags; |
3d47fd47 SV |
33 | |
34 | pm_runtime_get_sync(dev->dev); | |
35 | ||
06c0dd96 RC |
36 | /* Magic unknown register writes: |
37 | * | |
38 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
39 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
40 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
41 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
42 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
43 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
44 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
45 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
46 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
47 | * | |
48 | * Downstream fbdev driver gets these register offsets/values | |
49 | * from DT.. not really sure what these registers are or if | |
50 | * different values for different boards/SoC's, etc. I guess | |
51 | * they are the golden registers. | |
52 | * | |
53 | * Not setting these does not seem to cause any problem. But | |
54 | * we may be getting lucky with the bootloader initializing | |
55 | * them for us. OTOH, if we can always count on the bootloader | |
56 | * setting the golden registers, then perhaps we don't need to | |
57 | * care. | |
58 | */ | |
59 | ||
0deed25b | 60 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
f5253812 | 61 | mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); |
0deed25b | 62 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 63 | |
42238da8 | 64 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 65 | |
06c0dd96 RC |
66 | pm_runtime_put_sync(dev->dev); |
67 | ||
3d47fd47 | 68 | return 0; |
06c0dd96 RC |
69 | } |
70 | ||
0b776d45 RC |
71 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
72 | { | |
73 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
74 | mdp5_enable(mdp5_kms); | |
75 | } | |
76 | ||
77 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
78 | { | |
657c63f0 | 79 | int i; |
0b776d45 | 80 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); |
657c63f0 WX |
81 | int nplanes = mdp5_kms->dev->mode_config.num_total_plane; |
82 | ||
83 | for (i = 0; i < nplanes; i++) { | |
84 | struct drm_plane *plane = state->planes[i]; | |
85 | struct drm_plane_state *plane_state = state->plane_states[i]; | |
86 | ||
87 | if (!plane) | |
88 | continue; | |
89 | ||
90 | mdp5_plane_complete_commit(plane, plane_state); | |
91 | } | |
92 | ||
0b776d45 RC |
93 | mdp5_disable(mdp5_kms); |
94 | } | |
95 | ||
0a5c9aad HL |
96 | static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, |
97 | struct drm_crtc *crtc) | |
98 | { | |
99 | mdp5_crtc_wait_for_commit_done(crtc); | |
100 | } | |
101 | ||
06c0dd96 RC |
102 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
103 | struct drm_encoder *encoder) | |
104 | { | |
105 | return rate; | |
106 | } | |
107 | ||
d5af49c9 HL |
108 | static int mdp5_set_split_display(struct msm_kms *kms, |
109 | struct drm_encoder *encoder, | |
110 | struct drm_encoder *slave_encoder, | |
111 | bool is_cmd_mode) | |
112 | { | |
113 | if (is_cmd_mode) | |
114 | return mdp5_cmd_encoder_set_split_display(encoder, | |
115 | slave_encoder); | |
116 | else | |
117 | return mdp5_encoder_set_split_display(encoder, slave_encoder); | |
118 | } | |
119 | ||
06c0dd96 RC |
120 | static void mdp5_destroy(struct msm_kms *kms) |
121 | { | |
122 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
87e956e9 SV |
123 | struct msm_mmu *mmu = mdp5_kms->mmu; |
124 | ||
f6a8eaca RC |
125 | mdp5_irq_domain_fini(mdp5_kms); |
126 | ||
87e956e9 SV |
127 | if (mmu) { |
128 | mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); | |
129 | mmu->funcs->destroy(mmu); | |
130 | } | |
42238da8 RC |
131 | |
132 | if (mdp5_kms->ctlm) | |
133 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
134 | if (mdp5_kms->smp) | |
135 | mdp5_smp_destroy(mdp5_kms->smp); | |
136 | if (mdp5_kms->cfg) | |
137 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
bfcdfb0e | 138 | |
06c0dd96 RC |
139 | kfree(mdp5_kms); |
140 | } | |
141 | ||
142 | static const struct mdp_kms_funcs kms_funcs = { | |
143 | .base = { | |
144 | .hw_init = mdp5_hw_init, | |
145 | .irq_preinstall = mdp5_irq_preinstall, | |
146 | .irq_postinstall = mdp5_irq_postinstall, | |
147 | .irq_uninstall = mdp5_irq_uninstall, | |
148 | .irq = mdp5_irq, | |
149 | .enable_vblank = mdp5_enable_vblank, | |
150 | .disable_vblank = mdp5_disable_vblank, | |
0b776d45 RC |
151 | .prepare_commit = mdp5_prepare_commit, |
152 | .complete_commit = mdp5_complete_commit, | |
0a5c9aad | 153 | .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, |
06c0dd96 RC |
154 | .get_format = mdp_get_format, |
155 | .round_pixclk = mdp5_round_pixclk, | |
d5af49c9 | 156 | .set_split_display = mdp5_set_split_display, |
06c0dd96 RC |
157 | .destroy = mdp5_destroy, |
158 | }, | |
159 | .set_irqmask = mdp5_set_irqmask, | |
160 | }; | |
161 | ||
162 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
163 | { | |
164 | DBG(""); | |
165 | ||
166 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
167 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
168 | clk_disable_unprepare(mdp5_kms->core_clk); | |
3a84f846 SV |
169 | if (mdp5_kms->lut_clk) |
170 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
06c0dd96 RC |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
175 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
176 | { | |
177 | DBG(""); | |
178 | ||
179 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
180 | clk_prepare_enable(mdp5_kms->axi_clk); | |
181 | clk_prepare_enable(mdp5_kms->core_clk); | |
3a84f846 SV |
182 | if (mdp5_kms->lut_clk) |
183 | clk_prepare_enable(mdp5_kms->lut_clk); | |
06c0dd96 RC |
184 | |
185 | return 0; | |
186 | } | |
187 | ||
5722a9e3 HL |
188 | static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, |
189 | enum mdp5_intf_type intf_type, int intf_num, | |
c71716b1 | 190 | enum mdp5_intf_mode intf_mode, struct mdp5_ctl *ctl) |
67ac0a2d SV |
191 | { |
192 | struct drm_device *dev = mdp5_kms->dev; | |
193 | struct msm_drm_private *priv = dev->dev_private; | |
194 | struct drm_encoder *encoder; | |
195 | struct mdp5_interface intf = { | |
196 | .num = intf_num, | |
197 | .type = intf_type, | |
5722a9e3 | 198 | .mode = intf_mode, |
67ac0a2d | 199 | }; |
67ac0a2d | 200 | |
d5af49c9 HL |
201 | if ((intf_type == INTF_DSI) && |
202 | (intf_mode == MDP5_INTF_DSI_MODE_COMMAND)) | |
c71716b1 | 203 | encoder = mdp5_cmd_encoder_init(dev, &intf, ctl); |
d5af49c9 | 204 | else |
c71716b1 | 205 | encoder = mdp5_encoder_init(dev, &intf, ctl); |
d5af49c9 | 206 | |
67ac0a2d | 207 | if (IS_ERR(encoder)) { |
5722a9e3 HL |
208 | dev_err(dev->dev, "failed to construct encoder\n"); |
209 | return encoder; | |
67ac0a2d SV |
210 | } |
211 | ||
212 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
213 | priv->encoders[priv->num_encoders++] = encoder; | |
214 | ||
5722a9e3 HL |
215 | return encoder; |
216 | } | |
217 | ||
d5af49c9 HL |
218 | static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) |
219 | { | |
fe34464d SV |
220 | const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; |
221 | const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); | |
d5af49c9 HL |
222 | int id = 0, i; |
223 | ||
224 | for (i = 0; i < intf_cnt; i++) { | |
225 | if (intfs[i] == INTF_DSI) { | |
226 | if (intf_num == i) | |
227 | return id; | |
228 | ||
229 | id++; | |
230 | } | |
231 | } | |
232 | ||
233 | return -EINVAL; | |
234 | } | |
235 | ||
5722a9e3 HL |
236 | static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) |
237 | { | |
238 | struct drm_device *dev = mdp5_kms->dev; | |
239 | struct msm_drm_private *priv = dev->dev_private; | |
240 | const struct mdp5_cfg_hw *hw_cfg = | |
241 | mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
fe34464d | 242 | enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num]; |
c71716b1 HL |
243 | struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; |
244 | struct mdp5_ctl *ctl; | |
5722a9e3 HL |
245 | struct drm_encoder *encoder; |
246 | int ret = 0; | |
247 | ||
248 | switch (intf_type) { | |
249 | case INTF_DISABLED: | |
250 | break; | |
251 | case INTF_eDP: | |
252 | if (!priv->edp) | |
253 | break; | |
254 | ||
c71716b1 HL |
255 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
256 | if (!ctl) { | |
257 | ret = -EINVAL; | |
258 | break; | |
259 | } | |
260 | ||
5722a9e3 | 261 | encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num, |
c71716b1 | 262 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
263 | if (IS_ERR(encoder)) { |
264 | ret = PTR_ERR(encoder); | |
265 | break; | |
266 | } | |
67ac0a2d | 267 | |
67ac0a2d | 268 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); |
5722a9e3 HL |
269 | break; |
270 | case INTF_HDMI: | |
271 | if (!priv->hdmi) | |
272 | break; | |
273 | ||
c71716b1 HL |
274 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
275 | if (!ctl) { | |
276 | ret = -EINVAL; | |
277 | break; | |
278 | } | |
279 | ||
5722a9e3 | 280 | encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num, |
c71716b1 | 281 | MDP5_INTF_MODE_NONE, ctl); |
5722a9e3 HL |
282 | if (IS_ERR(encoder)) { |
283 | ret = PTR_ERR(encoder); | |
284 | break; | |
285 | } | |
286 | ||
fcda50c8 | 287 | ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); |
5722a9e3 | 288 | break; |
d5af49c9 HL |
289 | case INTF_DSI: |
290 | { | |
291 | int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num); | |
292 | struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM]; | |
293 | enum mdp5_intf_mode mode; | |
294 | int i; | |
295 | ||
296 | if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { | |
297 | dev_err(dev->dev, "failed to find dsi from intf %d\n", | |
298 | intf_num); | |
299 | ret = -EINVAL; | |
300 | break; | |
301 | } | |
302 | ||
303 | if (!priv->dsi[dsi_id]) | |
304 | break; | |
305 | ||
c71716b1 HL |
306 | ctl = mdp5_ctlm_request(ctlm, intf_num); |
307 | if (!ctl) { | |
308 | ret = -EINVAL; | |
309 | break; | |
310 | } | |
311 | ||
d5af49c9 HL |
312 | for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) { |
313 | mode = (i == MSM_DSI_CMD_ENCODER_ID) ? | |
314 | MDP5_INTF_DSI_MODE_COMMAND : | |
315 | MDP5_INTF_DSI_MODE_VIDEO; | |
316 | dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI, | |
c71716b1 HL |
317 | intf_num, mode, ctl); |
318 | if (IS_ERR(dsi_encs[i])) { | |
319 | ret = PTR_ERR(dsi_encs[i]); | |
d5af49c9 HL |
320 | break; |
321 | } | |
322 | } | |
323 | ||
324 | ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs); | |
325 | break; | |
326 | } | |
5722a9e3 HL |
327 | default: |
328 | dev_err(dev->dev, "unknown intf: %d\n", intf_type); | |
329 | ret = -EINVAL; | |
330 | break; | |
67ac0a2d SV |
331 | } |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
06c0dd96 RC |
336 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
337 | { | |
338 | static const enum mdp5_pipe crtcs[] = { | |
3d47fd47 | 339 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, |
06c0dd96 | 340 | }; |
8155ad4c | 341 | static const enum mdp5_pipe vig_planes[] = { |
0deed25b SV |
342 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, |
343 | }; | |
8155ad4c | 344 | static const enum mdp5_pipe dma_planes[] = { |
345 | SSPP_DMA0, SSPP_DMA1, | |
346 | }; | |
06c0dd96 RC |
347 | struct drm_device *dev = mdp5_kms->dev; |
348 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 349 | const struct mdp5_cfg_hw *hw_cfg; |
06c0dd96 RC |
350 | int i, ret; |
351 | ||
42238da8 | 352 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 353 | |
f6a8eaca RC |
354 | /* register our interrupt-controller for hdmi/eDP/dsi/etc |
355 | * to use for irqs routed through mdp: | |
356 | */ | |
357 | ret = mdp5_irq_domain_init(mdp5_kms); | |
358 | if (ret) | |
359 | goto fail; | |
360 | ||
0deed25b | 361 | /* construct CRTCs and their private planes: */ |
2e362e17 | 362 | for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { |
06c0dd96 RC |
363 | struct drm_plane *plane; |
364 | struct drm_crtc *crtc; | |
365 | ||
0deed25b | 366 | plane = mdp5_plane_init(dev, crtcs[i], true, |
3498409f | 367 | hw_cfg->pipe_rgb.base[i], hw_cfg->pipe_rgb.caps); |
06c0dd96 RC |
368 | if (IS_ERR(plane)) { |
369 | ret = PTR_ERR(plane); | |
370 | dev_err(dev->dev, "failed to construct plane for %s (%d)\n", | |
371 | pipe2name(crtcs[i]), ret); | |
372 | goto fail; | |
373 | } | |
374 | ||
375 | crtc = mdp5_crtc_init(dev, plane, i); | |
376 | if (IS_ERR(crtc)) { | |
377 | ret = PTR_ERR(crtc); | |
378 | dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", | |
379 | pipe2name(crtcs[i]), ret); | |
380 | goto fail; | |
381 | } | |
382 | priv->crtcs[priv->num_crtcs++] = crtc; | |
383 | } | |
384 | ||
8155ad4c | 385 | /* Construct video planes: */ |
0deed25b SV |
386 | for (i = 0; i < hw_cfg->pipe_vig.count; i++) { |
387 | struct drm_plane *plane; | |
388 | ||
8155ad4c | 389 | plane = mdp5_plane_init(dev, vig_planes[i], false, |
3498409f | 390 | hw_cfg->pipe_vig.base[i], hw_cfg->pipe_vig.caps); |
0deed25b SV |
391 | if (IS_ERR(plane)) { |
392 | ret = PTR_ERR(plane); | |
393 | dev_err(dev->dev, "failed to construct %s plane: %d\n", | |
8155ad4c | 394 | pipe2name(vig_planes[i]), ret); |
395 | goto fail; | |
396 | } | |
397 | } | |
398 | ||
399 | /* DMA planes */ | |
400 | for (i = 0; i < hw_cfg->pipe_dma.count; i++) { | |
401 | struct drm_plane *plane; | |
402 | ||
403 | plane = mdp5_plane_init(dev, dma_planes[i], false, | |
404 | hw_cfg->pipe_dma.base[i], hw_cfg->pipe_dma.caps); | |
405 | if (IS_ERR(plane)) { | |
406 | ret = PTR_ERR(plane); | |
407 | dev_err(dev->dev, "failed to construct %s plane: %d\n", | |
408 | pipe2name(dma_planes[i]), ret); | |
0deed25b SV |
409 | goto fail; |
410 | } | |
411 | } | |
412 | ||
5722a9e3 HL |
413 | /* Construct encoders and modeset initialize connector devices |
414 | * for each external display interface. | |
415 | */ | |
fe34464d | 416 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { |
5722a9e3 | 417 | ret = modeset_init_intf(mdp5_kms, i); |
67ac0a2d | 418 | if (ret) |
00453981 | 419 | goto fail; |
00453981 HL |
420 | } |
421 | ||
06c0dd96 RC |
422 | return 0; |
423 | ||
424 | fail: | |
425 | return ret; | |
426 | } | |
427 | ||
2e362e17 SV |
428 | static void read_hw_revision(struct mdp5_kms *mdp5_kms, |
429 | uint32_t *major, uint32_t *minor) | |
430 | { | |
431 | uint32_t version; | |
432 | ||
433 | mdp5_enable(mdp5_kms); | |
f5253812 | 434 | version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION); |
2e362e17 SV |
435 | mdp5_disable(mdp5_kms); |
436 | ||
f5253812 SV |
437 | *major = FIELD(version, MDSS_HW_VERSION_MAJOR); |
438 | *minor = FIELD(version, MDSS_HW_VERSION_MINOR); | |
2e362e17 SV |
439 | |
440 | DBG("MDP5 version v%d.%d", *major, *minor); | |
441 | } | |
442 | ||
06c0dd96 | 443 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
d40325b4 | 444 | const char *name, bool mandatory) |
06c0dd96 RC |
445 | { |
446 | struct device *dev = &pdev->dev; | |
447 | struct clk *clk = devm_clk_get(dev, name); | |
d40325b4 | 448 | if (IS_ERR(clk) && mandatory) { |
06c0dd96 RC |
449 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); |
450 | return PTR_ERR(clk); | |
451 | } | |
d40325b4 SV |
452 | if (IS_ERR(clk)) |
453 | DBG("skipping %s", name); | |
454 | else | |
455 | *clkp = clk; | |
456 | ||
06c0dd96 RC |
457 | return 0; |
458 | } | |
459 | ||
e2dd9f9f AT |
460 | static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) |
461 | { | |
462 | struct drm_device *dev = crtc->dev; | |
463 | struct drm_encoder *encoder; | |
464 | ||
465 | drm_for_each_encoder(encoder, dev) | |
466 | if (encoder->crtc == crtc) | |
467 | return encoder; | |
468 | ||
469 | return NULL; | |
470 | } | |
471 | ||
472 | static int mdp5_get_scanoutpos(struct drm_device *dev, unsigned int pipe, | |
473 | unsigned int flags, int *vpos, int *hpos, | |
474 | ktime_t *stime, ktime_t *etime, | |
475 | const struct drm_display_mode *mode) | |
476 | { | |
477 | struct msm_drm_private *priv = dev->dev_private; | |
478 | struct drm_crtc *crtc; | |
479 | struct drm_encoder *encoder; | |
480 | int line, vsw, vbp, vactive_start, vactive_end, vfp_end; | |
481 | int ret = 0; | |
482 | ||
483 | crtc = priv->crtcs[pipe]; | |
484 | if (!crtc) { | |
485 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
486 | return 0; | |
487 | } | |
488 | ||
489 | encoder = get_encoder_from_crtc(crtc); | |
490 | if (!encoder) { | |
491 | DRM_ERROR("no encoder found for crtc %d\n", pipe); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
496 | ||
497 | vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
498 | vbp = mode->crtc_vtotal - mode->crtc_vsync_end; | |
499 | ||
500 | /* | |
501 | * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at | |
502 | * the end of VFP. Translate the porch values relative to the line | |
503 | * counter positions. | |
504 | */ | |
505 | ||
506 | vactive_start = vsw + vbp + 1; | |
507 | ||
508 | vactive_end = vactive_start + mode->crtc_vdisplay; | |
509 | ||
510 | /* last scan line before VSYNC */ | |
511 | vfp_end = mode->crtc_vtotal; | |
512 | ||
513 | if (stime) | |
514 | *stime = ktime_get(); | |
515 | ||
516 | line = mdp5_encoder_get_linecount(encoder); | |
517 | ||
518 | if (line < vactive_start) { | |
519 | line -= vactive_start; | |
520 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
521 | } else if (line > vactive_end) { | |
522 | line = line - vfp_end - vactive_start; | |
523 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
524 | } else { | |
525 | line -= vactive_start; | |
526 | } | |
527 | ||
528 | *vpos = line; | |
529 | *hpos = 0; | |
530 | ||
531 | if (etime) | |
532 | *etime = ktime_get(); | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
537 | static int mdp5_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, | |
538 | int *max_error, | |
539 | struct timeval *vblank_time, | |
540 | unsigned flags) | |
541 | { | |
542 | struct msm_drm_private *priv = dev->dev_private; | |
543 | struct drm_crtc *crtc; | |
544 | ||
545 | if (pipe < 0 || pipe >= priv->num_crtcs) { | |
546 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
550 | crtc = priv->crtcs[pipe]; | |
551 | if (!crtc) { | |
552 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
556 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, | |
557 | vblank_time, flags, | |
558 | &crtc->mode); | |
559 | } | |
560 | ||
561 | static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) | |
562 | { | |
563 | struct msm_drm_private *priv = dev->dev_private; | |
564 | struct drm_crtc *crtc; | |
565 | struct drm_encoder *encoder; | |
566 | ||
567 | if (pipe < 0 || pipe >= priv->num_crtcs) | |
568 | return 0; | |
569 | ||
570 | crtc = priv->crtcs[pipe]; | |
571 | if (!crtc) | |
572 | return 0; | |
573 | ||
574 | encoder = get_encoder_from_crtc(crtc); | |
575 | if (!encoder) | |
576 | return 0; | |
577 | ||
578 | return mdp5_encoder_get_framecount(encoder); | |
579 | } | |
580 | ||
06c0dd96 RC |
581 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) |
582 | { | |
583 | struct platform_device *pdev = dev->platformdev; | |
2e362e17 | 584 | struct mdp5_cfg *config; |
06c0dd96 RC |
585 | struct mdp5_kms *mdp5_kms; |
586 | struct msm_kms *kms = NULL; | |
587 | struct msm_mmu *mmu; | |
2e362e17 | 588 | uint32_t major, minor; |
3d47fd47 | 589 | int i, ret; |
06c0dd96 RC |
590 | |
591 | mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); | |
592 | if (!mdp5_kms) { | |
593 | dev_err(dev->dev, "failed to allocate kms\n"); | |
594 | ret = -ENOMEM; | |
595 | goto fail; | |
596 | } | |
597 | ||
0deed25b SV |
598 | spin_lock_init(&mdp5_kms->resource_lock); |
599 | ||
06c0dd96 RC |
600 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); |
601 | ||
602 | kms = &mdp5_kms->base.base; | |
603 | ||
604 | mdp5_kms->dev = dev; | |
06c0dd96 | 605 | |
f5253812 | 606 | /* mdp5_kms->mmio actually represents the MDSS base address */ |
06c0dd96 RC |
607 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
608 | if (IS_ERR(mdp5_kms->mmio)) { | |
609 | ret = PTR_ERR(mdp5_kms->mmio); | |
610 | goto fail; | |
611 | } | |
612 | ||
613 | mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); | |
614 | if (IS_ERR(mdp5_kms->vbif)) { | |
615 | ret = PTR_ERR(mdp5_kms->vbif); | |
616 | goto fail; | |
617 | } | |
618 | ||
619 | mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); | |
620 | if (IS_ERR(mdp5_kms->vdd)) { | |
621 | ret = PTR_ERR(mdp5_kms->vdd); | |
622 | goto fail; | |
623 | } | |
624 | ||
625 | ret = regulator_enable(mdp5_kms->vdd); | |
626 | if (ret) { | |
627 | dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); | |
628 | goto fail; | |
629 | } | |
630 | ||
d40325b4 SV |
631 | /* mandatory clocks: */ |
632 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true); | |
a0906a02 RC |
633 | if (ret) |
634 | goto fail; | |
d40325b4 | 635 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); |
a0906a02 RC |
636 | if (ret) |
637 | goto fail; | |
d40325b4 | 638 | ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true); |
a0906a02 RC |
639 | if (ret) |
640 | goto fail; | |
d40325b4 | 641 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); |
a0906a02 RC |
642 | if (ret) |
643 | goto fail; | |
d40325b4 | 644 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true); |
06c0dd96 RC |
645 | if (ret) |
646 | goto fail; | |
647 | ||
d40325b4 SV |
648 | /* optional clocks: */ |
649 | get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false); | |
650 | ||
ac7a5704 RC |
651 | /* we need to set a default rate before enabling. Set a safe |
652 | * rate first, then figure out hw revision, and then set a | |
653 | * more optimal rate: | |
654 | */ | |
655 | clk_set_rate(mdp5_kms->src_clk, 200000000); | |
656 | ||
2e362e17 | 657 | read_hw_revision(mdp5_kms, &major, &minor); |
42238da8 RC |
658 | |
659 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
660 | if (IS_ERR(mdp5_kms->cfg)) { | |
661 | ret = PTR_ERR(mdp5_kms->cfg); | |
662 | mdp5_kms->cfg = NULL; | |
3d47fd47 | 663 | goto fail; |
2e362e17 | 664 | } |
42238da8 RC |
665 | |
666 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
d879eb5a | 667 | mdp5_kms->caps = config->hw->mdp.caps; |
3d47fd47 | 668 | |
3f307963 | 669 | /* TODO: compute core clock rate at runtime */ |
2e362e17 | 670 | clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); |
3f307963 | 671 | |
d879eb5a SV |
672 | /* |
673 | * Some chipsets have a Shared Memory Pool (SMP), while others | |
674 | * have dedicated latency buffering per source pipe instead; | |
675 | * this section initializes the SMP: | |
676 | */ | |
677 | if (mdp5_kms->caps & MDP_CAP_SMP) { | |
678 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); | |
679 | if (IS_ERR(mdp5_kms->smp)) { | |
680 | ret = PTR_ERR(mdp5_kms->smp); | |
681 | mdp5_kms->smp = NULL; | |
682 | goto fail; | |
683 | } | |
bfcdfb0e | 684 | } |
bfcdfb0e | 685 | |
b96b3a06 | 686 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); |
42238da8 RC |
687 | if (IS_ERR(mdp5_kms->ctlm)) { |
688 | ret = PTR_ERR(mdp5_kms->ctlm); | |
689 | mdp5_kms->ctlm = NULL; | |
0deed25b SV |
690 | goto fail; |
691 | } | |
0deed25b | 692 | |
06c0dd96 RC |
693 | /* make sure things are off before attaching iommu (bootloader could |
694 | * have left things on, in which case we'll start getting faults if | |
695 | * we don't disable): | |
696 | */ | |
697 | mdp5_enable(mdp5_kms); | |
67ac0a2d | 698 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { |
fe34464d SV |
699 | if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || |
700 | !config->hw->intf.base[i]) | |
67ac0a2d | 701 | continue; |
3d47fd47 | 702 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); |
e2dd9f9f AT |
703 | |
704 | mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); | |
67ac0a2d | 705 | } |
06c0dd96 RC |
706 | mdp5_disable(mdp5_kms); |
707 | mdelay(16); | |
708 | ||
2e362e17 SV |
709 | if (config->platform.iommu) { |
710 | mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); | |
06c0dd96 RC |
711 | if (IS_ERR(mmu)) { |
712 | ret = PTR_ERR(mmu); | |
87e956e9 | 713 | dev_err(dev->dev, "failed to init iommu: %d\n", ret); |
5e921b19 | 714 | iommu_domain_free(config->platform.iommu); |
06c0dd96 RC |
715 | goto fail; |
716 | } | |
87e956e9 | 717 | |
06c0dd96 RC |
718 | ret = mmu->funcs->attach(mmu, iommu_ports, |
719 | ARRAY_SIZE(iommu_ports)); | |
87e956e9 SV |
720 | if (ret) { |
721 | dev_err(dev->dev, "failed to attach iommu: %d\n", ret); | |
722 | mmu->funcs->destroy(mmu); | |
06c0dd96 | 723 | goto fail; |
87e956e9 | 724 | } |
06c0dd96 RC |
725 | } else { |
726 | dev_info(dev->dev, "no iommu, fallback to phys " | |
727 | "contig buffers for scanout\n"); | |
728 | mmu = NULL; | |
729 | } | |
87e956e9 | 730 | mdp5_kms->mmu = mmu; |
06c0dd96 RC |
731 | |
732 | mdp5_kms->id = msm_register_mmu(dev, mmu); | |
733 | if (mdp5_kms->id < 0) { | |
734 | ret = mdp5_kms->id; | |
735 | dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
736 | goto fail; | |
737 | } | |
738 | ||
739 | ret = modeset_init(mdp5_kms); | |
740 | if (ret) { | |
741 | dev_err(dev->dev, "modeset_init failed: %d\n", ret); | |
742 | goto fail; | |
743 | } | |
744 | ||
9b7a9fc2 HL |
745 | dev->mode_config.min_width = 0; |
746 | dev->mode_config.min_height = 0; | |
747 | dev->mode_config.max_width = config->hw->lm.max_width; | |
748 | dev->mode_config.max_height = config->hw->lm.max_height; | |
749 | ||
e2dd9f9f AT |
750 | dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; |
751 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; | |
752 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; | |
753 | dev->max_vblank_count = 0xffffffff; | |
754 | dev->vblank_disable_immediate = true; | |
755 | ||
06c0dd96 RC |
756 | return kms; |
757 | ||
758 | fail: | |
759 | if (kms) | |
760 | mdp5_destroy(kms); | |
761 | return ERR_PTR(ret); | |
762 | } |