[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_kms.c

/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */


#include "msm_drv.h"
#include "msm_mmu.h"
#include "mdp5_kms.h"

static const char *iommu_ports[] = {
		"mdp_0",
};

static int mdp5_hw_init(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct drm_device *dev = mdp5_kms->dev;
	unsigned long flags;

	pm_runtime_get_sync(dev->dev);

	/* Magic unknown register writes:
	 *
	 *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
	 *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
	 *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
	 *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
	 *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
	 *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
	 *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
	 *
	 * Downstream fbdev driver gets these register offsets/values
	 * from DT.. not really sure what these registers are or if
	 * different values for different boards/SoC's, etc.  I guess
	 * they are the golden registers.
	 *
	 * Not setting these does not seem to cause any problem.  But
	 * we may be getting lucky with the bootloader initializing
	 * them for us.  OTOH, if we can always count on the bootloader
	 * setting the golden registers, then perhaps we don't need to
	 * care.
	 */

	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
	mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0);
	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);

	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);

	pm_runtime_put_sync(dev->dev);

	return 0;
}

static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	mdp5_enable(mdp5_kms);
}

static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	mdp5_disable(mdp5_kms);
}

static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
		struct drm_encoder *encoder)
{
	return rate;
}

static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	unsigned i;

	for (i = 0; i < priv->num_crtcs; i++)
		mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
}

static void mdp5_destroy(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_mmu *mmu = mdp5_kms->mmu;

	mdp5_irq_domain_fini(mdp5_kms);

	if (mmu) {
		mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
		mmu->funcs->destroy(mmu);
	}

	if (mdp5_kms->ctlm)
		mdp5_ctlm_destroy(mdp5_kms->ctlm);
	if (mdp5_kms->smp)
		mdp5_smp_destroy(mdp5_kms->smp);
	if (mdp5_kms->cfg)
		mdp5_cfg_destroy(mdp5_kms->cfg);

	kfree(mdp5_kms);
}

static const struct mdp_kms_funcs kms_funcs = {
	.base = {
		.hw_init         = mdp5_hw_init,
		.irq_preinstall  = mdp5_irq_preinstall,
		.irq_postinstall = mdp5_irq_postinstall,
		.irq_uninstall   = mdp5_irq_uninstall,
		.irq             = mdp5_irq,
		.enable_vblank   = mdp5_enable_vblank,
		.disable_vblank  = mdp5_disable_vblank,
		.prepare_commit  = mdp5_prepare_commit,
		.complete_commit = mdp5_complete_commit,
		.get_format      = mdp_get_format,
		.round_pixclk    = mdp5_round_pixclk,
		.preclose        = mdp5_preclose,
		.destroy         = mdp5_destroy,
	},
	.set_irqmask         = mdp5_set_irqmask,
};

int mdp5_disable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_disable_unprepare(mdp5_kms->ahb_clk);
	clk_disable_unprepare(mdp5_kms->axi_clk);
	clk_disable_unprepare(mdp5_kms->core_clk);
	clk_disable_unprepare(mdp5_kms->lut_clk);

	return 0;
}

int mdp5_enable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_prepare_enable(mdp5_kms->ahb_clk);
	clk_prepare_enable(mdp5_kms->axi_clk);
	clk_prepare_enable(mdp5_kms->core_clk);
	clk_prepare_enable(mdp5_kms->lut_clk);

	return 0;
}

static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
		enum mdp5_intf_type intf_type, int intf_num,
		enum mdp5_intf_mode intf_mode)
{
	struct drm_device *dev = mdp5_kms->dev;
	struct msm_drm_private *priv = dev->dev_private;
	struct drm_encoder *encoder;
	struct mdp5_interface intf = {
			.num	= intf_num,
			.type	= intf_type,
			.mode	= intf_mode,
	};

	encoder = mdp5_encoder_init(dev, &intf);
	if (IS_ERR(encoder)) {
		dev_err(dev->dev, "failed to construct encoder\n");
		return encoder;
	}

	encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
	priv->encoders[priv->num_encoders++] = encoder;

	return encoder;
}

static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
{
	struct drm_device *dev = mdp5_kms->dev;
	struct msm_drm_private *priv = dev->dev_private;
	const struct mdp5_cfg_hw *hw_cfg =
					mdp5_cfg_get_hw_config(mdp5_kms->cfg);
	enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num];
	struct drm_encoder *encoder;
	int ret = 0;

	switch (intf_type) {
	case INTF_DISABLED:
		break;
	case INTF_eDP:
		if (!priv->edp)
			break;

		encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num,
					MDP5_INTF_MODE_NONE);
		if (IS_ERR(encoder)) {
			ret = PTR_ERR(encoder);
			break;
		}

		ret = msm_edp_modeset_init(priv->edp, dev, encoder);
		break;
	case INTF_HDMI:
		if (!priv->hdmi)
			break;

		encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num,
					MDP5_INTF_MODE_NONE);
		if (IS_ERR(encoder)) {
			ret = PTR_ERR(encoder);
			break;
		}

		ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
		break;
	default:
		dev_err(dev->dev, "unknown intf: %d\n", intf_type);
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int modeset_init(struct mdp5_kms *mdp5_kms)
{
	static const enum mdp5_pipe crtcs[] = {
			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
	};
	static const enum mdp5_pipe pub_planes[] = {
			SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
	};
	struct drm_device *dev = mdp5_kms->dev;
	struct msm_drm_private *priv = dev->dev_private;
	const struct mdp5_cfg_hw *hw_cfg;
	int i, ret;

	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	 * to use for irqs routed through mdp:
	 */
	ret = mdp5_irq_domain_init(mdp5_kms);
	if (ret)
		goto fail;

	/* construct CRTCs and their private planes: */
	for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
		struct drm_plane *plane;
		struct drm_crtc *crtc;

		plane = mdp5_plane_init(dev, crtcs[i], true,
				hw_cfg->pipe_rgb.base[i]);
		if (IS_ERR(plane)) {
			ret = PTR_ERR(plane);
			dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}

		crtc  = mdp5_crtc_init(dev, plane, i);
		if (IS_ERR(crtc)) {
			ret = PTR_ERR(crtc);
			dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}
		priv->crtcs[priv->num_crtcs++] = crtc;
	}

	/* Construct public planes: */
	for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
		struct drm_plane *plane;

		plane = mdp5_plane_init(dev, pub_planes[i], false,
				hw_cfg->pipe_vig.base[i]);
		if (IS_ERR(plane)) {
			ret = PTR_ERR(plane);
			dev_err(dev->dev, "failed to construct %s plane: %d\n",
					pipe2name(pub_planes[i]), ret);
			goto fail;
		}
	}

	/* Construct encoders and modeset initialize connector devices
	 * for each external display interface.
	 */
	for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) {
		ret = modeset_init_intf(mdp5_kms, i);
		if (ret)
			goto fail;
	}

	return 0;

fail:
	return ret;
}

static void read_hw_revision(struct mdp5_kms *mdp5_kms,
		uint32_t *major, uint32_t *minor)
{
	uint32_t version;

	mdp5_enable(mdp5_kms);
	version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION);
	mdp5_disable(mdp5_kms);

	*major = FIELD(version, MDSS_HW_VERSION_MAJOR);
	*minor = FIELD(version, MDSS_HW_VERSION_MINOR);

	DBG("MDP5 version v%d.%d", *major, *minor);
}

static int get_clk(struct platform_device *pdev, struct clk **clkp,
		const char *name)
{
	struct device *dev = &pdev->dev;
	struct clk *clk = devm_clk_get(dev, name);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	*clkp = clk;
	return 0;
}

struct msm_kms *mdp5_kms_init(struct drm_device *dev)
{
	struct platform_device *pdev = dev->platformdev;
	struct mdp5_cfg *config;
	struct mdp5_kms *mdp5_kms;
	struct msm_kms *kms = NULL;
	struct msm_mmu *mmu;
	uint32_t major, minor;
	int i, ret;

	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	if (!mdp5_kms) {
		dev_err(dev->dev, "failed to allocate kms\n");
		ret = -ENOMEM;
		goto fail;
	}

	spin_lock_init(&mdp5_kms->resource_lock);

	mdp_kms_init(&mdp5_kms->base, &kms_funcs);

	kms = &mdp5_kms->base.base;

	mdp5_kms->dev = dev;

	/* mdp5_kms->mmio actually represents the MDSS base address */
	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	if (IS_ERR(mdp5_kms->mmio)) {
		ret = PTR_ERR(mdp5_kms->mmio);
		goto fail;
	}

	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	if (IS_ERR(mdp5_kms->vbif)) {
		ret = PTR_ERR(mdp5_kms->vbif);
		goto fail;
	}

	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	if (IS_ERR(mdp5_kms->vdd)) {
		ret = PTR_ERR(mdp5_kms->vdd);
		goto fail;
	}

	ret = regulator_enable(mdp5_kms->vdd);
	if (ret) {
		dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
		goto fail;
	}

	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
	if (ret)
		goto fail;

	/* we need to set a default rate before enabling.  Set a safe
	 * rate first, then figure out hw revision, and then set a
	 * more optimal rate:
	 */
	clk_set_rate(mdp5_kms->src_clk, 200000000);

	read_hw_revision(mdp5_kms, &major, &minor);

	mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
	if (IS_ERR(mdp5_kms->cfg)) {
		ret = PTR_ERR(mdp5_kms->cfg);
		mdp5_kms->cfg = NULL;
		goto fail;
	}

	config = mdp5_cfg_get_config(mdp5_kms->cfg);

	/* TODO: compute core clock rate at runtime */
	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);

	mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
	if (IS_ERR(mdp5_kms->smp)) {
		ret = PTR_ERR(mdp5_kms->smp);
		mdp5_kms->smp = NULL;
		goto fail;
	}

	mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
	if (IS_ERR(mdp5_kms->ctlm)) {
		ret = PTR_ERR(mdp5_kms->ctlm);
		mdp5_kms->ctlm = NULL;
		goto fail;
	}

	/* make sure things are off before attaching iommu (bootloader could
	 * have left things on, in which case we'll start getting faults if
	 * we don't disable):
	 */
	mdp5_enable(mdp5_kms);
	for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
		if (!config->hw->intf.base[i] ||
				mdp5_cfg_intf_is_virtual(config->hw->intfs[i]))
			continue;
		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
	}
	mdp5_disable(mdp5_kms);
	mdelay(16);

	if (config->platform.iommu) {
		mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
		if (IS_ERR(mmu)) {
			ret = PTR_ERR(mmu);
			dev_err(dev->dev, "failed to init iommu: %d\n", ret);
			goto fail;
		}

		ret = mmu->funcs->attach(mmu, iommu_ports,
				ARRAY_SIZE(iommu_ports));
		if (ret) {
			dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
			mmu->funcs->destroy(mmu);
			goto fail;
		}
	} else {
		dev_info(dev->dev, "no iommu, fallback to phys "
				"contig buffers for scanout\n");
		mmu = NULL;
	}
	mdp5_kms->mmu = mmu;

	mdp5_kms->id = msm_register_mmu(dev, mmu);
	if (mdp5_kms->id < 0) {
		ret = mdp5_kms->id;
		dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
		goto fail;
	}

	ret = modeset_init(mdp5_kms);
	if (ret) {
		dev_err(dev->dev, "modeset_init failed: %d\n", ret);
		goto fail;
	}

	return kms;

fail:
	if (kms)
		mdp5_destroy(kms);
	return ERR_PTR(ret);
}
Commit	Line	Data
06c0dd96	1	/*
2e362e17	2	* Copyright (c) 2014, The Linux Foundation. All rights reserved.
06c0dd96 RC	3	* Copyright (C) 2013 Red Hat
	4	* Author: Rob Clark <robdclark@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19
	20	#include "msm_drv.h"
	21	#include "msm_mmu.h"
	22	#include "mdp5_kms.h"
	23
87e956e9 SV	24	static const char *iommu_ports[] = {
	25	"mdp_0",
	26	};
	27
3d47fd47 SV	28	static int mdp5_hw_init(struct msm_kms *kms)
	29	{
	30	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	31	struct drm_device *dev = mdp5_kms->dev;
0deed25b	32	unsigned long flags;
3d47fd47 SV	33
	34	pm_runtime_get_sync(dev->dev);
	35
06c0dd96 RC	36	/* Magic unknown register writes:
	37	*
	38	* W VBIF:0x004 00000001 (mdss_mdp.c:839)
	39	* W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
	40	* W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
	41	* W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
	42	* W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
	43	* W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
	44	* W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
	45	* W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
	46	* W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
	47	*
	48	* Downstream fbdev driver gets these register offsets/values
	49	* from DT.. not really sure what these registers are or if
	50	* different values for different boards/SoC's, etc. I guess
	51	* they are the golden registers.
	52	*
	53	* Not setting these does not seem to cause any problem. But
	54	* we may be getting lucky with the bootloader initializing
	55	* them for us. OTOH, if we can always count on the bootloader
	56	* setting the golden registers, then perhaps we don't need to
	57	* care.
	58	*/
	59
0deed25b	60	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
f5253812	61	mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0);
0deed25b	62	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
06c0dd96	63
42238da8	64	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
3d47fd47	65
06c0dd96 RC	66	pm_runtime_put_sync(dev->dev);
06c0dd96 RC	67
3d47fd47	68	return 0;
06c0dd96 RC	69	}
06c0dd96 RC	70
0b776d45 RC	71	static void mdp5_prepare_commit(struct msm_kms kms, struct drm_atomic_state state)
	72	{
	73	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	74	mdp5_enable(mdp5_kms);
	75	}
	76
	77	static void mdp5_complete_commit(struct msm_kms kms, struct drm_atomic_state state)
	78	{
	79	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	80	mdp5_disable(mdp5_kms);
	81	}
	82
06c0dd96 RC	83	static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
	84	struct drm_encoder *encoder)
	85	{
	86	return rate;
	87	}
	88
	89	static void mdp5_preclose(struct msm_kms kms, struct drm_file file)
	90	{
	91	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	92	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	93	unsigned i;
	94
	95	for (i = 0; i < priv->num_crtcs; i++)
	96	mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
	97	}
	98
	99	static void mdp5_destroy(struct msm_kms *kms)
	100	{
	101	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
87e956e9 SV	102	struct msm_mmu *mmu = mdp5_kms->mmu;
87e956e9 SV	103
f6a8eaca RC	104	mdp5_irq_domain_fini(mdp5_kms);
f6a8eaca RC	105
87e956e9 SV	106	if (mmu) {
	107	mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
	108	mmu->funcs->destroy(mmu);
	109	}
42238da8 RC	110
	111	if (mdp5_kms->ctlm)
	112	mdp5_ctlm_destroy(mdp5_kms->ctlm);
	113	if (mdp5_kms->smp)
	114	mdp5_smp_destroy(mdp5_kms->smp);
	115	if (mdp5_kms->cfg)
	116	mdp5_cfg_destroy(mdp5_kms->cfg);
bfcdfb0e	117
06c0dd96 RC	118	kfree(mdp5_kms);
	119	}
	120
	121	static const struct mdp_kms_funcs kms_funcs = {
	122	.base = {
	123	.hw_init = mdp5_hw_init,
	124	.irq_preinstall = mdp5_irq_preinstall,
	125	.irq_postinstall = mdp5_irq_postinstall,
	126	.irq_uninstall = mdp5_irq_uninstall,
	127	.irq = mdp5_irq,
	128	.enable_vblank = mdp5_enable_vblank,
	129	.disable_vblank = mdp5_disable_vblank,
0b776d45 RC	130	.prepare_commit = mdp5_prepare_commit,
0b776d45 RC	131	.complete_commit = mdp5_complete_commit,
06c0dd96 RC	132	.get_format = mdp_get_format,
	133	.round_pixclk = mdp5_round_pixclk,
	134	.preclose = mdp5_preclose,
	135	.destroy = mdp5_destroy,
	136	},
	137	.set_irqmask = mdp5_set_irqmask,
	138	};
	139
	140	int mdp5_disable(struct mdp5_kms *mdp5_kms)
	141	{
	142	DBG("");
	143
	144	clk_disable_unprepare(mdp5_kms->ahb_clk);
	145	clk_disable_unprepare(mdp5_kms->axi_clk);
	146	clk_disable_unprepare(mdp5_kms->core_clk);
	147	clk_disable_unprepare(mdp5_kms->lut_clk);
	148
	149	return 0;
	150	}
	151
	152	int mdp5_enable(struct mdp5_kms *mdp5_kms)
	153	{
	154	DBG("");
	155
	156	clk_prepare_enable(mdp5_kms->ahb_clk);
	157	clk_prepare_enable(mdp5_kms->axi_clk);
	158	clk_prepare_enable(mdp5_kms->core_clk);
	159	clk_prepare_enable(mdp5_kms->lut_clk);
	160
	161	return 0;
	162	}
	163
5722a9e3 HL	164	static struct drm_encoder construct_encoder(struct mdp5_kms mdp5_kms,
	165	enum mdp5_intf_type intf_type, int intf_num,
	166	enum mdp5_intf_mode intf_mode)
67ac0a2d SV	167	{
	168	struct drm_device *dev = mdp5_kms->dev;
	169	struct msm_drm_private *priv = dev->dev_private;
	170	struct drm_encoder *encoder;
	171	struct mdp5_interface intf = {
	172	.num = intf_num,
	173	.type = intf_type,
5722a9e3	174	.mode = intf_mode,
67ac0a2d	175	};
67ac0a2d SV	176
	177	encoder = mdp5_encoder_init(dev, &intf);
	178	if (IS_ERR(encoder)) {
5722a9e3 HL	179	dev_err(dev->dev, "failed to construct encoder\n");
5722a9e3 HL	180	return encoder;
67ac0a2d SV	181	}
	182
	183	encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
	184	priv->encoders[priv->num_encoders++] = encoder;
	185
5722a9e3 HL	186	return encoder;
	187	}
	188
	189	static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
	190	{
	191	struct drm_device *dev = mdp5_kms->dev;
	192	struct msm_drm_private *priv = dev->dev_private;
	193	const struct mdp5_cfg_hw *hw_cfg =
	194	mdp5_cfg_get_hw_config(mdp5_kms->cfg);
	195	enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num];
	196	struct drm_encoder *encoder;
	197	int ret = 0;
	198
	199	switch (intf_type) {
	200	case INTF_DISABLED:
	201	break;
	202	case INTF_eDP:
	203	if (!priv->edp)
	204	break;
	205
	206	encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num,
	207	MDP5_INTF_MODE_NONE);
	208	if (IS_ERR(encoder)) {
	209	ret = PTR_ERR(encoder);
	210	break;
	211	}
67ac0a2d	212
67ac0a2d	213	ret = msm_edp_modeset_init(priv->edp, dev, encoder);
5722a9e3 HL	214	break;
	215	case INTF_HDMI:
	216	if (!priv->hdmi)
	217	break;
	218
	219	encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num,
	220	MDP5_INTF_MODE_NONE);
	221	if (IS_ERR(encoder)) {
	222	ret = PTR_ERR(encoder);
	223	break;
	224	}
	225
	226	ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
	227	break;
	228	default:
	229	dev_err(dev->dev, "unknown intf: %d\n", intf_type);
	230	ret = -EINVAL;
	231	break;
67ac0a2d SV	232	}
	233
	234	return ret;
	235	}
	236
06c0dd96 RC	237	static int modeset_init(struct mdp5_kms *mdp5_kms)
	238	{
	239	static const enum mdp5_pipe crtcs[] = {
3d47fd47	240	SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
06c0dd96	241	};
0deed25b SV	242	static const enum mdp5_pipe pub_planes[] = {
	243	SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
	244	};
06c0dd96 RC	245	struct drm_device *dev = mdp5_kms->dev;
06c0dd96 RC	246	struct msm_drm_private *priv = dev->dev_private;
2e362e17	247	const struct mdp5_cfg_hw *hw_cfg;
06c0dd96 RC	248	int i, ret;
06c0dd96 RC	249
42238da8	250	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
2e362e17	251
f6a8eaca RC	252	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	253	* to use for irqs routed through mdp:
	254	*/
	255	ret = mdp5_irq_domain_init(mdp5_kms);
	256	if (ret)
	257	goto fail;
	258
0deed25b	259	/* construct CRTCs and their private planes: */
2e362e17	260	for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
06c0dd96 RC	261	struct drm_plane *plane;
	262	struct drm_crtc *crtc;
	263
0deed25b SV	264	plane = mdp5_plane_init(dev, crtcs[i], true,
0deed25b SV	265	hw_cfg->pipe_rgb.base[i]);
06c0dd96 RC	266	if (IS_ERR(plane)) {
	267	ret = PTR_ERR(plane);
	268	dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
	269	pipe2name(crtcs[i]), ret);
	270	goto fail;
	271	}
	272
	273	crtc = mdp5_crtc_init(dev, plane, i);
	274	if (IS_ERR(crtc)) {
	275	ret = PTR_ERR(crtc);
	276	dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
	277	pipe2name(crtcs[i]), ret);
	278	goto fail;
	279	}
	280	priv->crtcs[priv->num_crtcs++] = crtc;
	281	}
	282
0deed25b SV	283	/* Construct public planes: */
	284	for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
	285	struct drm_plane *plane;
	286
	287	plane = mdp5_plane_init(dev, pub_planes[i], false,
	288	hw_cfg->pipe_vig.base[i]);
	289	if (IS_ERR(plane)) {
	290	ret = PTR_ERR(plane);
	291	dev_err(dev->dev, "failed to construct %s plane: %d\n",
	292	pipe2name(pub_planes[i]), ret);
	293	goto fail;
	294	}
	295	}
	296
5722a9e3 HL	297	/* Construct encoders and modeset initialize connector devices
	298	* for each external display interface.
	299	*/
67ac0a2d	300	for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) {
5722a9e3	301	ret = modeset_init_intf(mdp5_kms, i);
67ac0a2d	302	if (ret)
00453981	303	goto fail;
00453981 HL	304	}
00453981 HL	305
06c0dd96 RC	306	return 0;
	307
	308	fail:
	309	return ret;
	310	}
	311
2e362e17 SV	312	static void read_hw_revision(struct mdp5_kms *mdp5_kms,
	313	uint32_t major, uint32_t minor)
	314	{
	315	uint32_t version;
	316
	317	mdp5_enable(mdp5_kms);
f5253812	318	version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION);
2e362e17 SV	319	mdp5_disable(mdp5_kms);
2e362e17 SV	320
f5253812 SV	321	*major = FIELD(version, MDSS_HW_VERSION_MAJOR);
f5253812 SV	322	*minor = FIELD(version, MDSS_HW_VERSION_MINOR);
2e362e17 SV	323
	324	DBG("MDP5 version v%d.%d", major, minor);
	325	}
	326
06c0dd96 RC	327	static int get_clk(struct platform_device pdev, struct clk *clkp,
	328	const char *name)
	329	{
	330	struct device *dev = &pdev->dev;
	331	struct clk *clk = devm_clk_get(dev, name);
	332	if (IS_ERR(clk)) {
	333	dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
	334	return PTR_ERR(clk);
	335	}
	336	*clkp = clk;
	337	return 0;
	338	}
	339
	340	struct msm_kms mdp5_kms_init(struct drm_device dev)
	341	{
	342	struct platform_device *pdev = dev->platformdev;
2e362e17	343	struct mdp5_cfg *config;
06c0dd96 RC	344	struct mdp5_kms *mdp5_kms;
	345	struct msm_kms *kms = NULL;
	346	struct msm_mmu *mmu;
2e362e17	347	uint32_t major, minor;
3d47fd47	348	int i, ret;
06c0dd96 RC	349
	350	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	351	if (!mdp5_kms) {
	352	dev_err(dev->dev, "failed to allocate kms\n");
	353	ret = -ENOMEM;
	354	goto fail;
	355	}
	356
0deed25b SV	357	spin_lock_init(&mdp5_kms->resource_lock);
0deed25b SV	358
06c0dd96 RC	359	mdp_kms_init(&mdp5_kms->base, &kms_funcs);
	360
	361	kms = &mdp5_kms->base.base;
	362
	363	mdp5_kms->dev = dev;
06c0dd96	364
f5253812	365	/* mdp5_kms->mmio actually represents the MDSS base address */
06c0dd96 RC	366	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	367	if (IS_ERR(mdp5_kms->mmio)) {
	368	ret = PTR_ERR(mdp5_kms->mmio);
	369	goto fail;
	370	}
	371
	372	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	373	if (IS_ERR(mdp5_kms->vbif)) {
	374	ret = PTR_ERR(mdp5_kms->vbif);
	375	goto fail;
	376	}
	377
	378	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	379	if (IS_ERR(mdp5_kms->vdd)) {
	380	ret = PTR_ERR(mdp5_kms->vdd);
	381	goto fail;
	382	}
	383
	384	ret = regulator_enable(mdp5_kms->vdd);
	385	if (ret) {
	386	dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
	387	goto fail;
	388	}
	389
a0906a02 RC	390	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	391	if (ret)
	392	goto fail;
	393	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	394	if (ret)
	395	goto fail;
	396	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	397	if (ret)
	398	goto fail;
	399	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	400	if (ret)
	401	goto fail;
	402	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	403	if (ret)
	404	goto fail;
	405	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
06c0dd96 RC	406	if (ret)
	407	goto fail;
	408
ac7a5704 RC	409	/* we need to set a default rate before enabling. Set a safe
	410	* rate first, then figure out hw revision, and then set a
	411	* more optimal rate:
	412	*/
	413	clk_set_rate(mdp5_kms->src_clk, 200000000);
	414
2e362e17	415	read_hw_revision(mdp5_kms, &major, &minor);
42238da8 RC	416
	417	mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
	418	if (IS_ERR(mdp5_kms->cfg)) {
	419	ret = PTR_ERR(mdp5_kms->cfg);
	420	mdp5_kms->cfg = NULL;
3d47fd47	421	goto fail;
2e362e17	422	}
42238da8 RC	423
42238da8 RC	424	config = mdp5_cfg_get_config(mdp5_kms->cfg);
3d47fd47	425
3f307963	426	/* TODO: compute core clock rate at runtime */
2e362e17	427	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
3f307963	428
42238da8 RC	429	mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
	430	if (IS_ERR(mdp5_kms->smp)) {
	431	ret = PTR_ERR(mdp5_kms->smp);
	432	mdp5_kms->smp = NULL;
bfcdfb0e SV	433	goto fail;
bfcdfb0e SV	434	}
bfcdfb0e	435
42238da8 RC	436	mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
	437	if (IS_ERR(mdp5_kms->ctlm)) {
	438	ret = PTR_ERR(mdp5_kms->ctlm);
	439	mdp5_kms->ctlm = NULL;
0deed25b SV	440	goto fail;
0deed25b SV	441	}
0deed25b	442
06c0dd96 RC	443	/* make sure things are off before attaching iommu (bootloader could
	444	* have left things on, in which case we'll start getting faults if
	445	* we don't disable):
	446	*/
	447	mdp5_enable(mdp5_kms);
67ac0a2d SV	448	for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
	449	if (!config->hw->intf.base[i] \|\|
	450	mdp5_cfg_intf_is_virtual(config->hw->intfs[i]))
	451	continue;
3d47fd47	452	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
67ac0a2d	453	}
06c0dd96 RC	454	mdp5_disable(mdp5_kms);
	455	mdelay(16);
	456
2e362e17 SV	457	if (config->platform.iommu) {
2e362e17 SV	458	mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
06c0dd96 RC	459	if (IS_ERR(mmu)) {
06c0dd96 RC	460	ret = PTR_ERR(mmu);
87e956e9	461	dev_err(dev->dev, "failed to init iommu: %d\n", ret);
06c0dd96 RC	462	goto fail;
06c0dd96 RC	463	}
87e956e9	464
06c0dd96 RC	465	ret = mmu->funcs->attach(mmu, iommu_ports,
06c0dd96 RC	466	ARRAY_SIZE(iommu_ports));
87e956e9 SV	467	if (ret) {
	468	dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
	469	mmu->funcs->destroy(mmu);
06c0dd96	470	goto fail;
87e956e9	471	}
06c0dd96 RC	472	} else {
	473	dev_info(dev->dev, "no iommu, fallback to phys "
	474	"contig buffers for scanout\n");
	475	mmu = NULL;
	476	}
87e956e9	477	mdp5_kms->mmu = mmu;
06c0dd96 RC	478
	479	mdp5_kms->id = msm_register_mmu(dev, mmu);
	480	if (mdp5_kms->id < 0) {
	481	ret = mdp5_kms->id;
	482	dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
	483	goto fail;
	484	}
	485
	486	ret = modeset_init(mdp5_kms);
	487	if (ret) {
	488	dev_err(dev->dev, "modeset_init failed: %d\n", ret);
	489	goto fail;
	490	}
	491
	492	return kms;
	493
	494	fail:
	495	if (kms)
	496	mdp5_destroy(kms);
	497	return ERR_PTR(ret);
	498	}