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Commit | Line | Data |
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06c0dd96 | 1 | /* |
2e362e17 | 2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | ||
20 | #include "msm_drv.h" | |
21 | #include "msm_mmu.h" | |
22 | #include "mdp5_kms.h" | |
23 | ||
87e956e9 SV |
24 | static const char *iommu_ports[] = { |
25 | "mdp_0", | |
26 | }; | |
27 | ||
3d47fd47 SV |
28 | static int mdp5_hw_init(struct msm_kms *kms) |
29 | { | |
30 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
31 | struct drm_device *dev = mdp5_kms->dev; | |
0deed25b | 32 | unsigned long flags; |
3d47fd47 SV |
33 | |
34 | pm_runtime_get_sync(dev->dev); | |
35 | ||
06c0dd96 RC |
36 | /* Magic unknown register writes: |
37 | * | |
38 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
39 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
40 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
41 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
42 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
43 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
44 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
45 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
46 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
47 | * | |
48 | * Downstream fbdev driver gets these register offsets/values | |
49 | * from DT.. not really sure what these registers are or if | |
50 | * different values for different boards/SoC's, etc. I guess | |
51 | * they are the golden registers. | |
52 | * | |
53 | * Not setting these does not seem to cause any problem. But | |
54 | * we may be getting lucky with the bootloader initializing | |
55 | * them for us. OTOH, if we can always count on the bootloader | |
56 | * setting the golden registers, then perhaps we don't need to | |
57 | * care. | |
58 | */ | |
59 | ||
0deed25b | 60 | spin_lock_irqsave(&mdp5_kms->resource_lock, flags); |
f5253812 | 61 | mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); |
0deed25b | 62 | spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); |
06c0dd96 | 63 | |
42238da8 | 64 | mdp5_ctlm_hw_reset(mdp5_kms->ctlm); |
3d47fd47 | 65 | |
06c0dd96 RC |
66 | pm_runtime_put_sync(dev->dev); |
67 | ||
3d47fd47 | 68 | return 0; |
06c0dd96 RC |
69 | } |
70 | ||
0b776d45 RC |
71 | static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) |
72 | { | |
73 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
74 | mdp5_enable(mdp5_kms); | |
75 | } | |
76 | ||
77 | static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) | |
78 | { | |
79 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
80 | mdp5_disable(mdp5_kms); | |
81 | } | |
82 | ||
0a5c9aad HL |
83 | static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, |
84 | struct drm_crtc *crtc) | |
85 | { | |
86 | mdp5_crtc_wait_for_commit_done(crtc); | |
87 | } | |
88 | ||
06c0dd96 RC |
89 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, |
90 | struct drm_encoder *encoder) | |
91 | { | |
92 | return rate; | |
93 | } | |
94 | ||
d5af49c9 HL |
95 | static int mdp5_set_split_display(struct msm_kms *kms, |
96 | struct drm_encoder *encoder, | |
97 | struct drm_encoder *slave_encoder, | |
98 | bool is_cmd_mode) | |
99 | { | |
100 | if (is_cmd_mode) | |
101 | return mdp5_cmd_encoder_set_split_display(encoder, | |
102 | slave_encoder); | |
103 | else | |
104 | return mdp5_encoder_set_split_display(encoder, slave_encoder); | |
105 | } | |
106 | ||
06c0dd96 RC |
107 | static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file) |
108 | { | |
109 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
110 | struct msm_drm_private *priv = mdp5_kms->dev->dev_private; | |
111 | unsigned i; | |
112 | ||
113 | for (i = 0; i < priv->num_crtcs; i++) | |
114 | mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file); | |
115 | } | |
116 | ||
117 | static void mdp5_destroy(struct msm_kms *kms) | |
118 | { | |
119 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
87e956e9 SV |
120 | struct msm_mmu *mmu = mdp5_kms->mmu; |
121 | ||
f6a8eaca RC |
122 | mdp5_irq_domain_fini(mdp5_kms); |
123 | ||
87e956e9 SV |
124 | if (mmu) { |
125 | mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); | |
126 | mmu->funcs->destroy(mmu); | |
127 | } | |
42238da8 RC |
128 | |
129 | if (mdp5_kms->ctlm) | |
130 | mdp5_ctlm_destroy(mdp5_kms->ctlm); | |
131 | if (mdp5_kms->smp) | |
132 | mdp5_smp_destroy(mdp5_kms->smp); | |
133 | if (mdp5_kms->cfg) | |
134 | mdp5_cfg_destroy(mdp5_kms->cfg); | |
bfcdfb0e | 135 | |
06c0dd96 RC |
136 | kfree(mdp5_kms); |
137 | } | |
138 | ||
139 | static const struct mdp_kms_funcs kms_funcs = { | |
140 | .base = { | |
141 | .hw_init = mdp5_hw_init, | |
142 | .irq_preinstall = mdp5_irq_preinstall, | |
143 | .irq_postinstall = mdp5_irq_postinstall, | |
144 | .irq_uninstall = mdp5_irq_uninstall, | |
145 | .irq = mdp5_irq, | |
146 | .enable_vblank = mdp5_enable_vblank, | |
147 | .disable_vblank = mdp5_disable_vblank, | |
0b776d45 RC |
148 | .prepare_commit = mdp5_prepare_commit, |
149 | .complete_commit = mdp5_complete_commit, | |
0a5c9aad | 150 | .wait_for_crtc_commit_done = mdp5_wait_for_crtc_commit_done, |
06c0dd96 RC |
151 | .get_format = mdp_get_format, |
152 | .round_pixclk = mdp5_round_pixclk, | |
d5af49c9 | 153 | .set_split_display = mdp5_set_split_display, |
06c0dd96 RC |
154 | .preclose = mdp5_preclose, |
155 | .destroy = mdp5_destroy, | |
156 | }, | |
157 | .set_irqmask = mdp5_set_irqmask, | |
158 | }; | |
159 | ||
160 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
161 | { | |
162 | DBG(""); | |
163 | ||
164 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
165 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
166 | clk_disable_unprepare(mdp5_kms->core_clk); | |
167 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
173 | { | |
174 | DBG(""); | |
175 | ||
176 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
177 | clk_prepare_enable(mdp5_kms->axi_clk); | |
178 | clk_prepare_enable(mdp5_kms->core_clk); | |
179 | clk_prepare_enable(mdp5_kms->lut_clk); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
5722a9e3 HL |
184 | static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, |
185 | enum mdp5_intf_type intf_type, int intf_num, | |
186 | enum mdp5_intf_mode intf_mode) | |
67ac0a2d SV |
187 | { |
188 | struct drm_device *dev = mdp5_kms->dev; | |
189 | struct msm_drm_private *priv = dev->dev_private; | |
190 | struct drm_encoder *encoder; | |
191 | struct mdp5_interface intf = { | |
192 | .num = intf_num, | |
193 | .type = intf_type, | |
5722a9e3 | 194 | .mode = intf_mode, |
67ac0a2d | 195 | }; |
67ac0a2d | 196 | |
d5af49c9 HL |
197 | if ((intf_type == INTF_DSI) && |
198 | (intf_mode == MDP5_INTF_DSI_MODE_COMMAND)) | |
199 | encoder = mdp5_cmd_encoder_init(dev, &intf); | |
200 | else | |
201 | encoder = mdp5_encoder_init(dev, &intf); | |
202 | ||
67ac0a2d | 203 | if (IS_ERR(encoder)) { |
5722a9e3 HL |
204 | dev_err(dev->dev, "failed to construct encoder\n"); |
205 | return encoder; | |
67ac0a2d SV |
206 | } |
207 | ||
208 | encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; | |
209 | priv->encoders[priv->num_encoders++] = encoder; | |
210 | ||
5722a9e3 HL |
211 | return encoder; |
212 | } | |
213 | ||
d5af49c9 HL |
214 | static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) |
215 | { | |
fe34464d SV |
216 | const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; |
217 | const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); | |
d5af49c9 HL |
218 | int id = 0, i; |
219 | ||
220 | for (i = 0; i < intf_cnt; i++) { | |
221 | if (intfs[i] == INTF_DSI) { | |
222 | if (intf_num == i) | |
223 | return id; | |
224 | ||
225 | id++; | |
226 | } | |
227 | } | |
228 | ||
229 | return -EINVAL; | |
230 | } | |
231 | ||
5722a9e3 HL |
232 | static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) |
233 | { | |
234 | struct drm_device *dev = mdp5_kms->dev; | |
235 | struct msm_drm_private *priv = dev->dev_private; | |
236 | const struct mdp5_cfg_hw *hw_cfg = | |
237 | mdp5_cfg_get_hw_config(mdp5_kms->cfg); | |
fe34464d | 238 | enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num]; |
5722a9e3 HL |
239 | struct drm_encoder *encoder; |
240 | int ret = 0; | |
241 | ||
242 | switch (intf_type) { | |
243 | case INTF_DISABLED: | |
244 | break; | |
245 | case INTF_eDP: | |
246 | if (!priv->edp) | |
247 | break; | |
248 | ||
249 | encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num, | |
250 | MDP5_INTF_MODE_NONE); | |
251 | if (IS_ERR(encoder)) { | |
252 | ret = PTR_ERR(encoder); | |
253 | break; | |
254 | } | |
67ac0a2d | 255 | |
67ac0a2d | 256 | ret = msm_edp_modeset_init(priv->edp, dev, encoder); |
5722a9e3 HL |
257 | break; |
258 | case INTF_HDMI: | |
259 | if (!priv->hdmi) | |
260 | break; | |
261 | ||
262 | encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num, | |
263 | MDP5_INTF_MODE_NONE); | |
264 | if (IS_ERR(encoder)) { | |
265 | ret = PTR_ERR(encoder); | |
266 | break; | |
267 | } | |
268 | ||
269 | ret = hdmi_modeset_init(priv->hdmi, dev, encoder); | |
270 | break; | |
d5af49c9 HL |
271 | case INTF_DSI: |
272 | { | |
273 | int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num); | |
274 | struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM]; | |
275 | enum mdp5_intf_mode mode; | |
276 | int i; | |
277 | ||
278 | if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { | |
279 | dev_err(dev->dev, "failed to find dsi from intf %d\n", | |
280 | intf_num); | |
281 | ret = -EINVAL; | |
282 | break; | |
283 | } | |
284 | ||
285 | if (!priv->dsi[dsi_id]) | |
286 | break; | |
287 | ||
288 | for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) { | |
289 | mode = (i == MSM_DSI_CMD_ENCODER_ID) ? | |
290 | MDP5_INTF_DSI_MODE_COMMAND : | |
291 | MDP5_INTF_DSI_MODE_VIDEO; | |
292 | dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI, | |
293 | intf_num, mode); | |
294 | if (IS_ERR(dsi_encs)) { | |
295 | ret = PTR_ERR(dsi_encs); | |
296 | break; | |
297 | } | |
298 | } | |
299 | ||
300 | ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs); | |
301 | break; | |
302 | } | |
5722a9e3 HL |
303 | default: |
304 | dev_err(dev->dev, "unknown intf: %d\n", intf_type); | |
305 | ret = -EINVAL; | |
306 | break; | |
67ac0a2d SV |
307 | } |
308 | ||
309 | return ret; | |
310 | } | |
311 | ||
06c0dd96 RC |
312 | static int modeset_init(struct mdp5_kms *mdp5_kms) |
313 | { | |
314 | static const enum mdp5_pipe crtcs[] = { | |
3d47fd47 | 315 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, |
06c0dd96 | 316 | }; |
0deed25b SV |
317 | static const enum mdp5_pipe pub_planes[] = { |
318 | SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, | |
319 | }; | |
06c0dd96 RC |
320 | struct drm_device *dev = mdp5_kms->dev; |
321 | struct msm_drm_private *priv = dev->dev_private; | |
2e362e17 | 322 | const struct mdp5_cfg_hw *hw_cfg; |
06c0dd96 RC |
323 | int i, ret; |
324 | ||
42238da8 | 325 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
2e362e17 | 326 | |
f6a8eaca RC |
327 | /* register our interrupt-controller for hdmi/eDP/dsi/etc |
328 | * to use for irqs routed through mdp: | |
329 | */ | |
330 | ret = mdp5_irq_domain_init(mdp5_kms); | |
331 | if (ret) | |
332 | goto fail; | |
333 | ||
0deed25b | 334 | /* construct CRTCs and their private planes: */ |
2e362e17 | 335 | for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { |
06c0dd96 RC |
336 | struct drm_plane *plane; |
337 | struct drm_crtc *crtc; | |
338 | ||
0deed25b SV |
339 | plane = mdp5_plane_init(dev, crtcs[i], true, |
340 | hw_cfg->pipe_rgb.base[i]); | |
06c0dd96 RC |
341 | if (IS_ERR(plane)) { |
342 | ret = PTR_ERR(plane); | |
343 | dev_err(dev->dev, "failed to construct plane for %s (%d)\n", | |
344 | pipe2name(crtcs[i]), ret); | |
345 | goto fail; | |
346 | } | |
347 | ||
348 | crtc = mdp5_crtc_init(dev, plane, i); | |
349 | if (IS_ERR(crtc)) { | |
350 | ret = PTR_ERR(crtc); | |
351 | dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", | |
352 | pipe2name(crtcs[i]), ret); | |
353 | goto fail; | |
354 | } | |
355 | priv->crtcs[priv->num_crtcs++] = crtc; | |
356 | } | |
357 | ||
0deed25b SV |
358 | /* Construct public planes: */ |
359 | for (i = 0; i < hw_cfg->pipe_vig.count; i++) { | |
360 | struct drm_plane *plane; | |
361 | ||
362 | plane = mdp5_plane_init(dev, pub_planes[i], false, | |
363 | hw_cfg->pipe_vig.base[i]); | |
364 | if (IS_ERR(plane)) { | |
365 | ret = PTR_ERR(plane); | |
366 | dev_err(dev->dev, "failed to construct %s plane: %d\n", | |
367 | pipe2name(pub_planes[i]), ret); | |
368 | goto fail; | |
369 | } | |
370 | } | |
371 | ||
5722a9e3 HL |
372 | /* Construct encoders and modeset initialize connector devices |
373 | * for each external display interface. | |
374 | */ | |
fe34464d | 375 | for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { |
5722a9e3 | 376 | ret = modeset_init_intf(mdp5_kms, i); |
67ac0a2d | 377 | if (ret) |
00453981 | 378 | goto fail; |
00453981 HL |
379 | } |
380 | ||
06c0dd96 RC |
381 | return 0; |
382 | ||
383 | fail: | |
384 | return ret; | |
385 | } | |
386 | ||
2e362e17 SV |
387 | static void read_hw_revision(struct mdp5_kms *mdp5_kms, |
388 | uint32_t *major, uint32_t *minor) | |
389 | { | |
390 | uint32_t version; | |
391 | ||
392 | mdp5_enable(mdp5_kms); | |
f5253812 | 393 | version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION); |
2e362e17 SV |
394 | mdp5_disable(mdp5_kms); |
395 | ||
f5253812 SV |
396 | *major = FIELD(version, MDSS_HW_VERSION_MAJOR); |
397 | *minor = FIELD(version, MDSS_HW_VERSION_MINOR); | |
2e362e17 SV |
398 | |
399 | DBG("MDP5 version v%d.%d", *major, *minor); | |
400 | } | |
401 | ||
06c0dd96 RC |
402 | static int get_clk(struct platform_device *pdev, struct clk **clkp, |
403 | const char *name) | |
404 | { | |
405 | struct device *dev = &pdev->dev; | |
406 | struct clk *clk = devm_clk_get(dev, name); | |
407 | if (IS_ERR(clk)) { | |
408 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); | |
409 | return PTR_ERR(clk); | |
410 | } | |
411 | *clkp = clk; | |
412 | return 0; | |
413 | } | |
414 | ||
415 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) | |
416 | { | |
417 | struct platform_device *pdev = dev->platformdev; | |
2e362e17 | 418 | struct mdp5_cfg *config; |
06c0dd96 RC |
419 | struct mdp5_kms *mdp5_kms; |
420 | struct msm_kms *kms = NULL; | |
421 | struct msm_mmu *mmu; | |
2e362e17 | 422 | uint32_t major, minor; |
3d47fd47 | 423 | int i, ret; |
06c0dd96 RC |
424 | |
425 | mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); | |
426 | if (!mdp5_kms) { | |
427 | dev_err(dev->dev, "failed to allocate kms\n"); | |
428 | ret = -ENOMEM; | |
429 | goto fail; | |
430 | } | |
431 | ||
0deed25b SV |
432 | spin_lock_init(&mdp5_kms->resource_lock); |
433 | ||
06c0dd96 RC |
434 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); |
435 | ||
436 | kms = &mdp5_kms->base.base; | |
437 | ||
438 | mdp5_kms->dev = dev; | |
06c0dd96 | 439 | |
f5253812 | 440 | /* mdp5_kms->mmio actually represents the MDSS base address */ |
06c0dd96 RC |
441 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); |
442 | if (IS_ERR(mdp5_kms->mmio)) { | |
443 | ret = PTR_ERR(mdp5_kms->mmio); | |
444 | goto fail; | |
445 | } | |
446 | ||
447 | mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); | |
448 | if (IS_ERR(mdp5_kms->vbif)) { | |
449 | ret = PTR_ERR(mdp5_kms->vbif); | |
450 | goto fail; | |
451 | } | |
452 | ||
453 | mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); | |
454 | if (IS_ERR(mdp5_kms->vdd)) { | |
455 | ret = PTR_ERR(mdp5_kms->vdd); | |
456 | goto fail; | |
457 | } | |
458 | ||
459 | ret = regulator_enable(mdp5_kms->vdd); | |
460 | if (ret) { | |
461 | dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); | |
462 | goto fail; | |
463 | } | |
464 | ||
a0906a02 RC |
465 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); |
466 | if (ret) | |
467 | goto fail; | |
468 | ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); | |
469 | if (ret) | |
470 | goto fail; | |
471 | ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); | |
472 | if (ret) | |
473 | goto fail; | |
474 | ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); | |
475 | if (ret) | |
476 | goto fail; | |
477 | ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); | |
478 | if (ret) | |
479 | goto fail; | |
480 | ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk"); | |
06c0dd96 RC |
481 | if (ret) |
482 | goto fail; | |
483 | ||
ac7a5704 RC |
484 | /* we need to set a default rate before enabling. Set a safe |
485 | * rate first, then figure out hw revision, and then set a | |
486 | * more optimal rate: | |
487 | */ | |
488 | clk_set_rate(mdp5_kms->src_clk, 200000000); | |
489 | ||
2e362e17 | 490 | read_hw_revision(mdp5_kms, &major, &minor); |
42238da8 RC |
491 | |
492 | mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); | |
493 | if (IS_ERR(mdp5_kms->cfg)) { | |
494 | ret = PTR_ERR(mdp5_kms->cfg); | |
495 | mdp5_kms->cfg = NULL; | |
3d47fd47 | 496 | goto fail; |
2e362e17 | 497 | } |
42238da8 RC |
498 | |
499 | config = mdp5_cfg_get_config(mdp5_kms->cfg); | |
3d47fd47 | 500 | |
3f307963 | 501 | /* TODO: compute core clock rate at runtime */ |
2e362e17 | 502 | clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); |
3f307963 | 503 | |
42238da8 RC |
504 | mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); |
505 | if (IS_ERR(mdp5_kms->smp)) { | |
506 | ret = PTR_ERR(mdp5_kms->smp); | |
507 | mdp5_kms->smp = NULL; | |
bfcdfb0e SV |
508 | goto fail; |
509 | } | |
bfcdfb0e | 510 | |
42238da8 RC |
511 | mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw); |
512 | if (IS_ERR(mdp5_kms->ctlm)) { | |
513 | ret = PTR_ERR(mdp5_kms->ctlm); | |
514 | mdp5_kms->ctlm = NULL; | |
0deed25b SV |
515 | goto fail; |
516 | } | |
0deed25b | 517 | |
06c0dd96 RC |
518 | /* make sure things are off before attaching iommu (bootloader could |
519 | * have left things on, in which case we'll start getting faults if | |
520 | * we don't disable): | |
521 | */ | |
522 | mdp5_enable(mdp5_kms); | |
67ac0a2d | 523 | for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { |
fe34464d SV |
524 | if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || |
525 | !config->hw->intf.base[i]) | |
67ac0a2d | 526 | continue; |
3d47fd47 | 527 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); |
67ac0a2d | 528 | } |
06c0dd96 RC |
529 | mdp5_disable(mdp5_kms); |
530 | mdelay(16); | |
531 | ||
2e362e17 SV |
532 | if (config->platform.iommu) { |
533 | mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); | |
06c0dd96 RC |
534 | if (IS_ERR(mmu)) { |
535 | ret = PTR_ERR(mmu); | |
87e956e9 | 536 | dev_err(dev->dev, "failed to init iommu: %d\n", ret); |
06c0dd96 RC |
537 | goto fail; |
538 | } | |
87e956e9 | 539 | |
06c0dd96 RC |
540 | ret = mmu->funcs->attach(mmu, iommu_ports, |
541 | ARRAY_SIZE(iommu_ports)); | |
87e956e9 SV |
542 | if (ret) { |
543 | dev_err(dev->dev, "failed to attach iommu: %d\n", ret); | |
544 | mmu->funcs->destroy(mmu); | |
06c0dd96 | 545 | goto fail; |
87e956e9 | 546 | } |
06c0dd96 RC |
547 | } else { |
548 | dev_info(dev->dev, "no iommu, fallback to phys " | |
549 | "contig buffers for scanout\n"); | |
550 | mmu = NULL; | |
551 | } | |
87e956e9 | 552 | mdp5_kms->mmu = mmu; |
06c0dd96 RC |
553 | |
554 | mdp5_kms->id = msm_register_mmu(dev, mmu); | |
555 | if (mdp5_kms->id < 0) { | |
556 | ret = mdp5_kms->id; | |
557 | dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
558 | goto fail; | |
559 | } | |
560 | ||
561 | ret = modeset_init(mdp5_kms); | |
562 | if (ret) { | |
563 | dev_err(dev->dev, "modeset_init failed: %d\n", ret); | |
564 | goto fail; | |
565 | } | |
566 | ||
567 | return kms; | |
568 | ||
569 | fail: | |
570 | if (kms) | |
571 | mdp5_destroy(kms); | |
572 | return ERR_PTR(ret); | |
573 | } |