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Commit | Line | Data |
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06c0dd96 | 1 | /* |
bef799fb | 2 | * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
dd701ae9 | 19 | #include <drm/drm_print.h> |
06c0dd96 RC |
20 | #include "mdp5_kms.h" |
21 | ||
06c0dd96 RC |
22 | struct mdp5_plane { |
23 | struct drm_plane base; | |
06c0dd96 | 24 | |
01f8a969 AT |
25 | spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */ |
26 | ||
06c0dd96 RC |
27 | uint32_t nformats; |
28 | uint32_t formats[32]; | |
06c0dd96 RC |
29 | }; |
30 | #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base) | |
31 | ||
ed851963 RC |
32 | static int mdp5_plane_mode_set(struct drm_plane *plane, |
33 | struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3b6acf14 | 34 | struct drm_rect *src, struct drm_rect *dest); |
bef799fb | 35 | |
10967a06 AT |
36 | static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane, |
37 | struct drm_crtc *crtc, | |
38 | struct drm_framebuffer *fb, | |
39 | int crtc_x, int crtc_y, | |
40 | unsigned int crtc_w, unsigned int crtc_h, | |
41 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
42 | uint32_t src_w, uint32_t src_h, |
43 | struct drm_modeset_acquire_ctx *ctx); | |
10967a06 | 44 | |
06c0dd96 RC |
45 | static struct mdp5_kms *get_kms(struct drm_plane *plane) |
46 | { | |
47 | struct msm_drm_private *priv = plane->dev->dev_private; | |
48 | return to_mdp5_kms(to_mdp_kms(priv->kms)); | |
49 | } | |
50 | ||
ed851963 | 51 | static bool plane_enabled(struct drm_plane_state *state) |
06c0dd96 | 52 | { |
3b6acf14 | 53 | return state->visible; |
06c0dd96 RC |
54 | } |
55 | ||
06c0dd96 RC |
56 | static void mdp5_plane_destroy(struct drm_plane *plane) |
57 | { | |
58 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); | |
59 | ||
ed851963 | 60 | drm_plane_helper_disable(plane); |
06c0dd96 RC |
61 | drm_plane_cleanup(plane); |
62 | ||
63 | kfree(mdp5_plane); | |
64 | } | |
65 | ||
8089082f | 66 | static void mdp5_plane_install_rotation_property(struct drm_device *dev, |
67 | struct drm_plane *plane) | |
68 | { | |
5b560c3a VS |
69 | drm_plane_create_rotation_property(plane, |
70 | DRM_ROTATE_0, | |
71 | DRM_ROTATE_0 | | |
574a37b1 | 72 | DRM_ROTATE_180 | |
5b560c3a VS |
73 | DRM_REFLECT_X | |
74 | DRM_REFLECT_Y); | |
8089082f | 75 | } |
76 | ||
06c0dd96 | 77 | /* helper to install properties which are common to planes and crtcs */ |
4ff696ea | 78 | static void mdp5_plane_install_properties(struct drm_plane *plane, |
06c0dd96 RC |
79 | struct drm_mode_object *obj) |
80 | { | |
12987781 | 81 | struct drm_device *dev = plane->dev; |
82 | struct msm_drm_private *dev_priv = dev->dev_private; | |
83 | struct drm_property *prop; | |
84 | ||
85 | #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ | |
86 | prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ | |
87 | if (!prop) { \ | |
88 | prop = drm_property_##fnc(dev, 0, #name, \ | |
89 | ##__VA_ARGS__); \ | |
90 | if (!prop) { \ | |
91 | dev_warn(dev->dev, \ | |
92 | "Create property %s failed\n", \ | |
93 | #name); \ | |
94 | return; \ | |
95 | } \ | |
96 | dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ | |
97 | } \ | |
98 | drm_object_attach_property(&plane->base, prop, init_val); \ | |
99 | } while (0) | |
100 | ||
101 | #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ | |
102 | INSTALL_PROPERTY(name, NAME, init_val, \ | |
103 | create_range, min, max) | |
104 | ||
105 | #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ | |
106 | INSTALL_PROPERTY(name, NAME, init_val, \ | |
107 | create_enum, name##_prop_enum_list, \ | |
108 | ARRAY_SIZE(name##_prop_enum_list)) | |
109 | ||
110 | INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); | |
111 | ||
8089082f | 112 | mdp5_plane_install_rotation_property(dev, plane); |
113 | ||
12987781 | 114 | #undef INSTALL_RANGE_PROPERTY |
115 | #undef INSTALL_ENUM_PROPERTY | |
116 | #undef INSTALL_PROPERTY | |
06c0dd96 RC |
117 | } |
118 | ||
12987781 | 119 | static int mdp5_plane_atomic_set_property(struct drm_plane *plane, |
120 | struct drm_plane_state *state, struct drm_property *property, | |
121 | uint64_t val) | |
122 | { | |
123 | struct drm_device *dev = plane->dev; | |
124 | struct mdp5_plane_state *pstate; | |
125 | struct msm_drm_private *dev_priv = dev->dev_private; | |
126 | int ret = 0; | |
127 | ||
128 | pstate = to_mdp5_plane_state(state); | |
129 | ||
130 | #define SET_PROPERTY(name, NAME, type) do { \ | |
131 | if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ | |
132 | pstate->name = (type)val; \ | |
133 | DBG("Set property %s %d", #name, (type)val); \ | |
134 | goto done; \ | |
135 | } \ | |
136 | } while (0) | |
137 | ||
138 | SET_PROPERTY(zpos, ZPOS, uint8_t); | |
139 | ||
140 | dev_err(dev->dev, "Invalid property\n"); | |
141 | ret = -EINVAL; | |
142 | done: | |
143 | return ret; | |
144 | #undef SET_PROPERTY | |
145 | } | |
146 | ||
12987781 | 147 | static int mdp5_plane_atomic_get_property(struct drm_plane *plane, |
148 | const struct drm_plane_state *state, | |
149 | struct drm_property *property, uint64_t *val) | |
150 | { | |
151 | struct drm_device *dev = plane->dev; | |
152 | struct mdp5_plane_state *pstate; | |
153 | struct msm_drm_private *dev_priv = dev->dev_private; | |
154 | int ret = 0; | |
155 | ||
156 | pstate = to_mdp5_plane_state(state); | |
157 | ||
158 | #define GET_PROPERTY(name, NAME, type) do { \ | |
159 | if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ | |
160 | *val = pstate->name; \ | |
161 | DBG("Get property %s %lld", #name, *val); \ | |
162 | goto done; \ | |
163 | } \ | |
164 | } while (0) | |
165 | ||
166 | GET_PROPERTY(zpos, ZPOS, uint8_t); | |
167 | ||
168 | dev_err(dev->dev, "Invalid property\n"); | |
169 | ret = -EINVAL; | |
170 | done: | |
171 | return ret; | |
172 | #undef SET_PROPERTY | |
06c0dd96 RC |
173 | } |
174 | ||
dd701ae9 RC |
175 | static void |
176 | mdp5_plane_atomic_print_state(struct drm_printer *p, | |
177 | const struct drm_plane_state *state) | |
178 | { | |
179 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); | |
7a10ee9b | 180 | struct mdp5_kms *mdp5_kms = get_kms(state->plane); |
dd701ae9 | 181 | |
4a0f012d RC |
182 | drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? |
183 | pstate->hwpipe->name : "(null)"); | |
7a10ee9b AT |
184 | if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) |
185 | drm_printf(p, "\tright-hwpipe=%s\n", | |
186 | pstate->r_hwpipe ? pstate->r_hwpipe->name : | |
187 | "(null)"); | |
dd701ae9 RC |
188 | drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); |
189 | drm_printf(p, "\tzpos=%u\n", pstate->zpos); | |
190 | drm_printf(p, "\talpha=%u\n", pstate->alpha); | |
191 | drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); | |
dd701ae9 RC |
192 | } |
193 | ||
ed851963 RC |
194 | static void mdp5_plane_reset(struct drm_plane *plane) |
195 | { | |
196 | struct mdp5_plane_state *mdp5_state; | |
197 | ||
198 | if (plane->state && plane->state->fb) | |
199 | drm_framebuffer_unreference(plane->state->fb); | |
200 | ||
201 | kfree(to_mdp5_plane_state(plane->state)); | |
202 | mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); | |
203 | ||
12987781 | 204 | /* assign default blend parameters */ |
205 | mdp5_state->alpha = 255; | |
206 | mdp5_state->premultiplied = 0; | |
207 | ||
208 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) | |
209 | mdp5_state->zpos = STAGE_BASE; | |
210 | else | |
211 | mdp5_state->zpos = STAGE0 + drm_plane_index(plane); | |
212 | ||
07cc0ef6 | 213 | mdp5_state->base.plane = plane; |
ed851963 RC |
214 | |
215 | plane->state = &mdp5_state->base; | |
216 | } | |
217 | ||
218 | static struct drm_plane_state * | |
219 | mdp5_plane_duplicate_state(struct drm_plane *plane) | |
220 | { | |
221 | struct mdp5_plane_state *mdp5_state; | |
222 | ||
223 | if (WARN_ON(!plane->state)) | |
224 | return NULL; | |
225 | ||
226 | mdp5_state = kmemdup(to_mdp5_plane_state(plane->state), | |
227 | sizeof(*mdp5_state), GFP_KERNEL); | |
786813c3 RC |
228 | if (!mdp5_state) |
229 | return NULL; | |
ed851963 | 230 | |
786813c3 | 231 | __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); |
ed851963 | 232 | |
ed851963 RC |
233 | return &mdp5_state->base; |
234 | } | |
235 | ||
236 | static void mdp5_plane_destroy_state(struct drm_plane *plane, | |
237 | struct drm_plane_state *state) | |
238 | { | |
4a0f012d RC |
239 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); |
240 | ||
ed851963 RC |
241 | if (state->fb) |
242 | drm_framebuffer_unreference(state->fb); | |
243 | ||
4a0f012d | 244 | kfree(pstate); |
ed851963 RC |
245 | } |
246 | ||
06c0dd96 | 247 | static const struct drm_plane_funcs mdp5_plane_funcs = { |
ed851963 RC |
248 | .update_plane = drm_atomic_helper_update_plane, |
249 | .disable_plane = drm_atomic_helper_disable_plane, | |
06c0dd96 | 250 | .destroy = mdp5_plane_destroy, |
8089082f | 251 | .set_property = drm_atomic_helper_plane_set_property, |
12987781 | 252 | .atomic_set_property = mdp5_plane_atomic_set_property, |
253 | .atomic_get_property = mdp5_plane_atomic_get_property, | |
ed851963 RC |
254 | .reset = mdp5_plane_reset, |
255 | .atomic_duplicate_state = mdp5_plane_duplicate_state, | |
256 | .atomic_destroy_state = mdp5_plane_destroy_state, | |
dd701ae9 | 257 | .atomic_print_state = mdp5_plane_atomic_print_state, |
06c0dd96 RC |
258 | }; |
259 | ||
10967a06 AT |
260 | static const struct drm_plane_funcs mdp5_cursor_plane_funcs = { |
261 | .update_plane = mdp5_update_cursor_plane_legacy, | |
262 | .disable_plane = drm_atomic_helper_disable_plane, | |
263 | .destroy = mdp5_plane_destroy, | |
264 | .set_property = drm_atomic_helper_plane_set_property, | |
265 | .atomic_set_property = mdp5_plane_atomic_set_property, | |
266 | .atomic_get_property = mdp5_plane_atomic_get_property, | |
267 | .reset = mdp5_plane_reset, | |
268 | .atomic_duplicate_state = mdp5_plane_duplicate_state, | |
269 | .atomic_destroy_state = mdp5_plane_destroy_state, | |
270 | .atomic_print_state = mdp5_plane_atomic_print_state, | |
271 | }; | |
272 | ||
ed851963 | 273 | static int mdp5_plane_prepare_fb(struct drm_plane *plane, |
1832040d | 274 | struct drm_plane_state *new_state) |
06c0dd96 | 275 | { |
06c0dd96 | 276 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
844f9111 ML |
277 | struct drm_framebuffer *fb = new_state->fb; |
278 | ||
279 | if (!new_state->fb) | |
280 | return 0; | |
06c0dd96 | 281 | |
0002d30f | 282 | DBG("%s: prepare: FB[%u]", plane->name, fb->base.id); |
ed851963 | 283 | return msm_framebuffer_prepare(fb, mdp5_kms->id); |
0deed25b SV |
284 | } |
285 | ||
ed851963 | 286 | static void mdp5_plane_cleanup_fb(struct drm_plane *plane, |
1832040d | 287 | struct drm_plane_state *old_state) |
0deed25b | 288 | { |
0deed25b | 289 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
844f9111 ML |
290 | struct drm_framebuffer *fb = old_state->fb; |
291 | ||
292 | if (!fb) | |
293 | return; | |
0deed25b | 294 | |
0002d30f | 295 | DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id); |
ed851963 RC |
296 | msm_framebuffer_cleanup(fb, mdp5_kms->id); |
297 | } | |
0deed25b | 298 | |
3b6acf14 | 299 | #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) |
9142364e AT |
300 | static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state, |
301 | struct drm_plane_state *state) | |
ed851963 | 302 | { |
4a0f012d | 303 | struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state); |
9142364e | 304 | struct drm_plane *plane = state->plane; |
ed851963 | 305 | struct drm_plane_state *old_state = plane->state; |
9708ebbe | 306 | struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg); |
4a0f012d | 307 | bool new_hwpipe = false; |
7a10ee9b | 308 | bool need_right_hwpipe = false; |
9708ebbe | 309 | uint32_t max_width, max_height; |
7a10ee9b | 310 | bool out_of_bounds = false; |
4a0f012d | 311 | uint32_t caps = 0; |
3b6acf14 AT |
312 | struct drm_rect clip; |
313 | int min_scale, max_scale; | |
314 | int ret; | |
ed851963 | 315 | |
0002d30f | 316 | DBG("%s: check (%d -> %d)", plane->name, |
ed851963 RC |
317 | plane_enabled(old_state), plane_enabled(state)); |
318 | ||
9708ebbe RC |
319 | max_width = config->hw->lm.max_width << 16; |
320 | max_height = config->hw->lm.max_height << 16; | |
321 | ||
322 | /* Make sure source dimensions are within bounds. */ | |
7a10ee9b AT |
323 | if (state->src_h > max_height) |
324 | out_of_bounds = true; | |
325 | ||
326 | if (state->src_w > max_width) { | |
327 | /* If source split is supported, we can go up to 2x | |
328 | * the max LM width, but we'd need to stage another | |
329 | * hwpipe to the right LM. So, the drm_plane would | |
330 | * consist of 2 hwpipes. | |
331 | */ | |
332 | if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT && | |
333 | (state->src_w <= 2 * max_width)) | |
334 | need_right_hwpipe = true; | |
335 | else | |
336 | out_of_bounds = true; | |
337 | } | |
338 | ||
339 | if (out_of_bounds) { | |
9708ebbe RC |
340 | struct drm_rect src = drm_plane_state_src(state); |
341 | DBG("Invalid source size "DRM_RECT_FP_FMT, | |
342 | DRM_RECT_FP_ARG(&src)); | |
343 | return -ERANGE; | |
344 | } | |
345 | ||
3b6acf14 AT |
346 | clip.x1 = 0; |
347 | clip.y1 = 0; | |
348 | clip.x2 = crtc_state->adjusted_mode.hdisplay; | |
349 | clip.y2 = crtc_state->adjusted_mode.vdisplay; | |
350 | min_scale = FRAC_16_16(1, 8); | |
351 | max_scale = FRAC_16_16(8, 1); | |
352 | ||
353 | ret = drm_plane_helper_check_state(state, &clip, min_scale, | |
354 | max_scale, true, true); | |
355 | if (ret) | |
356 | return ret; | |
357 | ||
3498409f | 358 | if (plane_enabled(state)) { |
574a37b1 | 359 | unsigned int rotation; |
4a0f012d | 360 | const struct mdp_format *format; |
49ec5b2e RC |
361 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
362 | uint32_t blkcfg = 0; | |
574a37b1 | 363 | |
3498409f | 364 | format = to_mdp_format(msm_framebuffer_format(state->fb)); |
4a0f012d RC |
365 | if (MDP_FORMAT_IS_YUV(format)) |
366 | caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC; | |
3498409f | 367 | |
4a0f012d RC |
368 | if (((state->src_w >> 16) != state->crtc_w) || |
369 | ((state->src_h >> 16) != state->crtc_h)) | |
370 | caps |= MDP_PIPE_CAP_SCALE; | |
8089082f | 371 | |
574a37b1 VS |
372 | rotation = drm_rotation_simplify(state->rotation, |
373 | DRM_ROTATE_0 | | |
374 | DRM_REFLECT_X | | |
375 | DRM_REFLECT_Y); | |
c056b55d | 376 | |
4a0f012d RC |
377 | if (rotation & DRM_REFLECT_X) |
378 | caps |= MDP_PIPE_CAP_HFLIP; | |
379 | ||
380 | if (rotation & DRM_REFLECT_Y) | |
381 | caps |= MDP_PIPE_CAP_VFLIP; | |
382 | ||
5798c8e0 AT |
383 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
384 | caps |= MDP_PIPE_CAP_CURSOR; | |
385 | ||
4a0f012d RC |
386 | /* (re)allocate hw pipe if we don't have one or caps-mismatch: */ |
387 | if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps)) | |
388 | new_hwpipe = true; | |
389 | ||
7a10ee9b AT |
390 | /* |
391 | * (re)allocte hw pipe if we're either requesting for 2 hw pipes | |
392 | * or we're switching from 2 hw pipes to 1 hw pipe because the | |
393 | * new src_w can be supported by 1 hw pipe itself. | |
394 | */ | |
395 | if ((need_right_hwpipe && !mdp5_state->r_hwpipe) || | |
396 | (!need_right_hwpipe && mdp5_state->r_hwpipe)) | |
397 | new_hwpipe = true; | |
398 | ||
49ec5b2e RC |
399 | if (mdp5_kms->smp) { |
400 | const struct mdp_format *format = | |
401 | to_mdp_format(msm_framebuffer_format(state->fb)); | |
402 | ||
403 | blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format, | |
404 | state->src_w >> 16, false); | |
405 | ||
406 | if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg)) | |
407 | new_hwpipe = true; | |
8089082f | 408 | } |
3498409f | 409 | |
4a0f012d RC |
410 | /* (re)assign hwpipe if needed, otherwise keep old one: */ |
411 | if (new_hwpipe) { | |
412 | /* TODO maybe we want to re-assign hwpipe sometimes | |
413 | * in cases when we no-longer need some caps to make | |
414 | * it available for other planes? | |
415 | */ | |
416 | struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe; | |
7a10ee9b AT |
417 | struct mdp5_hw_pipe *old_right_hwpipe = |
418 | mdp5_state->r_hwpipe; | |
419 | ||
49ec5b2e RC |
420 | mdp5_state->hwpipe = mdp5_pipe_assign(state->state, |
421 | plane, caps, blkcfg); | |
4a0f012d RC |
422 | if (IS_ERR(mdp5_state->hwpipe)) { |
423 | DBG("%s: failed to assign hwpipe!", plane->name); | |
424 | return PTR_ERR(mdp5_state->hwpipe); | |
425 | } | |
7a10ee9b AT |
426 | |
427 | if (need_right_hwpipe) { | |
428 | mdp5_state->r_hwpipe = | |
429 | mdp5_pipe_assign(state->state, plane, | |
430 | caps, blkcfg); | |
431 | if (IS_ERR(mdp5_state->r_hwpipe)) { | |
432 | DBG("%s: failed to assign right hwpipe", | |
433 | plane->name); | |
434 | return PTR_ERR(mdp5_state->r_hwpipe); | |
435 | } | |
436 | } else { | |
437 | /* | |
438 | * set it to NULL so that the driver knows we | |
439 | * don't have a right hwpipe when committing a | |
440 | * new state | |
441 | */ | |
442 | mdp5_state->r_hwpipe = NULL; | |
443 | } | |
444 | ||
4a0f012d | 445 | mdp5_pipe_release(state->state, old_hwpipe); |
7a10ee9b | 446 | mdp5_pipe_release(state->state, old_right_hwpipe); |
ed851963 | 447 | } |
adcbae31 RC |
448 | } else { |
449 | mdp5_pipe_release(state->state, mdp5_state->hwpipe); | |
450 | mdp5_pipe_release(state->state, mdp5_state->r_hwpipe); | |
451 | mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL; | |
ed851963 | 452 | } |
06c0dd96 | 453 | |
ed851963 RC |
454 | return 0; |
455 | } | |
456 | ||
9142364e AT |
457 | static int mdp5_plane_atomic_check(struct drm_plane *plane, |
458 | struct drm_plane_state *state) | |
459 | { | |
460 | struct drm_crtc *crtc; | |
461 | struct drm_crtc_state *crtc_state; | |
462 | ||
463 | crtc = state->crtc ? state->crtc : plane->state->crtc; | |
464 | if (!crtc) | |
465 | return 0; | |
466 | ||
467 | crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); | |
468 | if (WARN_ON(!crtc_state)) | |
469 | return -EINVAL; | |
470 | ||
471 | return mdp5_plane_atomic_check_with_state(crtc_state, state); | |
472 | } | |
473 | ||
f1c37e1a TR |
474 | static void mdp5_plane_atomic_update(struct drm_plane *plane, |
475 | struct drm_plane_state *old_state) | |
ed851963 | 476 | { |
ed851963 RC |
477 | struct drm_plane_state *state = plane->state; |
478 | ||
0002d30f | 479 | DBG("%s: update", plane->name); |
0deed25b | 480 | |
f5903bad | 481 | if (plane_enabled(state)) { |
ed851963 | 482 | int ret; |
f5903bad | 483 | |
ed851963 RC |
484 | ret = mdp5_plane_mode_set(plane, |
485 | state->crtc, state->fb, | |
3b6acf14 | 486 | &state->src, &state->dst); |
ed851963 RC |
487 | /* atomic_check should have ensured that this doesn't fail */ |
488 | WARN_ON(ret < 0); | |
ed851963 | 489 | } |
0deed25b SV |
490 | } |
491 | ||
ed851963 RC |
492 | static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = { |
493 | .prepare_fb = mdp5_plane_prepare_fb, | |
494 | .cleanup_fb = mdp5_plane_cleanup_fb, | |
495 | .atomic_check = mdp5_plane_atomic_check, | |
496 | .atomic_update = mdp5_plane_atomic_update, | |
497 | }; | |
498 | ||
821be43f AT |
499 | static void set_scanout_locked(struct mdp5_kms *mdp5_kms, |
500 | enum mdp5_pipe pipe, | |
501 | struct drm_framebuffer *fb) | |
0deed25b | 502 | { |
ed851963 RC |
503 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe), |
504 | MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) | | |
505 | MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1])); | |
0deed25b | 506 | |
ed851963 RC |
507 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe), |
508 | MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) | | |
509 | MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3])); | |
510 | ||
511 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe), | |
512 | msm_framebuffer_iova(fb, mdp5_kms->id, 0)); | |
513 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe), | |
514 | msm_framebuffer_iova(fb, mdp5_kms->id, 1)); | |
515 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe), | |
516 | msm_framebuffer_iova(fb, mdp5_kms->id, 2)); | |
517 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe), | |
755c814a | 518 | msm_framebuffer_iova(fb, mdp5_kms->id, 3)); |
06c0dd96 RC |
519 | } |
520 | ||
f8d9b515 SV |
521 | /* Note: mdp5_plane->pipe_lock must be locked */ |
522 | static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe) | |
523 | { | |
524 | uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) & | |
525 | ~MDP5_PIPE_OP_MODE_CSC_1_EN; | |
526 | ||
527 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value); | |
528 | } | |
529 | ||
530 | /* Note: mdp5_plane->pipe_lock must be locked */ | |
531 | static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, | |
532 | struct csc_cfg *csc) | |
533 | { | |
534 | uint32_t i, mode = 0; /* RGB, no CSC */ | |
535 | uint32_t *matrix; | |
536 | ||
537 | if (unlikely(!csc)) | |
538 | return; | |
539 | ||
540 | if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) | |
541 | mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV); | |
542 | if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) | |
543 | mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV); | |
544 | mode |= MDP5_PIPE_OP_MODE_CSC_1_EN; | |
545 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode); | |
546 | ||
547 | matrix = csc->matrix; | |
548 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe), | |
549 | MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) | | |
550 | MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1])); | |
551 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe), | |
552 | MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) | | |
553 | MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3])); | |
554 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe), | |
555 | MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) | | |
556 | MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5])); | |
557 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe), | |
558 | MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) | | |
559 | MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7])); | |
560 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe), | |
561 | MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8])); | |
562 | ||
563 | for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { | |
564 | uint32_t *pre_clamp = csc->pre_clamp; | |
565 | uint32_t *post_clamp = csc->post_clamp; | |
566 | ||
567 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i), | |
568 | MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) | | |
569 | MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i])); | |
570 | ||
571 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i), | |
572 | MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) | | |
573 | MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i])); | |
574 | ||
575 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i), | |
576 | MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); | |
577 | ||
578 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i), | |
579 | MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); | |
580 | } | |
581 | } | |
582 | ||
583 | #define PHASE_STEP_SHIFT 21 | |
584 | #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */ | |
585 | ||
586 | static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) | |
587 | { | |
588 | uint32_t unit; | |
589 | ||
590 | if (src == 0 || dst == 0) | |
591 | return -EINVAL; | |
592 | ||
593 | /* | |
594 | * PHASE_STEP_X/Y is coded on 26 bits (25:0), | |
595 | * where 2^21 represents the unity "1" in fixed-point hardware design. | |
596 | * This leaves 5 bits for the integer part (downscale case): | |
597 | * -> maximum downscale ratio = 0b1_1111 = 31 | |
598 | */ | |
599 | if (src > (dst * DOWN_SCALE_RATIO_MAX)) | |
600 | return -EOVERFLOW; | |
601 | ||
602 | unit = 1 << PHASE_STEP_SHIFT; | |
603 | *out_phase = mult_frac(unit, src, dst); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
bef799fb SV |
608 | static int calc_scalex_steps(struct drm_plane *plane, |
609 | uint32_t pixel_format, uint32_t src, uint32_t dest, | |
95651cd9 | 610 | uint32_t phasex_steps[COMP_MAX]) |
f8d9b515 | 611 | { |
bef799fb SV |
612 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
613 | struct device *dev = mdp5_kms->dev->dev; | |
f8d9b515 SV |
614 | uint32_t phasex_step; |
615 | unsigned int hsub; | |
616 | int ret; | |
617 | ||
618 | ret = calc_phase_step(src, dest, &phasex_step); | |
bef799fb SV |
619 | if (ret) { |
620 | dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret); | |
f8d9b515 | 621 | return ret; |
bef799fb | 622 | } |
f8d9b515 SV |
623 | |
624 | hsub = drm_format_horz_chroma_subsampling(pixel_format); | |
625 | ||
95651cd9 SV |
626 | phasex_steps[COMP_0] = phasex_step; |
627 | phasex_steps[COMP_3] = phasex_step; | |
628 | phasex_steps[COMP_1_2] = phasex_step / hsub; | |
f8d9b515 SV |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
bef799fb SV |
633 | static int calc_scaley_steps(struct drm_plane *plane, |
634 | uint32_t pixel_format, uint32_t src, uint32_t dest, | |
95651cd9 | 635 | uint32_t phasey_steps[COMP_MAX]) |
f8d9b515 | 636 | { |
bef799fb SV |
637 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
638 | struct device *dev = mdp5_kms->dev->dev; | |
f8d9b515 SV |
639 | uint32_t phasey_step; |
640 | unsigned int vsub; | |
641 | int ret; | |
642 | ||
643 | ret = calc_phase_step(src, dest, &phasey_step); | |
bef799fb SV |
644 | if (ret) { |
645 | dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret); | |
f8d9b515 | 646 | return ret; |
bef799fb | 647 | } |
f8d9b515 SV |
648 | |
649 | vsub = drm_format_vert_chroma_subsampling(pixel_format); | |
650 | ||
95651cd9 SV |
651 | phasey_steps[COMP_0] = phasey_step; |
652 | phasey_steps[COMP_3] = phasey_step; | |
653 | phasey_steps[COMP_1_2] = phasey_step / vsub; | |
f8d9b515 SV |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
8e2930c6 SV |
658 | static uint32_t get_scale_config(const struct mdp_format *format, |
659 | uint32_t src, uint32_t dst, bool horz) | |
f8d9b515 | 660 | { |
8e2930c6 SV |
661 | bool scaling = format->is_yuv ? true : (src != dst); |
662 | uint32_t sub, pix_fmt = format->base.pixel_format; | |
663 | uint32_t ya_filter, uv_filter; | |
664 | bool yuv = format->is_yuv; | |
665 | ||
666 | if (!scaling) | |
667 | return 0; | |
668 | ||
669 | if (yuv) { | |
670 | sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) : | |
671 | drm_format_vert_chroma_subsampling(pix_fmt); | |
672 | uv_filter = ((src / sub) <= dst) ? | |
673 | SCALE_FILTER_BIL : SCALE_FILTER_PCMN; | |
674 | } | |
675 | ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; | |
676 | ||
677 | if (horz) | |
678 | return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | | |
679 | MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | | |
680 | MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | | |
681 | COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); | |
682 | else | |
683 | return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | | |
684 | MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | | |
685 | MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | | |
686 | COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); | |
687 | } | |
688 | ||
689 | static void calc_pixel_ext(const struct mdp_format *format, | |
690 | uint32_t src, uint32_t dst, uint32_t phase_step[2], | |
691 | int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], | |
692 | bool horz) | |
693 | { | |
694 | bool scaling = format->is_yuv ? true : (src != dst); | |
695 | int i; | |
696 | ||
697 | /* | |
698 | * Note: | |
699 | * We assume here that: | |
700 | * 1. PCMN filter is used for downscale | |
701 | * 2. bilinear filter is used for upscale | |
702 | * 3. we are in a single pipe configuration | |
703 | */ | |
704 | ||
705 | for (i = 0; i < COMP_MAX; i++) { | |
706 | pix_ext_edge1[i] = 0; | |
707 | pix_ext_edge2[i] = scaling ? 1 : 0; | |
bef799fb | 708 | } |
8e2930c6 SV |
709 | } |
710 | ||
711 | static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, | |
712 | const struct mdp_format *format, | |
713 | uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], | |
714 | uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) | |
715 | { | |
716 | uint32_t pix_fmt = format->base.pixel_format; | |
717 | uint32_t lr, tb, req; | |
718 | int i; | |
719 | ||
720 | for (i = 0; i < COMP_MAX; i++) { | |
721 | uint32_t roi_w = src_w; | |
722 | uint32_t roi_h = src_h; | |
723 | ||
724 | if (format->is_yuv && i == COMP_1_2) { | |
725 | roi_w /= drm_format_horz_chroma_subsampling(pix_fmt); | |
726 | roi_h /= drm_format_vert_chroma_subsampling(pix_fmt); | |
727 | } | |
f8d9b515 | 728 | |
8e2930c6 SV |
729 | lr = (pe_left[i] >= 0) ? |
730 | MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : | |
731 | MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); | |
732 | ||
733 | lr |= (pe_right[i] >= 0) ? | |
734 | MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : | |
735 | MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); | |
736 | ||
737 | tb = (pe_top[i] >= 0) ? | |
738 | MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : | |
739 | MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); | |
740 | ||
741 | tb |= (pe_bottom[i] >= 0) ? | |
742 | MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : | |
743 | MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); | |
744 | ||
745 | req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + | |
746 | pe_left[i] + pe_right[i]); | |
747 | ||
748 | req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + | |
749 | pe_top[i] + pe_bottom[i]); | |
750 | ||
751 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); | |
752 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); | |
753 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); | |
754 | ||
755 | DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, | |
756 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), | |
757 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), | |
758 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), | |
759 | FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), | |
760 | FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); | |
761 | ||
762 | DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, | |
763 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), | |
764 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), | |
765 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), | |
766 | FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), | |
767 | FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); | |
768 | } | |
f8d9b515 SV |
769 | } |
770 | ||
821be43f AT |
771 | struct pixel_ext { |
772 | int left[COMP_MAX]; | |
773 | int right[COMP_MAX]; | |
774 | int top[COMP_MAX]; | |
775 | int bottom[COMP_MAX]; | |
776 | }; | |
777 | ||
778 | struct phase_step { | |
779 | u32 x[COMP_MAX]; | |
780 | u32 y[COMP_MAX]; | |
781 | }; | |
782 | ||
783 | static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms, | |
784 | struct mdp5_hw_pipe *hwpipe, | |
785 | struct drm_framebuffer *fb, | |
786 | struct phase_step *step, | |
787 | struct pixel_ext *pe, | |
788 | u32 scale_config, u32 hdecm, u32 vdecm, | |
789 | bool hflip, bool vflip, | |
790 | int crtc_x, int crtc_y, | |
791 | unsigned int crtc_w, unsigned int crtc_h, | |
792 | u32 src_img_w, u32 src_img_h, | |
793 | u32 src_x, u32 src_y, | |
794 | u32 src_w, u32 src_h) | |
795 | { | |
796 | enum mdp5_pipe pipe = hwpipe->pipe; | |
797 | bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT; | |
798 | const struct mdp_format *format = | |
799 | to_mdp_format(msm_framebuffer_format(fb)); | |
800 | ||
801 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe), | |
802 | MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) | | |
803 | MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h)); | |
804 | ||
805 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe), | |
806 | MDP5_PIPE_SRC_SIZE_WIDTH(src_w) | | |
807 | MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); | |
808 | ||
809 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe), | |
810 | MDP5_PIPE_SRC_XY_X(src_x) | | |
811 | MDP5_PIPE_SRC_XY_Y(src_y)); | |
812 | ||
813 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe), | |
814 | MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) | | |
815 | MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h)); | |
816 | ||
817 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe), | |
818 | MDP5_PIPE_OUT_XY_X(crtc_x) | | |
819 | MDP5_PIPE_OUT_XY_Y(crtc_y)); | |
820 | ||
821 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe), | |
822 | MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) | | |
823 | MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) | | |
824 | MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) | | |
825 | MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) | | |
826 | COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) | | |
827 | MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) | | |
828 | MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) | | |
829 | COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) | | |
830 | MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) | | |
831 | MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample)); | |
832 | ||
833 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe), | |
834 | MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) | | |
835 | MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) | | |
836 | MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) | | |
837 | MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3])); | |
838 | ||
839 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), | |
840 | (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | | |
841 | (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | | |
842 | COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | | |
843 | MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); | |
844 | ||
845 | /* not using secure mode: */ | |
846 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); | |
847 | ||
848 | if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) | |
849 | mdp5_write_pixel_ext(mdp5_kms, pipe, format, | |
850 | src_w, pe->left, pe->right, | |
851 | src_h, pe->top, pe->bottom); | |
852 | ||
853 | if (hwpipe->caps & MDP_PIPE_CAP_SCALE) { | |
854 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), | |
855 | step->x[COMP_0]); | |
856 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), | |
857 | step->y[COMP_0]); | |
858 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), | |
859 | step->x[COMP_1_2]); | |
860 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), | |
861 | step->y[COMP_1_2]); | |
862 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), | |
863 | MDP5_PIPE_DECIMATION_VERT(vdecm) | | |
864 | MDP5_PIPE_DECIMATION_HORZ(hdecm)); | |
865 | mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), | |
866 | scale_config); | |
867 | } | |
868 | ||
869 | if (hwpipe->caps & MDP_PIPE_CAP_CSC) { | |
870 | if (MDP_FORMAT_IS_YUV(format)) | |
871 | csc_enable(mdp5_kms, pipe, | |
872 | mdp_get_default_csc_cfg(CSC_YUV2RGB)); | |
873 | else | |
874 | csc_disable(mdp5_kms, pipe); | |
875 | } | |
876 | ||
877 | set_scanout_locked(mdp5_kms, pipe, fb); | |
878 | } | |
8e2930c6 | 879 | |
ed851963 | 880 | static int mdp5_plane_mode_set(struct drm_plane *plane, |
06c0dd96 | 881 | struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3b6acf14 | 882 | struct drm_rect *src, struct drm_rect *dest) |
06c0dd96 | 883 | { |
01f8a969 | 884 | struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); |
8089082f | 885 | struct drm_plane_state *pstate = plane->state; |
4a0f012d | 886 | struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe; |
06c0dd96 | 887 | struct mdp5_kms *mdp5_kms = get_kms(plane); |
c056b55d | 888 | enum mdp5_pipe pipe = hwpipe->pipe; |
c26b4f6c | 889 | struct mdp5_hw_pipe *right_hwpipe; |
06c0dd96 RC |
890 | const struct mdp_format *format; |
891 | uint32_t nplanes, config = 0; | |
821be43f AT |
892 | struct phase_step step = { 0 }; |
893 | struct pixel_ext pe = { 0 }; | |
06c0dd96 | 894 | uint32_t hdecm = 0, vdecm = 0; |
f8d9b515 | 895 | uint32_t pix_format; |
574a37b1 | 896 | unsigned int rotation; |
8089082f | 897 | bool vflip, hflip; |
3b6acf14 AT |
898 | int crtc_x, crtc_y; |
899 | unsigned int crtc_w, crtc_h; | |
900 | uint32_t src_x, src_y; | |
901 | uint32_t src_w, src_h; | |
821be43f | 902 | uint32_t src_img_w, src_img_h; |
c26b4f6c AT |
903 | uint32_t src_x_r; |
904 | int crtc_x_r; | |
0deed25b | 905 | unsigned long flags; |
bfcdfb0e | 906 | int ret; |
06c0dd96 | 907 | |
bcb0b461 | 908 | nplanes = fb->format->num_planes; |
06c0dd96 RC |
909 | |
910 | /* bad formats should already be rejected: */ | |
911 | if (WARN_ON(nplanes > pipe2nclients(pipe))) | |
912 | return -EINVAL; | |
913 | ||
f8d9b515 SV |
914 | format = to_mdp_format(msm_framebuffer_format(fb)); |
915 | pix_format = format->base.pixel_format; | |
916 | ||
3b6acf14 AT |
917 | src_x = src->x1; |
918 | src_y = src->y1; | |
919 | src_w = drm_rect_width(src); | |
920 | src_h = drm_rect_height(src); | |
921 | ||
922 | crtc_x = dest->x1; | |
923 | crtc_y = dest->y1; | |
924 | crtc_w = drm_rect_width(dest); | |
925 | crtc_h = drm_rect_height(dest); | |
926 | ||
06c0dd96 RC |
927 | /* src values are in Q16 fixed point, convert to integer: */ |
928 | src_x = src_x >> 16; | |
929 | src_y = src_y >> 16; | |
930 | src_w = src_w >> 16; | |
931 | src_h = src_h >> 16; | |
932 | ||
821be43f AT |
933 | src_img_w = min(fb->width, src_w); |
934 | src_img_h = min(fb->height, src_h); | |
935 | ||
0002d30f | 936 | DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name, |
06c0dd96 RC |
937 | fb->base.id, src_x, src_y, src_w, src_h, |
938 | crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); | |
939 | ||
c26b4f6c AT |
940 | right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe; |
941 | if (right_hwpipe) { | |
942 | /* | |
943 | * if the plane comprises of 2 hw pipes, assume that the width | |
944 | * is split equally across them. The only parameters that varies | |
945 | * between the 2 pipes are src_x and crtc_x | |
946 | */ | |
947 | crtc_w /= 2; | |
948 | src_w /= 2; | |
949 | src_img_w /= 2; | |
950 | ||
951 | crtc_x_r = crtc_x + crtc_w; | |
952 | src_x_r = src_x + src_w; | |
953 | } | |
954 | ||
821be43f | 955 | ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x); |
bef799fb SV |
956 | if (ret) |
957 | return ret; | |
f8d9b515 | 958 | |
821be43f | 959 | ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y); |
bef799fb SV |
960 | if (ret) |
961 | return ret; | |
06c0dd96 | 962 | |
c056b55d | 963 | if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) { |
821be43f AT |
964 | calc_pixel_ext(format, src_w, crtc_w, step.x, |
965 | pe.left, pe.right, true); | |
966 | calc_pixel_ext(format, src_h, crtc_h, step.y, | |
967 | pe.top, pe.bottom, false); | |
8e2930c6 SV |
968 | } |
969 | ||
bef799fb SV |
970 | /* TODO calc hdecm, vdecm */ |
971 | ||
972 | /* SCALE is used to both scale and up-sample chroma components */ | |
8e2930c6 SV |
973 | config |= get_scale_config(format, src_w, crtc_w, true); |
974 | config |= get_scale_config(format, src_h, crtc_h, false); | |
bef799fb | 975 | DBG("scale config = %x", config); |
06c0dd96 | 976 | |
574a37b1 VS |
977 | rotation = drm_rotation_simplify(pstate->rotation, |
978 | DRM_ROTATE_0 | | |
979 | DRM_REFLECT_X | | |
980 | DRM_REFLECT_Y); | |
981 | hflip = !!(rotation & DRM_REFLECT_X); | |
982 | vflip = !!(rotation & DRM_REFLECT_Y); | |
8089082f | 983 | |
01f8a969 | 984 | spin_lock_irqsave(&mdp5_plane->pipe_lock, flags); |
0deed25b | 985 | |
821be43f AT |
986 | mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe, |
987 | config, hdecm, vdecm, hflip, vflip, | |
988 | crtc_x, crtc_y, crtc_w, crtc_h, | |
989 | src_img_w, src_img_h, | |
990 | src_x, src_y, src_w, src_h); | |
c26b4f6c AT |
991 | if (right_hwpipe) |
992 | mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe, | |
993 | config, hdecm, vdecm, hflip, vflip, | |
994 | crtc_x_r, crtc_y, crtc_w, crtc_h, | |
995 | src_img_w, src_img_h, | |
996 | src_x_r, src_y, src_w, src_h); | |
0deed25b | 997 | |
01f8a969 | 998 | spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags); |
0deed25b | 999 | |
821be43f AT |
1000 | plane->fb = fb; |
1001 | ||
0deed25b | 1002 | return ret; |
06c0dd96 RC |
1003 | } |
1004 | ||
10967a06 AT |
1005 | static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane, |
1006 | struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
1007 | int crtc_x, int crtc_y, | |
1008 | unsigned int crtc_w, unsigned int crtc_h, | |
1009 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
1010 | uint32_t src_w, uint32_t src_h, |
1011 | struct drm_modeset_acquire_ctx *ctx) | |
10967a06 AT |
1012 | { |
1013 | struct drm_plane_state *plane_state, *new_plane_state; | |
1014 | struct mdp5_plane_state *mdp5_pstate; | |
1015 | struct drm_crtc_state *crtc_state = crtc->state; | |
1016 | int ret; | |
1017 | ||
1018 | if (!crtc_state->active || drm_atomic_crtc_needs_modeset(crtc_state)) | |
1019 | goto slow; | |
1020 | ||
1021 | plane_state = plane->state; | |
1022 | mdp5_pstate = to_mdp5_plane_state(plane_state); | |
1023 | ||
1024 | /* don't use fast path if we don't have a hwpipe allocated yet */ | |
1025 | if (!mdp5_pstate->hwpipe) | |
1026 | goto slow; | |
1027 | ||
1028 | /* only allow changing of position(crtc x/y or src x/y) in fast path */ | |
1029 | if (plane_state->crtc != crtc || | |
1030 | plane_state->src_w != src_w || | |
1031 | plane_state->src_h != src_h || | |
1032 | plane_state->crtc_w != crtc_w || | |
1033 | plane_state->crtc_h != crtc_h || | |
1034 | !plane_state->fb || | |
1035 | plane_state->fb != fb) | |
1036 | goto slow; | |
1037 | ||
1038 | new_plane_state = mdp5_plane_duplicate_state(plane); | |
1039 | if (!new_plane_state) | |
1040 | return -ENOMEM; | |
1041 | ||
1042 | new_plane_state->src_x = src_x; | |
1043 | new_plane_state->src_y = src_y; | |
1044 | new_plane_state->src_w = src_w; | |
1045 | new_plane_state->src_h = src_h; | |
1046 | new_plane_state->crtc_x = crtc_x; | |
1047 | new_plane_state->crtc_y = crtc_y; | |
1048 | new_plane_state->crtc_w = crtc_w; | |
1049 | new_plane_state->crtc_h = crtc_h; | |
1050 | ||
1051 | ret = mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state); | |
1052 | if (ret) | |
1053 | goto slow_free; | |
1054 | ||
1055 | if (new_plane_state->visible) { | |
1056 | struct mdp5_ctl *ctl; | |
f316b25a | 1057 | struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(crtc); |
10967a06 AT |
1058 | |
1059 | ret = mdp5_plane_mode_set(plane, crtc, fb, | |
1060 | &new_plane_state->src, | |
1061 | &new_plane_state->dst); | |
1062 | WARN_ON(ret < 0); | |
1063 | ||
1064 | ctl = mdp5_crtc_get_ctl(crtc); | |
1065 | ||
f316b25a | 1066 | mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane)); |
10967a06 AT |
1067 | } |
1068 | ||
1069 | *to_mdp5_plane_state(plane_state) = | |
1070 | *to_mdp5_plane_state(new_plane_state); | |
1071 | ||
1072 | mdp5_plane_destroy_state(plane, new_plane_state); | |
1073 | ||
1074 | return 0; | |
1075 | slow_free: | |
1076 | mdp5_plane_destroy_state(plane, new_plane_state); | |
1077 | slow: | |
1078 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
1079 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 1080 | src_x, src_y, src_w, src_h, ctx); |
10967a06 AT |
1081 | } |
1082 | ||
c26b4f6c AT |
1083 | /* |
1084 | * Use this func and the one below only after the atomic state has been | |
1085 | * successfully swapped | |
1086 | */ | |
06c0dd96 RC |
1087 | enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane) |
1088 | { | |
4a0f012d RC |
1089 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); |
1090 | ||
1091 | if (WARN_ON(!pstate->hwpipe)) | |
106f9727 | 1092 | return SSPP_NONE; |
4a0f012d RC |
1093 | |
1094 | return pstate->hwpipe->pipe; | |
06c0dd96 RC |
1095 | } |
1096 | ||
c26b4f6c AT |
1097 | enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane) |
1098 | { | |
1099 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); | |
1100 | ||
1101 | if (!pstate->r_hwpipe) | |
1102 | return SSPP_NONE; | |
1103 | ||
1104 | return pstate->r_hwpipe->pipe; | |
1105 | } | |
1106 | ||
0deed25b SV |
1107 | uint32_t mdp5_plane_get_flush(struct drm_plane *plane) |
1108 | { | |
4a0f012d | 1109 | struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); |
c26b4f6c | 1110 | u32 mask; |
4a0f012d RC |
1111 | |
1112 | if (WARN_ON(!pstate->hwpipe)) | |
1113 | return 0; | |
0deed25b | 1114 | |
c26b4f6c AT |
1115 | mask = pstate->hwpipe->flush_mask; |
1116 | ||
1117 | if (pstate->r_hwpipe) | |
1118 | mask |= pstate->r_hwpipe->flush_mask; | |
1119 | ||
1120 | return mask; | |
0deed25b SV |
1121 | } |
1122 | ||
06c0dd96 | 1123 | /* initialize plane */ |
5798c8e0 AT |
1124 | struct drm_plane *mdp5_plane_init(struct drm_device *dev, |
1125 | enum drm_plane_type type) | |
06c0dd96 RC |
1126 | { |
1127 | struct drm_plane *plane = NULL; | |
1128 | struct mdp5_plane *mdp5_plane; | |
1129 | int ret; | |
1130 | ||
1131 | mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL); | |
1132 | if (!mdp5_plane) { | |
1133 | ret = -ENOMEM; | |
1134 | goto fail; | |
1135 | } | |
1136 | ||
1137 | plane = &mdp5_plane->base; | |
1138 | ||
3498409f | 1139 | mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats, |
4a0f012d | 1140 | ARRAY_SIZE(mdp5_plane->formats), false); |
0deed25b | 1141 | |
01f8a969 AT |
1142 | spin_lock_init(&mdp5_plane->pipe_lock); |
1143 | ||
10967a06 AT |
1144 | if (type == DRM_PLANE_TYPE_CURSOR) |
1145 | ret = drm_universal_plane_init(dev, plane, 0xff, | |
1146 | &mdp5_cursor_plane_funcs, | |
1147 | mdp5_plane->formats, mdp5_plane->nformats, | |
1148 | type, NULL); | |
1149 | else | |
1150 | ret = drm_universal_plane_init(dev, plane, 0xff, | |
1151 | &mdp5_plane_funcs, | |
1152 | mdp5_plane->formats, mdp5_plane->nformats, | |
1153 | type, NULL); | |
ed851963 RC |
1154 | if (ret) |
1155 | goto fail; | |
1156 | ||
1157 | drm_plane_helper_add(plane, &mdp5_plane_helper_funcs); | |
06c0dd96 RC |
1158 | |
1159 | mdp5_plane_install_properties(plane, &plane->base); | |
1160 | ||
1161 | return plane; | |
1162 | ||
1163 | fail: | |
1164 | if (plane) | |
1165 | mdp5_plane_destroy(plane); | |
1166 | ||
1167 | return ERR_PTR(ret); | |
1168 | } |