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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c8afe684 | 2 | /* |
98659487 | 3 | * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. |
c8afe684 RC |
4 | * Copyright (C) 2013 Red Hat |
5 | * Author: Rob Clark <robdclark@gmail.com> | |
c8afe684 RC |
6 | */ |
7 | ||
feea39a8 | 8 | #include <linux/dma-mapping.h> |
25fdd593 | 9 | #include <linux/kthread.h> |
d984457b | 10 | #include <linux/sched/mm.h> |
feea39a8 | 11 | #include <linux/uaccess.h> |
25fdd593 | 12 | #include <uapi/linux/sched/types.h> |
feea39a8 SR |
13 | |
14 | #include <drm/drm_drv.h> | |
15 | #include <drm/drm_file.h> | |
16 | #include <drm/drm_ioctl.h> | |
feea39a8 | 17 | #include <drm/drm_prime.h> |
97ac0e47 | 18 | #include <drm/drm_of.h> |
feea39a8 | 19 | #include <drm/drm_vblank.h> |
97ac0e47 | 20 | |
98659487 | 21 | #include "disp/msm_disp_snapshot.h" |
c8afe684 | 22 | #include "msm_drv.h" |
edcd60ce | 23 | #include "msm_debugfs.h" |
fde5de6c | 24 | #include "msm_fence.h" |
f05c83e7 | 25 | #include "msm_gem.h" |
7198e6b0 | 26 | #include "msm_gpu.h" |
dd2da6e3 | 27 | #include "msm_kms.h" |
c2052a4e | 28 | #include "adreno/adreno_gpu.h" |
c8afe684 | 29 | |
a8d854c1 RC |
30 | /* |
31 | * MSM driver version: | |
32 | * - 1.0.0 - initial interface | |
33 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers | |
7a3bcc0a | 34 | * - 1.2.0 - adds explicit fence support for submit ioctl |
f7de1545 JC |
35 | * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + |
36 | * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for | |
37 | * MSM_GEM_INFO ioctl. | |
1fed8df3 RC |
38 | * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get |
39 | * GEM object's debug name | |
b0fb6604 | 40 | * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl |
ab723b7a | 41 | * - 1.6.0 - Syncobj support |
3ab1c5cc | 42 | * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count |
d12e3390 | 43 | * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) |
a8d854c1 RC |
44 | */ |
45 | #define MSM_VERSION_MAJOR 1 | |
d12e3390 | 46 | #define MSM_VERSION_MINOR 8 |
a8d854c1 RC |
47 | #define MSM_VERSION_PATCHLEVEL 0 |
48 | ||
c8afe684 RC |
49 | static const struct drm_mode_config_funcs mode_config_funcs = { |
50 | .fb_create = msm_framebuffer_create, | |
4ccbc6e5 | 51 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
1f920175 | 52 | .atomic_check = drm_atomic_helper_check, |
d14659f5 SP |
53 | .atomic_commit = drm_atomic_helper_commit, |
54 | }; | |
55 | ||
56 | static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { | |
57 | .atomic_commit_tail = msm_atomic_commit_tail, | |
c8afe684 RC |
58 | }; |
59 | ||
c8afe684 RC |
60 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
61 | static bool reglog = false; | |
62 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
63 | module_param(reglog, bool, 0600); | |
64 | #else | |
65 | #define reglog 0 | |
66 | #endif | |
67 | ||
a9ee34b7 | 68 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
69 | static bool fbdev = true; |
70 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
71 | module_param(fbdev, bool, 0600); | |
72 | #endif | |
73 | ||
3a10ba8c | 74 | static char *vram = "16m"; |
4313c744 | 75 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
871d812a RC |
76 | module_param(vram, charp, 0); |
77 | ||
06d9f56f RC |
78 | bool dumpstate = false; |
79 | MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); | |
80 | module_param(dumpstate, bool, 0600); | |
81 | ||
ba4dd718 RC |
82 | static bool modeset = true; |
83 | MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); | |
84 | module_param(modeset, bool, 0600); | |
85 | ||
060530f1 RC |
86 | /* |
87 | * Util/helpers: | |
88 | */ | |
89 | ||
8e54eea5 JC |
90 | struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, |
91 | const char *name) | |
92 | { | |
93 | int i; | |
94 | char n[32]; | |
95 | ||
96 | snprintf(n, sizeof(n), "%s_clk", name); | |
97 | ||
98 | for (i = 0; bulk && i < count; i++) { | |
99 | if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n)) | |
100 | return bulk[i].clk; | |
101 | } | |
102 | ||
103 | ||
104 | return NULL; | |
105 | } | |
106 | ||
720c3bb8 RC |
107 | struct clk *msm_clk_get(struct platform_device *pdev, const char *name) |
108 | { | |
109 | struct clk *clk; | |
110 | char name2[32]; | |
111 | ||
112 | clk = devm_clk_get(&pdev->dev, name); | |
113 | if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) | |
114 | return clk; | |
115 | ||
116 | snprintf(name2, sizeof(name2), "%s_clk", name); | |
117 | ||
118 | clk = devm_clk_get(&pdev->dev, name2); | |
119 | if (!IS_ERR(clk)) | |
120 | dev_warn(&pdev->dev, "Using legacy clk name binding. Use " | |
121 | "\"%s\" instead of \"%s\"\n", name, name2); | |
122 | ||
123 | return clk; | |
124 | } | |
125 | ||
ea8742c6 | 126 | static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, |
bac2c6a6 | 127 | const char *dbgname, bool quiet, phys_addr_t *psize) |
c8afe684 RC |
128 | { |
129 | struct resource *res; | |
130 | unsigned long size; | |
131 | void __iomem *ptr; | |
132 | ||
133 | if (name) | |
134 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
135 | else | |
136 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
137 | ||
138 | if (!res) { | |
62a35e81 EA |
139 | if (!quiet) |
140 | DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); | |
c8afe684 RC |
141 | return ERR_PTR(-EINVAL); |
142 | } | |
143 | ||
144 | size = resource_size(res); | |
145 | ||
4bdc0d67 | 146 | ptr = devm_ioremap(&pdev->dev, res->start, size); |
c8afe684 | 147 | if (!ptr) { |
62a35e81 EA |
148 | if (!quiet) |
149 | DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); | |
c8afe684 RC |
150 | return ERR_PTR(-ENOMEM); |
151 | } | |
152 | ||
153 | if (reglog) | |
fc99f97a | 154 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 | 155 | |
bac2c6a6 DB |
156 | if (psize) |
157 | *psize = size; | |
158 | ||
c8afe684 RC |
159 | return ptr; |
160 | } | |
161 | ||
62a35e81 EA |
162 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
163 | const char *dbgname) | |
164 | { | |
bac2c6a6 | 165 | return _msm_ioremap(pdev, name, dbgname, false, NULL); |
62a35e81 EA |
166 | } |
167 | ||
168 | void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, | |
169 | const char *dbgname) | |
170 | { | |
bac2c6a6 | 171 | return _msm_ioremap(pdev, name, dbgname, true, NULL); |
62a35e81 EA |
172 | } |
173 | ||
bac2c6a6 DB |
174 | void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, |
175 | const char *dbgname, phys_addr_t *psize) | |
98659487 | 176 | { |
bac2c6a6 | 177 | return _msm_ioremap(pdev, name, dbgname, false, psize); |
98659487 AK |
178 | } |
179 | ||
c8afe684 RC |
180 | void msm_writel(u32 data, void __iomem *addr) |
181 | { | |
182 | if (reglog) | |
fc99f97a | 183 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
184 | writel(data, addr); |
185 | } | |
186 | ||
187 | u32 msm_readl(const void __iomem *addr) | |
188 | { | |
189 | u32 val = readl(addr); | |
190 | if (reglog) | |
8dfe162a | 191 | pr_err("IO:R %p %08x\n", addr, val); |
c8afe684 RC |
192 | return val; |
193 | } | |
194 | ||
40a72b0c SM |
195 | void msm_rmw(void __iomem *addr, u32 mask, u32 or) |
196 | { | |
197 | u32 val = msm_readl(addr); | |
198 | ||
199 | val &= ~mask; | |
200 | msm_writel(val | or, addr); | |
201 | } | |
202 | ||
f026e431 TZ |
203 | static irqreturn_t msm_irq(int irq, void *arg) |
204 | { | |
205 | struct drm_device *dev = arg; | |
206 | struct msm_drm_private *priv = dev->dev_private; | |
207 | struct msm_kms *kms = priv->kms; | |
208 | ||
209 | BUG_ON(!kms); | |
210 | ||
211 | return kms->funcs->irq(kms); | |
212 | } | |
213 | ||
214 | static void msm_irq_preinstall(struct drm_device *dev) | |
215 | { | |
216 | struct msm_drm_private *priv = dev->dev_private; | |
217 | struct msm_kms *kms = priv->kms; | |
218 | ||
219 | BUG_ON(!kms); | |
220 | ||
221 | kms->funcs->irq_preinstall(kms); | |
222 | } | |
223 | ||
224 | static int msm_irq_postinstall(struct drm_device *dev) | |
225 | { | |
226 | struct msm_drm_private *priv = dev->dev_private; | |
227 | struct msm_kms *kms = priv->kms; | |
228 | ||
229 | BUG_ON(!kms); | |
230 | ||
231 | if (kms->funcs->irq_postinstall) | |
232 | return kms->funcs->irq_postinstall(kms); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static int msm_irq_install(struct drm_device *dev, unsigned int irq) | |
238 | { | |
239 | int ret; | |
240 | ||
241 | if (irq == IRQ_NOTCONNECTED) | |
242 | return -ENOTCONN; | |
243 | ||
244 | msm_irq_preinstall(dev); | |
245 | ||
246 | ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev); | |
247 | if (ret) | |
248 | return ret; | |
249 | ||
250 | ret = msm_irq_postinstall(dev); | |
251 | if (ret) { | |
252 | free_irq(irq, dev); | |
253 | return ret; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
259 | static void msm_irq_uninstall(struct drm_device *dev) | |
260 | { | |
261 | struct msm_drm_private *priv = dev->dev_private; | |
262 | struct msm_kms *kms = priv->kms; | |
263 | ||
264 | kms->funcs->irq_uninstall(kms); | |
265 | free_irq(kms->irq, dev); | |
266 | } | |
267 | ||
48d1d28e JS |
268 | struct msm_vblank_work { |
269 | struct work_struct work; | |
78b1d470 HL |
270 | int crtc_id; |
271 | bool enable; | |
48d1d28e | 272 | struct msm_drm_private *priv; |
78b1d470 HL |
273 | }; |
274 | ||
5aeb6656 | 275 | static void vblank_ctrl_worker(struct work_struct *work) |
78b1d470 | 276 | { |
48d1d28e JS |
277 | struct msm_vblank_work *vbl_work = container_of(work, |
278 | struct msm_vblank_work, work); | |
279 | struct msm_drm_private *priv = vbl_work->priv; | |
78b1d470 | 280 | struct msm_kms *kms = priv->kms; |
78b1d470 | 281 | |
48d1d28e JS |
282 | if (vbl_work->enable) |
283 | kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); | |
284 | else | |
285 | kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); | |
78b1d470 | 286 | |
48d1d28e | 287 | kfree(vbl_work); |
78b1d470 HL |
288 | } |
289 | ||
290 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
291 | int crtc_id, bool enable) | |
292 | { | |
48d1d28e | 293 | struct msm_vblank_work *vbl_work; |
78b1d470 | 294 | |
48d1d28e JS |
295 | vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); |
296 | if (!vbl_work) | |
78b1d470 HL |
297 | return -ENOMEM; |
298 | ||
48d1d28e | 299 | INIT_WORK(&vbl_work->work, vblank_ctrl_worker); |
78b1d470 | 300 | |
48d1d28e JS |
301 | vbl_work->crtc_id = crtc_id; |
302 | vbl_work->enable = enable; | |
303 | vbl_work->priv = priv; | |
78b1d470 | 304 | |
48d1d28e | 305 | queue_work(priv->wq, &vbl_work->work); |
78b1d470 HL |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
2b669875 | 310 | static int msm_drm_uninit(struct device *dev) |
c8afe684 | 311 | { |
2b669875 AT |
312 | struct platform_device *pdev = to_platform_device(dev); |
313 | struct drm_device *ddev = platform_get_drvdata(pdev); | |
314 | struct msm_drm_private *priv = ddev->dev_private; | |
c8afe684 | 315 | struct msm_kms *kms = priv->kms; |
bc3220be | 316 | struct msm_mdss *mdss = priv->mdss; |
25fdd593 | 317 | int i; |
78b1d470 | 318 | |
2aa31767 SP |
319 | /* |
320 | * Shutdown the hw if we're far enough along where things might be on. | |
321 | * If we run this too early, we'll end up panicking in any variety of | |
322 | * places. Since we don't register the drm device until late in | |
323 | * msm_drm_init, drm_dev->registered is used as an indicator that the | |
324 | * shutdown will be successful. | |
325 | */ | |
326 | if (ddev->registered) { | |
327 | drm_dev_unregister(ddev); | |
328 | drm_atomic_helper_shutdown(ddev); | |
329 | } | |
330 | ||
78b1d470 | 331 | /* We must cancel and cleanup any pending vblank enable/disable |
f026e431 | 332 | * work before msm_irq_uninstall() to avoid work re-enabling an |
78b1d470 HL |
333 | * irq after uninstall has disabled it. |
334 | */ | |
c8afe684 | 335 | |
48d1d28e | 336 | flush_workqueue(priv->wq); |
25fdd593 | 337 | |
d9db30ce | 338 | /* clean up event worker threads */ |
25fdd593 | 339 | for (i = 0; i < priv->num_crtcs; i++) { |
1041dee2 B |
340 | if (priv->event_thread[i].worker) |
341 | kthread_destroy_worker(priv->event_thread[i].worker); | |
25fdd593 JS |
342 | } |
343 | ||
68209390 RC |
344 | msm_gem_shrinker_cleanup(ddev); |
345 | ||
2b669875 AT |
346 | drm_kms_helper_poll_fini(ddev); |
347 | ||
85eac470 NT |
348 | msm_perf_debugfs_cleanup(priv); |
349 | msm_rd_debugfs_cleanup(priv); | |
350 | ||
1aaa57f5 AT |
351 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
352 | if (fbdev && priv->fbdev) | |
2b669875 | 353 | msm_fbdev_free(ddev); |
1aaa57f5 | 354 | #endif |
2aa31767 | 355 | |
98659487 AK |
356 | msm_disp_snapshot_destroy(ddev); |
357 | ||
2b669875 | 358 | drm_mode_config_cleanup(ddev); |
c8afe684 | 359 | |
2b669875 | 360 | pm_runtime_get_sync(dev); |
f026e431 | 361 | msm_irq_uninstall(ddev); |
2b669875 | 362 | pm_runtime_put_sync(dev); |
c8afe684 | 363 | |
16976085 | 364 | if (kms && kms->funcs) |
c8afe684 | 365 | kms->funcs->destroy(kms); |
c8afe684 | 366 | |
871d812a | 367 | if (priv->vram.paddr) { |
00085f1e | 368 | unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
871d812a | 369 | drm_mm_takedown(&priv->vram.mm); |
2b669875 | 370 | dma_free_attrs(dev, priv->vram.size, NULL, |
00085f1e | 371 | priv->vram.paddr, attrs); |
871d812a RC |
372 | } |
373 | ||
2b669875 | 374 | component_unbind_all(dev, ddev); |
060530f1 | 375 | |
bc3220be RY |
376 | if (mdss && mdss->funcs) |
377 | mdss->funcs->destroy(ddev); | |
0a6030d2 | 378 | |
2b669875 | 379 | ddev->dev_private = NULL; |
4d8dc2df | 380 | drm_dev_put(ddev); |
c8afe684 | 381 | |
2aa31767 | 382 | destroy_workqueue(priv->wq); |
c8afe684 RC |
383 | kfree(priv); |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
aaded2e3 JS |
388 | #define KMS_MDP4 4 |
389 | #define KMS_MDP5 5 | |
25fdd593 | 390 | #define KMS_DPU 3 |
aaded2e3 | 391 | |
06c0dd96 RC |
392 | static int get_mdp_ver(struct platform_device *pdev) |
393 | { | |
06c0dd96 | 394 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
395 | |
396 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
397 | } |
398 | ||
072f1f91 RC |
399 | #include <linux/of_address.h> |
400 | ||
c2052a4e JM |
401 | bool msm_use_mmu(struct drm_device *dev) |
402 | { | |
403 | struct msm_drm_private *priv = dev->dev_private; | |
404 | ||
405 | /* a2xx comes with its own MMU */ | |
406 | return priv->is_a2xx || iommu_present(&platform_bus_type); | |
407 | } | |
408 | ||
5bf9c0b6 | 409 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 410 | { |
5bf9c0b6 | 411 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 412 | struct device_node *node; |
072f1f91 RC |
413 | unsigned long size = 0; |
414 | int ret = 0; | |
415 | ||
072f1f91 RC |
416 | /* In the device-tree world, we could have a 'memory-region' |
417 | * phandle, which gives us a link to our "vram". Allocating | |
418 | * is all nicely abstracted behind the dma api, but we need | |
419 | * to know the entire size to allocate it all in one go. There | |
420 | * are two cases: | |
421 | * 1) device with no IOMMU, in which case we need exclusive | |
422 | * access to a VRAM carveout big enough for all gpu | |
423 | * buffers | |
424 | * 2) device with IOMMU, but where the bootloader puts up | |
425 | * a splash screen. In this case, the VRAM carveout | |
426 | * need only be large enough for fbdev fb. But we need | |
427 | * exclusive access to the buffer to avoid the kernel | |
428 | * using those pages for other purposes (which appears | |
429 | * as corruption on screen before we have a chance to | |
430 | * load and do initial modeset) | |
431 | */ | |
072f1f91 RC |
432 | |
433 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
434 | if (node) { | |
435 | struct resource r; | |
436 | ret = of_address_to_resource(node, 0, &r); | |
2ca41c17 | 437 | of_node_put(node); |
072f1f91 RC |
438 | if (ret) |
439 | return ret; | |
440 | size = r.end - r.start; | |
fc99f97a | 441 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 442 | |
e9fbdaf2 AT |
443 | /* if we have no IOMMU, then we need to use carveout allocator. |
444 | * Grab the entire CMA chunk carved out in early startup in | |
445 | * mach-msm: | |
446 | */ | |
c2052a4e | 447 | } else if (!msm_use_mmu(dev)) { |
072f1f91 RC |
448 | DRM_INFO("using %s VRAM carveout\n", vram); |
449 | size = memparse(vram, NULL); | |
450 | } | |
451 | ||
452 | if (size) { | |
00085f1e | 453 | unsigned long attrs = 0; |
871d812a RC |
454 | void *p; |
455 | ||
871d812a RC |
456 | priv->vram.size = size; |
457 | ||
458 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
0e08270a | 459 | spin_lock_init(&priv->vram.lock); |
871d812a | 460 | |
00085f1e KK |
461 | attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
462 | attrs |= DMA_ATTR_WRITE_COMBINE; | |
871d812a RC |
463 | |
464 | /* note that for no-kernel-mapping, the vaddr returned | |
465 | * is bogus, but non-null if allocation succeeded: | |
466 | */ | |
467 | p = dma_alloc_attrs(dev->dev, size, | |
00085f1e | 468 | &priv->vram.paddr, GFP_KERNEL, attrs); |
871d812a | 469 | if (!p) { |
6a41da17 | 470 | DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); |
871d812a | 471 | priv->vram.paddr = 0; |
5bf9c0b6 | 472 | return -ENOMEM; |
871d812a RC |
473 | } |
474 | ||
6a41da17 | 475 | DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", |
871d812a RC |
476 | (uint32_t)priv->vram.paddr, |
477 | (uint32_t)(priv->vram.paddr + size)); | |
478 | } | |
479 | ||
072f1f91 | 480 | return ret; |
5bf9c0b6 RC |
481 | } |
482 | ||
70a59dd8 | 483 | static int msm_drm_init(struct device *dev, const struct drm_driver *drv) |
5bf9c0b6 | 484 | { |
2b669875 AT |
485 | struct platform_device *pdev = to_platform_device(dev); |
486 | struct drm_device *ddev; | |
5bf9c0b6 RC |
487 | struct msm_drm_private *priv; |
488 | struct msm_kms *kms; | |
bc3220be | 489 | struct msm_mdss *mdss; |
25fdd593 | 490 | int ret, i; |
5bf9c0b6 | 491 | |
2b669875 | 492 | ddev = drm_dev_alloc(drv, dev); |
0f288605 | 493 | if (IS_ERR(ddev)) { |
6a41da17 | 494 | DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); |
0f288605 | 495 | return PTR_ERR(ddev); |
2b669875 AT |
496 | } |
497 | ||
498 | platform_set_drvdata(pdev, ddev); | |
2b669875 | 499 | |
5bf9c0b6 RC |
500 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
501 | if (!priv) { | |
77050c3f | 502 | ret = -ENOMEM; |
4d8dc2df | 503 | goto err_put_drm_dev; |
5bf9c0b6 RC |
504 | } |
505 | ||
2b669875 | 506 | ddev->dev_private = priv; |
68209390 | 507 | priv->dev = ddev; |
5bf9c0b6 | 508 | |
25fdd593 JS |
509 | switch (get_mdp_ver(pdev)) { |
510 | case KMS_MDP5: | |
511 | ret = mdp5_mdss_init(ddev); | |
512 | break; | |
513 | case KMS_DPU: | |
514 | ret = dpu_mdss_init(ddev); | |
515 | break; | |
516 | default: | |
517 | ret = 0; | |
518 | break; | |
519 | } | |
77050c3f JS |
520 | if (ret) |
521 | goto err_free_priv; | |
0a6030d2 | 522 | |
bc3220be RY |
523 | mdss = priv->mdss; |
524 | ||
5bf9c0b6 | 525 | priv->wq = alloc_ordered_workqueue("msm", 0); |
1d2fa58e | 526 | priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; |
5bf9c0b6 | 527 | |
6ed0897c RC |
528 | INIT_LIST_HEAD(&priv->objects); |
529 | mutex_init(&priv->obj_lock); | |
530 | ||
3edfa30f RC |
531 | INIT_LIST_HEAD(&priv->inactive_willneed); |
532 | INIT_LIST_HEAD(&priv->inactive_dontneed); | |
64fcbde7 | 533 | INIT_LIST_HEAD(&priv->inactive_unpinned); |
d984457b | 534 | mutex_init(&priv->mm_lock); |
48e7f183 | 535 | |
d984457b RC |
536 | /* Teach lockdep about lock ordering wrt. shrinker: */ |
537 | fs_reclaim_acquire(GFP_KERNEL); | |
538 | might_lock(&priv->mm_lock); | |
539 | fs_reclaim_release(GFP_KERNEL); | |
5bf9c0b6 | 540 | |
2b669875 | 541 | drm_mode_config_init(ddev); |
060530f1 | 542 | |
d863f0c7 | 543 | ret = msm_init_vram(ddev); |
77050c3f JS |
544 | if (ret) |
545 | goto err_destroy_mdss; | |
060530f1 | 546 | |
d863f0c7 CT |
547 | /* Bind all our sub-components: */ |
548 | ret = component_bind_all(dev, ddev); | |
13f15565 | 549 | if (ret) |
d863f0c7 | 550 | goto err_destroy_mdss; |
13f15565 | 551 | |
d5653a99 | 552 | dma_set_max_seg_size(dev, UINT_MAX); |
db735fc4 | 553 | |
68209390 RC |
554 | msm_gem_shrinker_init(ddev); |
555 | ||
06c0dd96 | 556 | switch (get_mdp_ver(pdev)) { |
aaded2e3 | 557 | case KMS_MDP4: |
2b669875 | 558 | kms = mdp4_kms_init(ddev); |
0a6030d2 | 559 | priv->kms = kms; |
06c0dd96 | 560 | break; |
aaded2e3 | 561 | case KMS_MDP5: |
392ae6e0 | 562 | kms = mdp5_kms_init(ddev); |
06c0dd96 | 563 | break; |
25fdd593 JS |
564 | case KMS_DPU: |
565 | kms = dpu_kms_init(ddev); | |
566 | priv->kms = kms; | |
567 | break; | |
06c0dd96 | 568 | default: |
e6f6d63e JM |
569 | /* valid only for the dummy headless case, where of_node=NULL */ |
570 | WARN_ON(dev->of_node); | |
571 | kms = NULL; | |
06c0dd96 RC |
572 | break; |
573 | } | |
574 | ||
c8afe684 | 575 | if (IS_ERR(kms)) { |
6a41da17 | 576 | DRM_DEV_ERROR(dev, "failed to load kms\n"); |
e4826a94 | 577 | ret = PTR_ERR(kms); |
b2ccfdf1 | 578 | priv->kms = NULL; |
77050c3f | 579 | goto err_msm_uninit; |
c8afe684 RC |
580 | } |
581 | ||
bb676df1 JS |
582 | /* Enable normalization of plane zpos */ |
583 | ddev->mode_config.normalize_zpos = true; | |
584 | ||
c8afe684 | 585 | if (kms) { |
2d99ced7 | 586 | kms->dev = ddev; |
c8afe684 RC |
587 | ret = kms->funcs->hw_init(kms); |
588 | if (ret) { | |
6a41da17 | 589 | DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); |
77050c3f | 590 | goto err_msm_uninit; |
c8afe684 RC |
591 | } |
592 | } | |
593 | ||
2b669875 | 594 | ddev->mode_config.funcs = &mode_config_funcs; |
d14659f5 | 595 | ddev->mode_config.helper_private = &mode_config_helper_funcs; |
c8afe684 | 596 | |
25fdd593 | 597 | for (i = 0; i < priv->num_crtcs; i++) { |
25fdd593 JS |
598 | /* initialize event thread */ |
599 | priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; | |
25fdd593 | 600 | priv->event_thread[i].dev = ddev; |
1041dee2 B |
601 | priv->event_thread[i].worker = kthread_create_worker(0, |
602 | "crtc_event:%d", priv->event_thread[i].crtc_id); | |
603 | if (IS_ERR(priv->event_thread[i].worker)) { | |
a1c9b1e3 | 604 | ret = PTR_ERR(priv->event_thread[i].worker); |
4971f090 | 605 | DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); |
bfddcfe1 | 606 | ret = PTR_ERR(priv->event_thread[i].worker); |
7f9743ab JS |
607 | goto err_msm_uninit; |
608 | } | |
609 | ||
6d2b84a4 | 610 | sched_set_fifo(priv->event_thread[i].worker->task); |
25fdd593 JS |
611 | } |
612 | ||
2b669875 | 613 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
c8afe684 | 614 | if (ret < 0) { |
6a41da17 | 615 | DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); |
77050c3f | 616 | goto err_msm_uninit; |
c8afe684 RC |
617 | } |
618 | ||
a2b3a557 AT |
619 | if (kms) { |
620 | pm_runtime_get_sync(dev); | |
f026e431 | 621 | ret = msm_irq_install(ddev, kms->irq); |
a2b3a557 AT |
622 | pm_runtime_put_sync(dev); |
623 | if (ret < 0) { | |
6a41da17 | 624 | DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); |
77050c3f | 625 | goto err_msm_uninit; |
a2b3a557 | 626 | } |
c8afe684 RC |
627 | } |
628 | ||
2b669875 AT |
629 | ret = drm_dev_register(ddev, 0); |
630 | if (ret) | |
77050c3f | 631 | goto err_msm_uninit; |
2b669875 | 632 | |
6a7e0b0e FE |
633 | if (kms) { |
634 | ret = msm_disp_snapshot_init(ddev); | |
635 | if (ret) | |
636 | DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); | |
637 | } | |
2b669875 | 638 | drm_mode_config_reset(ddev); |
cf3a7e4c | 639 | |
a9ee34b7 | 640 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e6f6d63e | 641 | if (kms && fbdev) |
2b669875 | 642 | priv->fbdev = msm_fbdev_init(ddev); |
c8afe684 RC |
643 | #endif |
644 | ||
2b669875 | 645 | ret = msm_debugfs_late_init(ddev); |
a7d3c950 | 646 | if (ret) |
77050c3f | 647 | goto err_msm_uninit; |
a7d3c950 | 648 | |
2b669875 | 649 | drm_kms_helper_poll_init(ddev); |
c8afe684 RC |
650 | |
651 | return 0; | |
652 | ||
77050c3f | 653 | err_msm_uninit: |
2b669875 | 654 | msm_drm_uninit(dev); |
c8afe684 | 655 | return ret; |
77050c3f JS |
656 | err_destroy_mdss: |
657 | if (mdss && mdss->funcs) | |
658 | mdss->funcs->destroy(ddev); | |
659 | err_free_priv: | |
660 | kfree(priv); | |
4d8dc2df TZ |
661 | err_put_drm_dev: |
662 | drm_dev_put(ddev); | |
5620b135 | 663 | platform_set_drvdata(pdev, NULL); |
77050c3f | 664 | return ret; |
c8afe684 RC |
665 | } |
666 | ||
2b669875 AT |
667 | /* |
668 | * DRM operations: | |
669 | */ | |
670 | ||
7198e6b0 RC |
671 | static void load_gpu(struct drm_device *dev) |
672 | { | |
a1ad3523 | 673 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 674 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 675 | |
a1ad3523 RC |
676 | mutex_lock(&init_lock); |
677 | ||
e2550b7a RC |
678 | if (!priv->gpu) |
679 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 680 | |
a1ad3523 | 681 | mutex_unlock(&init_lock); |
7198e6b0 RC |
682 | } |
683 | ||
f97decac | 684 | static int context_init(struct drm_device *dev, struct drm_file *file) |
7198e6b0 | 685 | { |
14eb0cb4 | 686 | static atomic_t ident = ATOMIC_INIT(0); |
295b22ae | 687 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 RC |
688 | struct msm_file_private *ctx; |
689 | ||
7198e6b0 RC |
690 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
691 | if (!ctx) | |
692 | return -ENOMEM; | |
693 | ||
654e9c18 RC |
694 | INIT_LIST_HEAD(&ctx->submitqueues); |
695 | rwlock_init(&ctx->queuelock); | |
696 | ||
cf655d61 | 697 | kref_init(&ctx->ref); |
f97decac | 698 | msm_submitqueue_init(dev, ctx); |
f7de1545 | 699 | |
25faf2f2 | 700 | ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); |
7198e6b0 RC |
701 | file->driver_priv = ctx; |
702 | ||
14eb0cb4 RC |
703 | ctx->seqno = atomic_inc_return(&ident); |
704 | ||
7198e6b0 RC |
705 | return 0; |
706 | } | |
707 | ||
f7de1545 JC |
708 | static int msm_open(struct drm_device *dev, struct drm_file *file) |
709 | { | |
710 | /* For now, load gpu on open.. to avoid the requirement of having | |
711 | * firmware in the initrd. | |
712 | */ | |
713 | load_gpu(dev); | |
714 | ||
f97decac | 715 | return context_init(dev, file); |
f7de1545 JC |
716 | } |
717 | ||
718 | static void context_close(struct msm_file_private *ctx) | |
719 | { | |
720 | msm_submitqueue_close(ctx); | |
cf655d61 | 721 | msm_file_private_put(ctx); |
f7de1545 JC |
722 | } |
723 | ||
94df145c | 724 | static void msm_postclose(struct drm_device *dev, struct drm_file *file) |
c8afe684 RC |
725 | { |
726 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 727 | struct msm_file_private *ctx = file->driver_priv; |
7198e6b0 | 728 | |
7198e6b0 RC |
729 | mutex_lock(&dev->struct_mutex); |
730 | if (ctx == priv->lastctx) | |
731 | priv->lastctx = NULL; | |
732 | mutex_unlock(&dev->struct_mutex); | |
733 | ||
f7de1545 | 734 | context_close(ctx); |
c8afe684 RC |
735 | } |
736 | ||
76e8cfd8 | 737 | int msm_crtc_enable_vblank(struct drm_crtc *crtc) |
c8afe684 | 738 | { |
76e8cfd8 TZ |
739 | struct drm_device *dev = crtc->dev; |
740 | unsigned int pipe = crtc->index; | |
c8afe684 RC |
741 | struct msm_drm_private *priv = dev->dev_private; |
742 | struct msm_kms *kms = priv->kms; | |
743 | if (!kms) | |
744 | return -ENXIO; | |
721c6e0c | 745 | drm_dbg_vbl(dev, "crtc=%u", pipe); |
88e72717 | 746 | return vblank_ctrl_queue_work(priv, pipe, true); |
c8afe684 RC |
747 | } |
748 | ||
76e8cfd8 | 749 | void msm_crtc_disable_vblank(struct drm_crtc *crtc) |
c8afe684 | 750 | { |
76e8cfd8 TZ |
751 | struct drm_device *dev = crtc->dev; |
752 | unsigned int pipe = crtc->index; | |
c8afe684 RC |
753 | struct msm_drm_private *priv = dev->dev_private; |
754 | struct msm_kms *kms = priv->kms; | |
755 | if (!kms) | |
756 | return; | |
721c6e0c | 757 | drm_dbg_vbl(dev, "crtc=%u", pipe); |
88e72717 | 758 | vblank_ctrl_queue_work(priv, pipe, false); |
c8afe684 RC |
759 | } |
760 | ||
7198e6b0 RC |
761 | /* |
762 | * DRM ioctls: | |
763 | */ | |
764 | ||
765 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
766 | struct drm_file *file) | |
767 | { | |
768 | struct msm_drm_private *priv = dev->dev_private; | |
769 | struct drm_msm_param *args = data; | |
770 | struct msm_gpu *gpu; | |
771 | ||
772 | /* for now, we just have 3d pipe.. eventually this would need to | |
773 | * be more clever to dispatch to appropriate gpu module: | |
774 | */ | |
775 | if (args->pipe != MSM_PIPE_3D0) | |
776 | return -EINVAL; | |
777 | ||
778 | gpu = priv->gpu; | |
779 | ||
780 | if (!gpu) | |
781 | return -ENXIO; | |
782 | ||
783 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
784 | } | |
785 | ||
786 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
787 | struct drm_file *file) | |
788 | { | |
789 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
790 | |
791 | if (args->flags & ~MSM_BO_FLAGS) { | |
792 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
793 | return -EINVAL; | |
794 | } | |
795 | ||
7198e6b0 | 796 | return msm_gem_new_handle(dev, file, args->size, |
0815d774 | 797 | args->flags, &args->handle, NULL); |
7198e6b0 RC |
798 | } |
799 | ||
56c2da83 RC |
800 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
801 | { | |
802 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
803 | } | |
7198e6b0 RC |
804 | |
805 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
806 | struct drm_file *file) | |
807 | { | |
808 | struct drm_msm_gem_cpu_prep *args = data; | |
809 | struct drm_gem_object *obj; | |
56c2da83 | 810 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
811 | int ret; |
812 | ||
93ddb0d3 RC |
813 | if (args->op & ~MSM_PREP_FLAGS) { |
814 | DRM_ERROR("invalid op: %08x\n", args->op); | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
a8ad0bd8 | 818 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
819 | if (!obj) |
820 | return -ENOENT; | |
821 | ||
56c2da83 | 822 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 | 823 | |
f7d33950 | 824 | drm_gem_object_put(obj); |
7198e6b0 RC |
825 | |
826 | return ret; | |
827 | } | |
828 | ||
829 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
830 | struct drm_file *file) | |
831 | { | |
832 | struct drm_msm_gem_cpu_fini *args = data; | |
833 | struct drm_gem_object *obj; | |
834 | int ret; | |
835 | ||
a8ad0bd8 | 836 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
837 | if (!obj) |
838 | return -ENOENT; | |
839 | ||
840 | ret = msm_gem_cpu_fini(obj); | |
841 | ||
f7d33950 | 842 | drm_gem_object_put(obj); |
7198e6b0 RC |
843 | |
844 | return ret; | |
845 | } | |
846 | ||
49fd08ba | 847 | static int msm_ioctl_gem_info_iova(struct drm_device *dev, |
933415e2 JC |
848 | struct drm_file *file, struct drm_gem_object *obj, |
849 | uint64_t *iova) | |
49fd08ba | 850 | { |
6cefa31e | 851 | struct msm_drm_private *priv = dev->dev_private; |
933415e2 | 852 | struct msm_file_private *ctx = file->driver_priv; |
49fd08ba | 853 | |
6cefa31e | 854 | if (!priv->gpu) |
49fd08ba JC |
855 | return -EINVAL; |
856 | ||
9fe041f6 JC |
857 | /* |
858 | * Don't pin the memory here - just get an address so that userspace can | |
859 | * be productive | |
860 | */ | |
933415e2 | 861 | return msm_gem_get_iova(obj, ctx->aspace, iova); |
49fd08ba JC |
862 | } |
863 | ||
7198e6b0 RC |
864 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, |
865 | struct drm_file *file) | |
866 | { | |
867 | struct drm_msm_gem_info *args = data; | |
868 | struct drm_gem_object *obj; | |
f05c83e7 RC |
869 | struct msm_gem_object *msm_obj; |
870 | int i, ret = 0; | |
7198e6b0 | 871 | |
789d2e5a | 872 | if (args->pad) |
7198e6b0 RC |
873 | return -EINVAL; |
874 | ||
789d2e5a RC |
875 | switch (args->info) { |
876 | case MSM_INFO_GET_OFFSET: | |
877 | case MSM_INFO_GET_IOVA: | |
878 | /* value returned as immediate, not pointer, so len==0: */ | |
879 | if (args->len) | |
880 | return -EINVAL; | |
881 | break; | |
f05c83e7 RC |
882 | case MSM_INFO_SET_NAME: |
883 | case MSM_INFO_GET_NAME: | |
884 | break; | |
789d2e5a | 885 | default: |
7198e6b0 | 886 | return -EINVAL; |
789d2e5a | 887 | } |
7198e6b0 | 888 | |
a8ad0bd8 | 889 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
890 | if (!obj) |
891 | return -ENOENT; | |
892 | ||
f05c83e7 | 893 | msm_obj = to_msm_bo(obj); |
49fd08ba | 894 | |
789d2e5a RC |
895 | switch (args->info) { |
896 | case MSM_INFO_GET_OFFSET: | |
897 | args->value = msm_gem_mmap_offset(obj); | |
898 | break; | |
899 | case MSM_INFO_GET_IOVA: | |
933415e2 | 900 | ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); |
789d2e5a | 901 | break; |
f05c83e7 RC |
902 | case MSM_INFO_SET_NAME: |
903 | /* length check should leave room for terminating null: */ | |
904 | if (args->len >= sizeof(msm_obj->name)) { | |
905 | ret = -EINVAL; | |
906 | break; | |
907 | } | |
7cce8e4e | 908 | if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), |
860433ed JC |
909 | args->len)) { |
910 | msm_obj->name[0] = '\0'; | |
7cce8e4e | 911 | ret = -EFAULT; |
860433ed JC |
912 | break; |
913 | } | |
f05c83e7 RC |
914 | msm_obj->name[args->len] = '\0'; |
915 | for (i = 0; i < args->len; i++) { | |
916 | if (!isprint(msm_obj->name[i])) { | |
917 | msm_obj->name[i] = '\0'; | |
918 | break; | |
919 | } | |
920 | } | |
921 | break; | |
922 | case MSM_INFO_GET_NAME: | |
923 | if (args->value && (args->len < strlen(msm_obj->name))) { | |
924 | ret = -EINVAL; | |
925 | break; | |
926 | } | |
927 | args->len = strlen(msm_obj->name); | |
928 | if (args->value) { | |
7cce8e4e DC |
929 | if (copy_to_user(u64_to_user_ptr(args->value), |
930 | msm_obj->name, args->len)) | |
931 | ret = -EFAULT; | |
f05c83e7 RC |
932 | } |
933 | break; | |
49fd08ba | 934 | } |
7198e6b0 | 935 | |
f7d33950 | 936 | drm_gem_object_put(obj); |
7198e6b0 RC |
937 | |
938 | return ret; | |
939 | } | |
940 | ||
824d4f9d RC |
941 | static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, |
942 | ktime_t timeout) | |
7198e6b0 | 943 | { |
a61acbbe | 944 | struct dma_fence *fence; |
f97decac | 945 | int ret; |
93ddb0d3 | 946 | |
a61acbbe RC |
947 | /* |
948 | * Map submitqueue scoped "seqno" (which is actually an idr key) | |
949 | * back to underlying dma-fence | |
950 | * | |
951 | * The fence is removed from the fence_idr when the submit is | |
952 | * retired, so if the fence is not found it means there is nothing | |
953 | * to wait for | |
954 | */ | |
955 | ret = mutex_lock_interruptible(&queue->lock); | |
956 | if (ret) | |
957 | return ret; | |
824d4f9d | 958 | fence = idr_find(&queue->fence_idr, fence_id); |
a61acbbe RC |
959 | if (fence) |
960 | fence = dma_fence_get_rcu(fence); | |
961 | mutex_unlock(&queue->lock); | |
962 | ||
963 | if (!fence) | |
964 | return 0; | |
f97decac | 965 | |
a61acbbe RC |
966 | ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); |
967 | if (ret == 0) { | |
968 | ret = -ETIMEDOUT; | |
969 | } else if (ret != -ERESTARTSYS) { | |
970 | ret = 0; | |
971 | } | |
972 | ||
973 | dma_fence_put(fence); | |
824d4f9d RC |
974 | |
975 | return ret; | |
976 | } | |
977 | ||
978 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
979 | struct drm_file *file) | |
980 | { | |
981 | struct msm_drm_private *priv = dev->dev_private; | |
982 | struct drm_msm_wait_fence *args = data; | |
983 | struct msm_gpu_submitqueue *queue; | |
984 | int ret; | |
985 | ||
986 | if (args->pad) { | |
987 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
988 | return -EINVAL; | |
989 | } | |
990 | ||
991 | if (!priv->gpu) | |
992 | return 0; | |
993 | ||
994 | queue = msm_submitqueue_get(file->driver_priv, args->queueid); | |
995 | if (!queue) | |
996 | return -ENOENT; | |
997 | ||
998 | ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); | |
999 | ||
f97decac | 1000 | msm_submitqueue_put(queue); |
a61acbbe | 1001 | |
f97decac | 1002 | return ret; |
7198e6b0 RC |
1003 | } |
1004 | ||
4cd33c48 RC |
1005 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
1006 | struct drm_file *file) | |
1007 | { | |
1008 | struct drm_msm_gem_madvise *args = data; | |
1009 | struct drm_gem_object *obj; | |
1010 | int ret; | |
1011 | ||
1012 | switch (args->madv) { | |
1013 | case MSM_MADV_DONTNEED: | |
1014 | case MSM_MADV_WILLNEED: | |
1015 | break; | |
1016 | default: | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
4cd33c48 RC |
1020 | obj = drm_gem_object_lookup(file, args->handle); |
1021 | if (!obj) { | |
f92f026a | 1022 | return -ENOENT; |
4cd33c48 RC |
1023 | } |
1024 | ||
1025 | ret = msm_gem_madvise(obj, args->madv); | |
1026 | if (ret >= 0) { | |
1027 | args->retained = ret; | |
1028 | ret = 0; | |
1029 | } | |
1030 | ||
f92f026a | 1031 | drm_gem_object_put(obj); |
4cd33c48 | 1032 | |
4cd33c48 RC |
1033 | return ret; |
1034 | } | |
1035 | ||
f7de1545 JC |
1036 | |
1037 | static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, | |
1038 | struct drm_file *file) | |
1039 | { | |
1040 | struct drm_msm_submitqueue *args = data; | |
1041 | ||
1042 | if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) | |
1043 | return -EINVAL; | |
1044 | ||
f97decac | 1045 | return msm_submitqueue_create(dev, file->driver_priv, args->prio, |
f7de1545 JC |
1046 | args->flags, &args->id); |
1047 | } | |
1048 | ||
b0fb6604 JC |
1049 | static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, |
1050 | struct drm_file *file) | |
1051 | { | |
1052 | return msm_submitqueue_query(dev, file->driver_priv, data); | |
1053 | } | |
f7de1545 JC |
1054 | |
1055 | static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, | |
1056 | struct drm_file *file) | |
1057 | { | |
1058 | u32 id = *(u32 *) data; | |
1059 | ||
1060 | return msm_submitqueue_remove(file->driver_priv, id); | |
1061 | } | |
1062 | ||
7198e6b0 | 1063 | static const struct drm_ioctl_desc msm_ioctls[] = { |
34127c7a EV |
1064 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), |
1065 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), | |
1066 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), | |
1067 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), | |
1068 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), | |
1069 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), | |
1070 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), | |
1071 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), | |
1072 | DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), | |
1073 | DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), | |
1074 | DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), | |
7198e6b0 RC |
1075 | }; |
1076 | ||
510410bf | 1077 | DEFINE_DRM_GEM_FOPS(fops); |
c8afe684 | 1078 | |
70a59dd8 | 1079 | static const struct drm_driver msm_driver = { |
5b38e747 | 1080 | .driver_features = DRIVER_GEM | |
b4b15c86 | 1081 | DRIVER_RENDER | |
a5436e1d | 1082 | DRIVER_ATOMIC | |
ab723b7a BN |
1083 | DRIVER_MODESET | |
1084 | DRIVER_SYNCOBJ, | |
7198e6b0 | 1085 | .open = msm_open, |
94df145c | 1086 | .postclose = msm_postclose, |
4ccbc6e5 | 1087 | .lastclose = drm_fb_helper_lastclose, |
c8afe684 RC |
1088 | .dumb_create = msm_gem_dumb_create, |
1089 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
05b84911 RC |
1090 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
1091 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
05b84911 | 1092 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, |
510410bf | 1093 | .gem_prime_mmap = drm_gem_prime_mmap, |
c8afe684 RC |
1094 | #ifdef CONFIG_DEBUG_FS |
1095 | .debugfs_init = msm_debugfs_init, | |
c8afe684 | 1096 | #endif |
7198e6b0 | 1097 | .ioctls = msm_ioctls, |
167b606a | 1098 | .num_ioctls = ARRAY_SIZE(msm_ioctls), |
c8afe684 RC |
1099 | .fops = &fops, |
1100 | .name = "msm", | |
1101 | .desc = "MSM Snapdragon DRM", | |
1102 | .date = "20130625", | |
a8d854c1 RC |
1103 | .major = MSM_VERSION_MAJOR, |
1104 | .minor = MSM_VERSION_MINOR, | |
1105 | .patchlevel = MSM_VERSION_PATCHLEVEL, | |
c8afe684 RC |
1106 | }; |
1107 | ||
ca8199f1 | 1108 | static int __maybe_unused msm_runtime_suspend(struct device *dev) |
c8afe684 RC |
1109 | { |
1110 | struct drm_device *ddev = dev_get_drvdata(dev); | |
ec446d09 | 1111 | struct msm_drm_private *priv = ddev->dev_private; |
ca8199f1 | 1112 | struct msm_mdss *mdss = priv->mdss; |
c8afe684 | 1113 | |
ca8199f1 | 1114 | DBG(""); |
c8afe684 | 1115 | |
ca8199f1 KT |
1116 | if (mdss && mdss->funcs) |
1117 | return mdss->funcs->disable(mdss); | |
ec446d09 | 1118 | |
c8afe684 RC |
1119 | return 0; |
1120 | } | |
1121 | ||
ca8199f1 | 1122 | static int __maybe_unused msm_runtime_resume(struct device *dev) |
c8afe684 RC |
1123 | { |
1124 | struct drm_device *ddev = dev_get_drvdata(dev); | |
ec446d09 | 1125 | struct msm_drm_private *priv = ddev->dev_private; |
ca8199f1 | 1126 | struct msm_mdss *mdss = priv->mdss; |
036bfeb3 | 1127 | |
ca8199f1 | 1128 | DBG(""); |
c8afe684 | 1129 | |
ca8199f1 KT |
1130 | if (mdss && mdss->funcs) |
1131 | return mdss->funcs->enable(mdss); | |
c8afe684 | 1132 | |
ca8199f1 | 1133 | return 0; |
c8afe684 | 1134 | } |
c8afe684 | 1135 | |
ca8199f1 | 1136 | static int __maybe_unused msm_pm_suspend(struct device *dev) |
774e39ee | 1137 | { |
774e39ee | 1138 | |
ca8199f1 KT |
1139 | if (pm_runtime_suspended(dev)) |
1140 | return 0; | |
774e39ee | 1141 | |
ca8199f1 KT |
1142 | return msm_runtime_suspend(dev); |
1143 | } | |
774e39ee | 1144 | |
ca8199f1 KT |
1145 | static int __maybe_unused msm_pm_resume(struct device *dev) |
1146 | { | |
1147 | if (pm_runtime_suspended(dev)) | |
1148 | return 0; | |
1149 | ||
1150 | return msm_runtime_resume(dev); | |
774e39ee AT |
1151 | } |
1152 | ||
ca8199f1 | 1153 | static int __maybe_unused msm_pm_prepare(struct device *dev) |
774e39ee AT |
1154 | { |
1155 | struct drm_device *ddev = dev_get_drvdata(dev); | |
a9748134 FE |
1156 | struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; |
1157 | ||
1158 | if (!priv || !priv->kms) | |
1159 | return 0; | |
774e39ee | 1160 | |
ca8199f1 KT |
1161 | return drm_mode_config_helper_suspend(ddev); |
1162 | } | |
774e39ee | 1163 | |
ca8199f1 KT |
1164 | static void __maybe_unused msm_pm_complete(struct device *dev) |
1165 | { | |
1166 | struct drm_device *ddev = dev_get_drvdata(dev); | |
a9748134 FE |
1167 | struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; |
1168 | ||
1169 | if (!priv || !priv->kms) | |
1170 | return; | |
774e39ee | 1171 | |
ca8199f1 | 1172 | drm_mode_config_helper_resume(ddev); |
774e39ee | 1173 | } |
774e39ee | 1174 | |
c8afe684 RC |
1175 | static const struct dev_pm_ops msm_pm_ops = { |
1176 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
774e39ee | 1177 | SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) |
ca8199f1 KT |
1178 | .prepare = msm_pm_prepare, |
1179 | .complete = msm_pm_complete, | |
c8afe684 RC |
1180 | }; |
1181 | ||
060530f1 RC |
1182 | /* |
1183 | * Componentized driver support: | |
1184 | */ | |
1185 | ||
e9fbdaf2 AT |
1186 | /* |
1187 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
1188 | * so probably some room for some helpers | |
060530f1 RC |
1189 | */ |
1190 | static int compare_of(struct device *dev, void *data) | |
1191 | { | |
1192 | return dev->of_node == data; | |
1193 | } | |
41e69778 | 1194 | |
812070eb AT |
1195 | /* |
1196 | * Identify what components need to be added by parsing what remote-endpoints | |
1197 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there | |
1198 | * is no external component that we need to add since LVDS is within MDP4 | |
1199 | * itself. | |
1200 | */ | |
1201 | static int add_components_mdp(struct device *mdp_dev, | |
1202 | struct component_match **matchptr) | |
1203 | { | |
1204 | struct device_node *np = mdp_dev->of_node; | |
1205 | struct device_node *ep_node; | |
54011e26 AT |
1206 | struct device *master_dev; |
1207 | ||
1208 | /* | |
1209 | * on MDP4 based platforms, the MDP platform device is the component | |
1210 | * master that adds other display interface components to itself. | |
1211 | * | |
1212 | * on MDP5 based platforms, the MDSS platform device is the component | |
1213 | * master that adds MDP5 and other display interface components to | |
1214 | * itself. | |
1215 | */ | |
1216 | if (of_device_is_compatible(np, "qcom,mdp4")) | |
1217 | master_dev = mdp_dev; | |
1218 | else | |
1219 | master_dev = mdp_dev->parent; | |
812070eb AT |
1220 | |
1221 | for_each_endpoint_of_node(np, ep_node) { | |
1222 | struct device_node *intf; | |
1223 | struct of_endpoint ep; | |
1224 | int ret; | |
1225 | ||
1226 | ret = of_graph_parse_endpoint(ep_node, &ep); | |
1227 | if (ret) { | |
6a41da17 | 1228 | DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n"); |
812070eb AT |
1229 | of_node_put(ep_node); |
1230 | return ret; | |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * The LCDC/LVDS port on MDP4 is a speacial case where the | |
1235 | * remote-endpoint isn't a component that we need to add | |
1236 | */ | |
1237 | if (of_device_is_compatible(np, "qcom,mdp4") && | |
d8dd8052 | 1238 | ep.port == 0) |
812070eb | 1239 | continue; |
812070eb AT |
1240 | |
1241 | /* | |
1242 | * It's okay if some of the ports don't have a remote endpoint | |
1243 | * specified. It just means that the port isn't connected to | |
1244 | * any external interface. | |
1245 | */ | |
1246 | intf = of_graph_get_remote_port_parent(ep_node); | |
d8dd8052 | 1247 | if (!intf) |
812070eb | 1248 | continue; |
812070eb | 1249 | |
d1d9d0e1 DA |
1250 | if (of_device_is_available(intf)) |
1251 | drm_of_component_match_add(master_dev, matchptr, | |
1252 | compare_of, intf); | |
1253 | ||
812070eb | 1254 | of_node_put(intf); |
812070eb AT |
1255 | } |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
54011e26 AT |
1260 | static int compare_name_mdp(struct device *dev, void *data) |
1261 | { | |
1262 | return (strstr(dev_name(dev), "mdp") != NULL); | |
1263 | } | |
1264 | ||
8424084f | 1265 | static int add_display_components(struct platform_device *pdev, |
7d526fcf AT |
1266 | struct component_match **matchptr) |
1267 | { | |
54011e26 | 1268 | struct device *mdp_dev; |
8424084f | 1269 | struct device *dev = &pdev->dev; |
54011e26 AT |
1270 | int ret; |
1271 | ||
1272 | /* | |
25fdd593 JS |
1273 | * MDP5/DPU based devices don't have a flat hierarchy. There is a top |
1274 | * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. | |
1275 | * Populate the children devices, find the MDP5/DPU node, and then add | |
1276 | * the interfaces to our components list. | |
54011e26 | 1277 | */ |
8424084f BA |
1278 | switch (get_mdp_ver(pdev)) { |
1279 | case KMS_MDP5: | |
1280 | case KMS_DPU: | |
54011e26 AT |
1281 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); |
1282 | if (ret) { | |
6a41da17 | 1283 | DRM_DEV_ERROR(dev, "failed to populate children devices\n"); |
54011e26 AT |
1284 | return ret; |
1285 | } | |
1286 | ||
1287 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); | |
1288 | if (!mdp_dev) { | |
6a41da17 | 1289 | DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n"); |
54011e26 AT |
1290 | of_platform_depopulate(dev); |
1291 | return -ENODEV; | |
1292 | } | |
1293 | ||
1294 | put_device(mdp_dev); | |
1295 | ||
1296 | /* add the MDP component itself */ | |
97ac0e47 RK |
1297 | drm_of_component_match_add(dev, matchptr, compare_of, |
1298 | mdp_dev->of_node); | |
8424084f BA |
1299 | break; |
1300 | case KMS_MDP4: | |
54011e26 AT |
1301 | /* MDP4 */ |
1302 | mdp_dev = dev; | |
8424084f | 1303 | break; |
54011e26 AT |
1304 | } |
1305 | ||
1306 | ret = add_components_mdp(mdp_dev, matchptr); | |
1307 | if (ret) | |
1308 | of_platform_depopulate(dev); | |
1309 | ||
1310 | return ret; | |
7d526fcf AT |
1311 | } |
1312 | ||
dc3ea265 AT |
1313 | /* |
1314 | * We don't know what's the best binding to link the gpu with the drm device. | |
1315 | * Fow now, we just hunt for all the possible gpus that we support, and add them | |
1316 | * as components. | |
1317 | */ | |
1318 | static const struct of_device_id msm_gpu_match[] = { | |
1db7afa4 | 1319 | { .compatible = "qcom,adreno" }, |
dc3ea265 | 1320 | { .compatible = "qcom,adreno-3xx" }, |
e6f6d63e | 1321 | { .compatible = "amd,imageon" }, |
dc3ea265 AT |
1322 | { .compatible = "qcom,kgsl-3d0" }, |
1323 | { }, | |
1324 | }; | |
1325 | ||
7d526fcf AT |
1326 | static int add_gpu_components(struct device *dev, |
1327 | struct component_match **matchptr) | |
1328 | { | |
dc3ea265 AT |
1329 | struct device_node *np; |
1330 | ||
1331 | np = of_find_matching_node(NULL, msm_gpu_match); | |
1332 | if (!np) | |
1333 | return 0; | |
1334 | ||
9ca7ad6c JH |
1335 | if (of_device_is_available(np)) |
1336 | drm_of_component_match_add(dev, matchptr, compare_of, np); | |
dc3ea265 AT |
1337 | |
1338 | of_node_put(np); | |
1339 | ||
1340 | return 0; | |
7d526fcf AT |
1341 | } |
1342 | ||
84448288 RK |
1343 | static int msm_drm_bind(struct device *dev) |
1344 | { | |
2b669875 | 1345 | return msm_drm_init(dev, &msm_driver); |
84448288 RK |
1346 | } |
1347 | ||
1348 | static void msm_drm_unbind(struct device *dev) | |
1349 | { | |
2b669875 | 1350 | msm_drm_uninit(dev); |
84448288 RK |
1351 | } |
1352 | ||
1353 | static const struct component_master_ops msm_drm_ops = { | |
1354 | .bind = msm_drm_bind, | |
1355 | .unbind = msm_drm_unbind, | |
1356 | }; | |
1357 | ||
1358 | /* | |
1359 | * Platform driver: | |
1360 | */ | |
060530f1 | 1361 | |
84448288 | 1362 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1363 | { |
84448288 | 1364 | struct component_match *match = NULL; |
7d526fcf AT |
1365 | int ret; |
1366 | ||
e6f6d63e | 1367 | if (get_mdp_ver(pdev)) { |
8424084f | 1368 | ret = add_display_components(pdev, &match); |
e6f6d63e JM |
1369 | if (ret) |
1370 | return ret; | |
1371 | } | |
e9fbdaf2 | 1372 | |
7d526fcf AT |
1373 | ret = add_gpu_components(&pdev->dev, &match); |
1374 | if (ret) | |
4368a153 | 1375 | goto fail; |
060530f1 | 1376 | |
c83ea576 RC |
1377 | /* on all devices that I am aware of, iommu's which can map |
1378 | * any address the cpu can see are used: | |
1379 | */ | |
1380 | ret = dma_set_mask_and_coherent(&pdev->dev, ~0); | |
1381 | if (ret) | |
4368a153 SP |
1382 | goto fail; |
1383 | ||
1384 | ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); | |
1385 | if (ret) | |
1386 | goto fail; | |
c83ea576 | 1387 | |
4368a153 SP |
1388 | return 0; |
1389 | ||
1390 | fail: | |
1391 | of_platform_depopulate(&pdev->dev); | |
1392 | return ret; | |
c8afe684 RC |
1393 | } |
1394 | ||
1395 | static int msm_pdev_remove(struct platform_device *pdev) | |
1396 | { | |
060530f1 | 1397 | component_master_del(&pdev->dev, &msm_drm_ops); |
54011e26 | 1398 | of_platform_depopulate(&pdev->dev); |
c8afe684 RC |
1399 | |
1400 | return 0; | |
1401 | } | |
1402 | ||
9d5cbf5f KM |
1403 | static void msm_pdev_shutdown(struct platform_device *pdev) |
1404 | { | |
1405 | struct drm_device *drm = platform_get_drvdata(pdev); | |
623f279c DB |
1406 | struct msm_drm_private *priv = drm ? drm->dev_private : NULL; |
1407 | ||
1408 | if (!priv || !priv->kms) | |
1409 | return; | |
9d5cbf5f KM |
1410 | |
1411 | drm_atomic_helper_shutdown(drm); | |
1412 | } | |
1413 | ||
06c0dd96 | 1414 | static const struct of_device_id dt_match[] = { |
aaded2e3 JS |
1415 | { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, |
1416 | { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, | |
25fdd593 | 1417 | { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, |
7bdc0c4b | 1418 | { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, |
591e34a0 | 1419 | { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU }, |
0ba17e7a JM |
1420 | { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU }, |
1421 | { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU }, | |
06c0dd96 RC |
1422 | {} |
1423 | }; | |
1424 | MODULE_DEVICE_TABLE(of, dt_match); | |
1425 | ||
c8afe684 RC |
1426 | static struct platform_driver msm_platform_driver = { |
1427 | .probe = msm_pdev_probe, | |
1428 | .remove = msm_pdev_remove, | |
9d5cbf5f | 1429 | .shutdown = msm_pdev_shutdown, |
c8afe684 | 1430 | .driver = { |
c8afe684 | 1431 | .name = "msm", |
06c0dd96 | 1432 | .of_match_table = dt_match, |
c8afe684 RC |
1433 | .pm = &msm_pm_ops, |
1434 | }, | |
c8afe684 RC |
1435 | }; |
1436 | ||
1437 | static int __init msm_drm_register(void) | |
1438 | { | |
ba4dd718 RC |
1439 | if (!modeset) |
1440 | return -EINVAL; | |
1441 | ||
c8afe684 | 1442 | DBG("init"); |
1dd0a0b1 | 1443 | msm_mdp_register(); |
25fdd593 | 1444 | msm_dpu_register(); |
d5af49c9 | 1445 | msm_dsi_register(); |
00453981 | 1446 | msm_edp_register(); |
fcda50c8 | 1447 | msm_hdmi_register(); |
c943b494 | 1448 | msm_dp_register(); |
bfd28b13 | 1449 | adreno_register(); |
c8afe684 RC |
1450 | return platform_driver_register(&msm_platform_driver); |
1451 | } | |
1452 | ||
1453 | static void __exit msm_drm_unregister(void) | |
1454 | { | |
1455 | DBG("fini"); | |
1456 | platform_driver_unregister(&msm_platform_driver); | |
c943b494 | 1457 | msm_dp_unregister(); |
fcda50c8 | 1458 | msm_hdmi_unregister(); |
bfd28b13 | 1459 | adreno_unregister(); |
00453981 | 1460 | msm_edp_unregister(); |
d5af49c9 | 1461 | msm_dsi_unregister(); |
1dd0a0b1 | 1462 | msm_mdp_unregister(); |
25fdd593 | 1463 | msm_dpu_unregister(); |
c8afe684 RC |
1464 | } |
1465 | ||
1466 | module_init(msm_drm_register); | |
1467 | module_exit(msm_drm_unregister); | |
1468 | ||
1469 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1470 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1471 | MODULE_LICENSE("GPL"); |