]>
Commit | Line | Data |
---|---|---|
c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
97ac0e47 RK |
18 | #include <drm/drm_of.h> |
19 | ||
c8afe684 | 20 | #include "msm_drv.h" |
edcd60ce | 21 | #include "msm_debugfs.h" |
fde5de6c | 22 | #include "msm_fence.h" |
7198e6b0 | 23 | #include "msm_gpu.h" |
dd2da6e3 | 24 | #include "msm_kms.h" |
c8afe684 | 25 | |
a8d854c1 RC |
26 | |
27 | /* | |
28 | * MSM driver version: | |
29 | * - 1.0.0 - initial interface | |
30 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers | |
7a3bcc0a | 31 | * - 1.2.0 - adds explicit fence support for submit ioctl |
a8d854c1 RC |
32 | */ |
33 | #define MSM_VERSION_MAJOR 1 | |
7a3bcc0a | 34 | #define MSM_VERSION_MINOR 2 |
a8d854c1 RC |
35 | #define MSM_VERSION_PATCHLEVEL 0 |
36 | ||
c8afe684 RC |
37 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
38 | { | |
39 | struct msm_drm_private *priv = dev->dev_private; | |
40 | if (priv->fbdev) | |
41 | drm_fb_helper_hotplug_event(priv->fbdev); | |
42 | } | |
43 | ||
44 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
45 | .fb_create = msm_framebuffer_create, | |
46 | .output_poll_changed = msm_fb_output_poll_changed, | |
b4274fbe | 47 | .atomic_check = msm_atomic_check, |
cf3a7e4c | 48 | .atomic_commit = msm_atomic_commit, |
870d738a RC |
49 | .atomic_state_alloc = msm_atomic_state_alloc, |
50 | .atomic_state_clear = msm_atomic_state_clear, | |
51 | .atomic_state_free = msm_atomic_state_free, | |
c8afe684 RC |
52 | }; |
53 | ||
667ce33e RC |
54 | int msm_register_address_space(struct drm_device *dev, |
55 | struct msm_gem_address_space *aspace) | |
c8afe684 RC |
56 | { |
57 | struct msm_drm_private *priv = dev->dev_private; | |
c8afe684 | 58 | |
36849cc3 | 59 | if (WARN_ON(priv->num_aspaces >= ARRAY_SIZE(priv->aspace))) |
c8afe684 RC |
60 | return -EINVAL; |
61 | ||
36849cc3 | 62 | priv->aspace[priv->num_aspaces] = aspace; |
c8afe684 | 63 | |
36849cc3 | 64 | return priv->num_aspaces++; |
c8afe684 RC |
65 | } |
66 | ||
c8afe684 RC |
67 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
68 | static bool reglog = false; | |
69 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
70 | module_param(reglog, bool, 0600); | |
71 | #else | |
72 | #define reglog 0 | |
73 | #endif | |
74 | ||
a9ee34b7 | 75 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 RC |
76 | static bool fbdev = true; |
77 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); | |
78 | module_param(fbdev, bool, 0600); | |
79 | #endif | |
80 | ||
3a10ba8c | 81 | static char *vram = "16m"; |
4313c744 | 82 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
871d812a RC |
83 | module_param(vram, charp, 0); |
84 | ||
06d9f56f RC |
85 | bool dumpstate = false; |
86 | MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); | |
87 | module_param(dumpstate, bool, 0600); | |
88 | ||
060530f1 RC |
89 | /* |
90 | * Util/helpers: | |
91 | */ | |
92 | ||
720c3bb8 RC |
93 | struct clk *msm_clk_get(struct platform_device *pdev, const char *name) |
94 | { | |
95 | struct clk *clk; | |
96 | char name2[32]; | |
97 | ||
98 | clk = devm_clk_get(&pdev->dev, name); | |
99 | if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) | |
100 | return clk; | |
101 | ||
102 | snprintf(name2, sizeof(name2), "%s_clk", name); | |
103 | ||
104 | clk = devm_clk_get(&pdev->dev, name2); | |
105 | if (!IS_ERR(clk)) | |
106 | dev_warn(&pdev->dev, "Using legacy clk name binding. Use " | |
107 | "\"%s\" instead of \"%s\"\n", name, name2); | |
108 | ||
109 | return clk; | |
110 | } | |
111 | ||
c8afe684 RC |
112 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
113 | const char *dbgname) | |
114 | { | |
115 | struct resource *res; | |
116 | unsigned long size; | |
117 | void __iomem *ptr; | |
118 | ||
119 | if (name) | |
120 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
121 | else | |
122 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
123 | ||
124 | if (!res) { | |
125 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
126 | return ERR_PTR(-EINVAL); | |
127 | } | |
128 | ||
129 | size = resource_size(res); | |
130 | ||
131 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
132 | if (!ptr) { | |
133 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
134 | return ERR_PTR(-ENOMEM); | |
135 | } | |
136 | ||
137 | if (reglog) | |
fc99f97a | 138 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
c8afe684 RC |
139 | |
140 | return ptr; | |
141 | } | |
142 | ||
143 | void msm_writel(u32 data, void __iomem *addr) | |
144 | { | |
145 | if (reglog) | |
fc99f97a | 146 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
c8afe684 RC |
147 | writel(data, addr); |
148 | } | |
149 | ||
150 | u32 msm_readl(const void __iomem *addr) | |
151 | { | |
152 | u32 val = readl(addr); | |
153 | if (reglog) | |
8dfe162a | 154 | pr_err("IO:R %p %08x\n", addr, val); |
c8afe684 RC |
155 | return val; |
156 | } | |
157 | ||
78b1d470 HL |
158 | struct vblank_event { |
159 | struct list_head node; | |
160 | int crtc_id; | |
161 | bool enable; | |
162 | }; | |
163 | ||
164 | static void vblank_ctrl_worker(struct work_struct *work) | |
165 | { | |
166 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, | |
167 | struct msm_vblank_ctrl, work); | |
168 | struct msm_drm_private *priv = container_of(vbl_ctrl, | |
169 | struct msm_drm_private, vblank_ctrl); | |
170 | struct msm_kms *kms = priv->kms; | |
171 | struct vblank_event *vbl_ev, *tmp; | |
172 | unsigned long flags; | |
173 | ||
174 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
175 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
176 | list_del(&vbl_ev->node); | |
177 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
178 | ||
179 | if (vbl_ev->enable) | |
180 | kms->funcs->enable_vblank(kms, | |
181 | priv->crtcs[vbl_ev->crtc_id]); | |
182 | else | |
183 | kms->funcs->disable_vblank(kms, | |
184 | priv->crtcs[vbl_ev->crtc_id]); | |
185 | ||
186 | kfree(vbl_ev); | |
187 | ||
188 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
189 | } | |
190 | ||
191 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
192 | } | |
193 | ||
194 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, | |
195 | int crtc_id, bool enable) | |
196 | { | |
197 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; | |
198 | struct vblank_event *vbl_ev; | |
199 | unsigned long flags; | |
200 | ||
201 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); | |
202 | if (!vbl_ev) | |
203 | return -ENOMEM; | |
204 | ||
205 | vbl_ev->crtc_id = crtc_id; | |
206 | vbl_ev->enable = enable; | |
207 | ||
208 | spin_lock_irqsave(&vbl_ctrl->lock, flags); | |
209 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); | |
210 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); | |
211 | ||
212 | queue_work(priv->wq, &vbl_ctrl->work); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
2b669875 | 217 | static int msm_drm_uninit(struct device *dev) |
c8afe684 | 218 | { |
2b669875 AT |
219 | struct platform_device *pdev = to_platform_device(dev); |
220 | struct drm_device *ddev = platform_get_drvdata(pdev); | |
221 | struct msm_drm_private *priv = ddev->dev_private; | |
c8afe684 | 222 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 223 | struct msm_gpu *gpu = priv->gpu; |
78b1d470 HL |
224 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
225 | struct vblank_event *vbl_ev, *tmp; | |
226 | ||
227 | /* We must cancel and cleanup any pending vblank enable/disable | |
228 | * work before drm_irq_uninstall() to avoid work re-enabling an | |
229 | * irq after uninstall has disabled it. | |
230 | */ | |
231 | cancel_work_sync(&vbl_ctrl->work); | |
232 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { | |
233 | list_del(&vbl_ev->node); | |
234 | kfree(vbl_ev); | |
235 | } | |
c8afe684 | 236 | |
68209390 RC |
237 | msm_gem_shrinker_cleanup(ddev); |
238 | ||
2b669875 AT |
239 | drm_kms_helper_poll_fini(ddev); |
240 | ||
2b669875 | 241 | drm_dev_unregister(ddev); |
8208ed93 | 242 | |
85eac470 NT |
243 | msm_perf_debugfs_cleanup(priv); |
244 | msm_rd_debugfs_cleanup(priv); | |
245 | ||
1aaa57f5 AT |
246 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
247 | if (fbdev && priv->fbdev) | |
2b669875 | 248 | msm_fbdev_free(ddev); |
1aaa57f5 | 249 | #endif |
2b669875 | 250 | drm_mode_config_cleanup(ddev); |
c8afe684 | 251 | |
2b669875 AT |
252 | pm_runtime_get_sync(dev); |
253 | drm_irq_uninstall(ddev); | |
254 | pm_runtime_put_sync(dev); | |
c8afe684 RC |
255 | |
256 | flush_workqueue(priv->wq); | |
257 | destroy_workqueue(priv->wq); | |
258 | ||
ba00c3f2 RC |
259 | flush_workqueue(priv->atomic_wq); |
260 | destroy_workqueue(priv->atomic_wq); | |
261 | ||
16976085 | 262 | if (kms && kms->funcs) |
c8afe684 | 263 | kms->funcs->destroy(kms); |
c8afe684 | 264 | |
7198e6b0 | 265 | if (gpu) { |
2b669875 | 266 | mutex_lock(&ddev->struct_mutex); |
eeb75474 RC |
267 | // XXX what do we do here? |
268 | //pm_runtime_enable(&pdev->dev); | |
7198e6b0 | 269 | gpu->funcs->pm_suspend(gpu); |
2b669875 | 270 | mutex_unlock(&ddev->struct_mutex); |
774449eb | 271 | gpu->funcs->destroy(gpu); |
7198e6b0 | 272 | } |
c8afe684 | 273 | |
871d812a | 274 | if (priv->vram.paddr) { |
00085f1e | 275 | unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
871d812a | 276 | drm_mm_takedown(&priv->vram.mm); |
2b669875 | 277 | dma_free_attrs(dev, priv->vram.size, NULL, |
00085f1e | 278 | priv->vram.paddr, attrs); |
871d812a RC |
279 | } |
280 | ||
2b669875 | 281 | component_unbind_all(dev, ddev); |
060530f1 | 282 | |
0a6030d2 AT |
283 | msm_mdss_destroy(ddev); |
284 | ||
2b669875 AT |
285 | ddev->dev_private = NULL; |
286 | drm_dev_unref(ddev); | |
c8afe684 RC |
287 | |
288 | kfree(priv); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
06c0dd96 RC |
293 | static int get_mdp_ver(struct platform_device *pdev) |
294 | { | |
06c0dd96 | 295 | struct device *dev = &pdev->dev; |
e9fbdaf2 AT |
296 | |
297 | return (int) (unsigned long) of_device_get_match_data(dev); | |
06c0dd96 RC |
298 | } |
299 | ||
072f1f91 RC |
300 | #include <linux/of_address.h> |
301 | ||
5bf9c0b6 | 302 | static int msm_init_vram(struct drm_device *dev) |
c8afe684 | 303 | { |
5bf9c0b6 | 304 | struct msm_drm_private *priv = dev->dev_private; |
e9fbdaf2 | 305 | struct device_node *node; |
072f1f91 RC |
306 | unsigned long size = 0; |
307 | int ret = 0; | |
308 | ||
072f1f91 RC |
309 | /* In the device-tree world, we could have a 'memory-region' |
310 | * phandle, which gives us a link to our "vram". Allocating | |
311 | * is all nicely abstracted behind the dma api, but we need | |
312 | * to know the entire size to allocate it all in one go. There | |
313 | * are two cases: | |
314 | * 1) device with no IOMMU, in which case we need exclusive | |
315 | * access to a VRAM carveout big enough for all gpu | |
316 | * buffers | |
317 | * 2) device with IOMMU, but where the bootloader puts up | |
318 | * a splash screen. In this case, the VRAM carveout | |
319 | * need only be large enough for fbdev fb. But we need | |
320 | * exclusive access to the buffer to avoid the kernel | |
321 | * using those pages for other purposes (which appears | |
322 | * as corruption on screen before we have a chance to | |
323 | * load and do initial modeset) | |
324 | */ | |
072f1f91 RC |
325 | |
326 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); | |
327 | if (node) { | |
328 | struct resource r; | |
329 | ret = of_address_to_resource(node, 0, &r); | |
2ca41c17 | 330 | of_node_put(node); |
072f1f91 RC |
331 | if (ret) |
332 | return ret; | |
333 | size = r.end - r.start; | |
fc99f97a | 334 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
c8afe684 | 335 | |
e9fbdaf2 AT |
336 | /* if we have no IOMMU, then we need to use carveout allocator. |
337 | * Grab the entire CMA chunk carved out in early startup in | |
338 | * mach-msm: | |
339 | */ | |
340 | } else if (!iommu_present(&platform_bus_type)) { | |
072f1f91 RC |
341 | DRM_INFO("using %s VRAM carveout\n", vram); |
342 | size = memparse(vram, NULL); | |
343 | } | |
344 | ||
345 | if (size) { | |
00085f1e | 346 | unsigned long attrs = 0; |
871d812a RC |
347 | void *p; |
348 | ||
871d812a RC |
349 | priv->vram.size = size; |
350 | ||
351 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
352 | ||
00085f1e KK |
353 | attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
354 | attrs |= DMA_ATTR_WRITE_COMBINE; | |
871d812a RC |
355 | |
356 | /* note that for no-kernel-mapping, the vaddr returned | |
357 | * is bogus, but non-null if allocation succeeded: | |
358 | */ | |
359 | p = dma_alloc_attrs(dev->dev, size, | |
00085f1e | 360 | &priv->vram.paddr, GFP_KERNEL, attrs); |
871d812a RC |
361 | if (!p) { |
362 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
363 | priv->vram.paddr = 0; | |
5bf9c0b6 | 364 | return -ENOMEM; |
871d812a RC |
365 | } |
366 | ||
367 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
368 | (uint32_t)priv->vram.paddr, | |
369 | (uint32_t)(priv->vram.paddr + size)); | |
370 | } | |
371 | ||
072f1f91 | 372 | return ret; |
5bf9c0b6 RC |
373 | } |
374 | ||
2b669875 | 375 | static int msm_drm_init(struct device *dev, struct drm_driver *drv) |
5bf9c0b6 | 376 | { |
2b669875 AT |
377 | struct platform_device *pdev = to_platform_device(dev); |
378 | struct drm_device *ddev; | |
5bf9c0b6 RC |
379 | struct msm_drm_private *priv; |
380 | struct msm_kms *kms; | |
381 | int ret; | |
382 | ||
2b669875 | 383 | ddev = drm_dev_alloc(drv, dev); |
0f288605 | 384 | if (IS_ERR(ddev)) { |
2b669875 | 385 | dev_err(dev, "failed to allocate drm_device\n"); |
0f288605 | 386 | return PTR_ERR(ddev); |
2b669875 AT |
387 | } |
388 | ||
389 | platform_set_drvdata(pdev, ddev); | |
2b669875 | 390 | |
5bf9c0b6 RC |
391 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
392 | if (!priv) { | |
2b669875 | 393 | drm_dev_unref(ddev); |
5bf9c0b6 RC |
394 | return -ENOMEM; |
395 | } | |
396 | ||
2b669875 | 397 | ddev->dev_private = priv; |
68209390 | 398 | priv->dev = ddev; |
5bf9c0b6 | 399 | |
0a6030d2 AT |
400 | ret = msm_mdss_init(ddev); |
401 | if (ret) { | |
402 | kfree(priv); | |
403 | drm_dev_unref(ddev); | |
404 | return ret; | |
405 | } | |
406 | ||
5bf9c0b6 | 407 | priv->wq = alloc_ordered_workqueue("msm", 0); |
ba00c3f2 | 408 | priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0); |
5bf9c0b6 RC |
409 | init_waitqueue_head(&priv->pending_crtcs_event); |
410 | ||
411 | INIT_LIST_HEAD(&priv->inactive_list); | |
78b1d470 HL |
412 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
413 | INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker); | |
414 | spin_lock_init(&priv->vblank_ctrl.lock); | |
5bf9c0b6 | 415 | |
2b669875 | 416 | drm_mode_config_init(ddev); |
060530f1 RC |
417 | |
418 | /* Bind all our sub-components: */ | |
2b669875 AT |
419 | ret = component_bind_all(dev, ddev); |
420 | if (ret) { | |
0a6030d2 | 421 | msm_mdss_destroy(ddev); |
2b669875 AT |
422 | kfree(priv); |
423 | drm_dev_unref(ddev); | |
060530f1 | 424 | return ret; |
2b669875 | 425 | } |
060530f1 | 426 | |
2b669875 | 427 | ret = msm_init_vram(ddev); |
13f15565 RC |
428 | if (ret) |
429 | goto fail; | |
430 | ||
68209390 RC |
431 | msm_gem_shrinker_init(ddev); |
432 | ||
06c0dd96 RC |
433 | switch (get_mdp_ver(pdev)) { |
434 | case 4: | |
2b669875 | 435 | kms = mdp4_kms_init(ddev); |
0a6030d2 | 436 | priv->kms = kms; |
06c0dd96 RC |
437 | break; |
438 | case 5: | |
392ae6e0 | 439 | kms = mdp5_kms_init(ddev); |
06c0dd96 RC |
440 | break; |
441 | default: | |
442 | kms = ERR_PTR(-ENODEV); | |
443 | break; | |
444 | } | |
445 | ||
c8afe684 RC |
446 | if (IS_ERR(kms)) { |
447 | /* | |
448 | * NOTE: once we have GPU support, having no kms should not | |
449 | * be considered fatal.. ideally we would still support gpu | |
450 | * and (for example) use dmabuf/prime to share buffers with | |
451 | * imx drm driver on iMX5 | |
452 | */ | |
2b669875 | 453 | dev_err(dev, "failed to load kms\n"); |
e4826a94 | 454 | ret = PTR_ERR(kms); |
c8afe684 RC |
455 | goto fail; |
456 | } | |
457 | ||
c8afe684 | 458 | if (kms) { |
c8afe684 RC |
459 | ret = kms->funcs->hw_init(kms); |
460 | if (ret) { | |
2b669875 | 461 | dev_err(dev, "kms hw init failed: %d\n", ret); |
c8afe684 RC |
462 | goto fail; |
463 | } | |
464 | } | |
465 | ||
2b669875 | 466 | ddev->mode_config.funcs = &mode_config_funcs; |
c8afe684 | 467 | |
2b669875 | 468 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
c8afe684 | 469 | if (ret < 0) { |
2b669875 | 470 | dev_err(dev, "failed to initialize vblank\n"); |
c8afe684 RC |
471 | goto fail; |
472 | } | |
473 | ||
a2b3a557 AT |
474 | if (kms) { |
475 | pm_runtime_get_sync(dev); | |
476 | ret = drm_irq_install(ddev, kms->irq); | |
477 | pm_runtime_put_sync(dev); | |
478 | if (ret < 0) { | |
479 | dev_err(dev, "failed to install IRQ handler\n"); | |
480 | goto fail; | |
481 | } | |
c8afe684 RC |
482 | } |
483 | ||
2b669875 AT |
484 | ret = drm_dev_register(ddev, 0); |
485 | if (ret) | |
486 | goto fail; | |
487 | ||
2b669875 | 488 | drm_mode_config_reset(ddev); |
cf3a7e4c | 489 | |
a9ee34b7 | 490 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
e90dfec7 | 491 | if (fbdev) |
2b669875 | 492 | priv->fbdev = msm_fbdev_init(ddev); |
c8afe684 RC |
493 | #endif |
494 | ||
2b669875 | 495 | ret = msm_debugfs_late_init(ddev); |
a7d3c950 RC |
496 | if (ret) |
497 | goto fail; | |
498 | ||
2b669875 | 499 | drm_kms_helper_poll_init(ddev); |
c8afe684 RC |
500 | |
501 | return 0; | |
502 | ||
503 | fail: | |
2b669875 | 504 | msm_drm_uninit(dev); |
c8afe684 RC |
505 | return ret; |
506 | } | |
507 | ||
2b669875 AT |
508 | /* |
509 | * DRM operations: | |
510 | */ | |
511 | ||
7198e6b0 RC |
512 | static void load_gpu(struct drm_device *dev) |
513 | { | |
a1ad3523 | 514 | static DEFINE_MUTEX(init_lock); |
7198e6b0 | 515 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 516 | |
a1ad3523 RC |
517 | mutex_lock(&init_lock); |
518 | ||
e2550b7a RC |
519 | if (!priv->gpu) |
520 | priv->gpu = adreno_load_gpu(dev); | |
7198e6b0 | 521 | |
a1ad3523 | 522 | mutex_unlock(&init_lock); |
7198e6b0 RC |
523 | } |
524 | ||
525 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
526 | { | |
527 | struct msm_file_private *ctx; | |
528 | ||
529 | /* For now, load gpu on open.. to avoid the requirement of having | |
530 | * firmware in the initrd. | |
531 | */ | |
532 | load_gpu(dev); | |
533 | ||
534 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
535 | if (!ctx) | |
536 | return -ENOMEM; | |
537 | ||
538 | file->driver_priv = ctx; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
94df145c | 543 | static void msm_postclose(struct drm_device *dev, struct drm_file *file) |
c8afe684 RC |
544 | { |
545 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 546 | struct msm_file_private *ctx = file->driver_priv; |
7198e6b0 | 547 | |
7198e6b0 RC |
548 | mutex_lock(&dev->struct_mutex); |
549 | if (ctx == priv->lastctx) | |
550 | priv->lastctx = NULL; | |
551 | mutex_unlock(&dev->struct_mutex); | |
552 | ||
553 | kfree(ctx); | |
c8afe684 RC |
554 | } |
555 | ||
556 | static void msm_lastclose(struct drm_device *dev) | |
557 | { | |
558 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
559 | if (priv->fbdev) |
560 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
561 | } |
562 | ||
e9f0d76f | 563 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
564 | { |
565 | struct drm_device *dev = arg; | |
566 | struct msm_drm_private *priv = dev->dev_private; | |
567 | struct msm_kms *kms = priv->kms; | |
568 | BUG_ON(!kms); | |
569 | return kms->funcs->irq(kms); | |
570 | } | |
571 | ||
572 | static void msm_irq_preinstall(struct drm_device *dev) | |
573 | { | |
574 | struct msm_drm_private *priv = dev->dev_private; | |
575 | struct msm_kms *kms = priv->kms; | |
576 | BUG_ON(!kms); | |
577 | kms->funcs->irq_preinstall(kms); | |
578 | } | |
579 | ||
580 | static int msm_irq_postinstall(struct drm_device *dev) | |
581 | { | |
582 | struct msm_drm_private *priv = dev->dev_private; | |
583 | struct msm_kms *kms = priv->kms; | |
584 | BUG_ON(!kms); | |
585 | return kms->funcs->irq_postinstall(kms); | |
586 | } | |
587 | ||
588 | static void msm_irq_uninstall(struct drm_device *dev) | |
589 | { | |
590 | struct msm_drm_private *priv = dev->dev_private; | |
591 | struct msm_kms *kms = priv->kms; | |
592 | BUG_ON(!kms); | |
593 | kms->funcs->irq_uninstall(kms); | |
594 | } | |
595 | ||
88e72717 | 596 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
597 | { |
598 | struct msm_drm_private *priv = dev->dev_private; | |
599 | struct msm_kms *kms = priv->kms; | |
600 | if (!kms) | |
601 | return -ENXIO; | |
88e72717 TR |
602 | DBG("dev=%p, crtc=%u", dev, pipe); |
603 | return vblank_ctrl_queue_work(priv, pipe, true); | |
c8afe684 RC |
604 | } |
605 | ||
88e72717 | 606 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
c8afe684 RC |
607 | { |
608 | struct msm_drm_private *priv = dev->dev_private; | |
609 | struct msm_kms *kms = priv->kms; | |
610 | if (!kms) | |
611 | return; | |
88e72717 TR |
612 | DBG("dev=%p, crtc=%u", dev, pipe); |
613 | vblank_ctrl_queue_work(priv, pipe, false); | |
c8afe684 RC |
614 | } |
615 | ||
7198e6b0 RC |
616 | /* |
617 | * DRM ioctls: | |
618 | */ | |
619 | ||
620 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
621 | struct drm_file *file) | |
622 | { | |
623 | struct msm_drm_private *priv = dev->dev_private; | |
624 | struct drm_msm_param *args = data; | |
625 | struct msm_gpu *gpu; | |
626 | ||
627 | /* for now, we just have 3d pipe.. eventually this would need to | |
628 | * be more clever to dispatch to appropriate gpu module: | |
629 | */ | |
630 | if (args->pipe != MSM_PIPE_3D0) | |
631 | return -EINVAL; | |
632 | ||
633 | gpu = priv->gpu; | |
634 | ||
635 | if (!gpu) | |
636 | return -ENXIO; | |
637 | ||
638 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
639 | } | |
640 | ||
641 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
642 | struct drm_file *file) | |
643 | { | |
644 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
645 | |
646 | if (args->flags & ~MSM_BO_FLAGS) { | |
647 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
7198e6b0 RC |
651 | return msm_gem_new_handle(dev, file, args->size, |
652 | args->flags, &args->handle); | |
653 | } | |
654 | ||
56c2da83 RC |
655 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
656 | { | |
657 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); | |
658 | } | |
7198e6b0 RC |
659 | |
660 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
661 | struct drm_file *file) | |
662 | { | |
663 | struct drm_msm_gem_cpu_prep *args = data; | |
664 | struct drm_gem_object *obj; | |
56c2da83 | 665 | ktime_t timeout = to_ktime(args->timeout); |
7198e6b0 RC |
666 | int ret; |
667 | ||
93ddb0d3 RC |
668 | if (args->op & ~MSM_PREP_FLAGS) { |
669 | DRM_ERROR("invalid op: %08x\n", args->op); | |
670 | return -EINVAL; | |
671 | } | |
672 | ||
a8ad0bd8 | 673 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
674 | if (!obj) |
675 | return -ENOENT; | |
676 | ||
56c2da83 | 677 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
7198e6b0 RC |
678 | |
679 | drm_gem_object_unreference_unlocked(obj); | |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
684 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
685 | struct drm_file *file) | |
686 | { | |
687 | struct drm_msm_gem_cpu_fini *args = data; | |
688 | struct drm_gem_object *obj; | |
689 | int ret; | |
690 | ||
a8ad0bd8 | 691 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
692 | if (!obj) |
693 | return -ENOENT; | |
694 | ||
695 | ret = msm_gem_cpu_fini(obj); | |
696 | ||
697 | drm_gem_object_unreference_unlocked(obj); | |
698 | ||
699 | return ret; | |
700 | } | |
701 | ||
702 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
703 | struct drm_file *file) | |
704 | { | |
705 | struct drm_msm_gem_info *args = data; | |
706 | struct drm_gem_object *obj; | |
707 | int ret = 0; | |
708 | ||
709 | if (args->pad) | |
710 | return -EINVAL; | |
711 | ||
a8ad0bd8 | 712 | obj = drm_gem_object_lookup(file, args->handle); |
7198e6b0 RC |
713 | if (!obj) |
714 | return -ENOENT; | |
715 | ||
716 | args->offset = msm_gem_mmap_offset(obj); | |
717 | ||
718 | drm_gem_object_unreference_unlocked(obj); | |
719 | ||
720 | return ret; | |
721 | } | |
722 | ||
723 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
724 | struct drm_file *file) | |
725 | { | |
ca762a8a | 726 | struct msm_drm_private *priv = dev->dev_private; |
7198e6b0 | 727 | struct drm_msm_wait_fence *args = data; |
56c2da83 | 728 | ktime_t timeout = to_ktime(args->timeout); |
93ddb0d3 RC |
729 | |
730 | if (args->pad) { | |
731 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
732 | return -EINVAL; | |
733 | } | |
734 | ||
ca762a8a RC |
735 | if (!priv->gpu) |
736 | return 0; | |
737 | ||
738 | return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true); | |
7198e6b0 RC |
739 | } |
740 | ||
4cd33c48 RC |
741 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
742 | struct drm_file *file) | |
743 | { | |
744 | struct drm_msm_gem_madvise *args = data; | |
745 | struct drm_gem_object *obj; | |
746 | int ret; | |
747 | ||
748 | switch (args->madv) { | |
749 | case MSM_MADV_DONTNEED: | |
750 | case MSM_MADV_WILLNEED: | |
751 | break; | |
752 | default: | |
753 | return -EINVAL; | |
754 | } | |
755 | ||
756 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
757 | if (ret) | |
758 | return ret; | |
759 | ||
760 | obj = drm_gem_object_lookup(file, args->handle); | |
761 | if (!obj) { | |
762 | ret = -ENOENT; | |
763 | goto unlock; | |
764 | } | |
765 | ||
766 | ret = msm_gem_madvise(obj, args->madv); | |
767 | if (ret >= 0) { | |
768 | args->retained = ret; | |
769 | ret = 0; | |
770 | } | |
771 | ||
772 | drm_gem_object_unreference(obj); | |
773 | ||
774 | unlock: | |
775 | mutex_unlock(&dev->struct_mutex); | |
776 | return ret; | |
777 | } | |
778 | ||
7198e6b0 | 779 | static const struct drm_ioctl_desc msm_ioctls[] = { |
f8c47144 DV |
780 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
781 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
782 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
783 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
784 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
785 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), | |
786 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), | |
4cd33c48 | 787 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW), |
7198e6b0 RC |
788 | }; |
789 | ||
c8afe684 RC |
790 | static const struct vm_operations_struct vm_ops = { |
791 | .fault = msm_gem_fault, | |
792 | .open = drm_gem_vm_open, | |
793 | .close = drm_gem_vm_close, | |
794 | }; | |
795 | ||
796 | static const struct file_operations fops = { | |
797 | .owner = THIS_MODULE, | |
798 | .open = drm_open, | |
799 | .release = drm_release, | |
800 | .unlocked_ioctl = drm_ioctl, | |
c8afe684 | 801 | .compat_ioctl = drm_compat_ioctl, |
c8afe684 RC |
802 | .poll = drm_poll, |
803 | .read = drm_read, | |
804 | .llseek = no_llseek, | |
805 | .mmap = msm_gem_mmap, | |
806 | }; | |
807 | ||
808 | static struct drm_driver msm_driver = { | |
05b84911 RC |
809 | .driver_features = DRIVER_HAVE_IRQ | |
810 | DRIVER_GEM | | |
811 | DRIVER_PRIME | | |
b4b15c86 | 812 | DRIVER_RENDER | |
a5436e1d | 813 | DRIVER_ATOMIC | |
05b84911 | 814 | DRIVER_MODESET, |
7198e6b0 | 815 | .open = msm_open, |
94df145c | 816 | .postclose = msm_postclose, |
c8afe684 RC |
817 | .lastclose = msm_lastclose, |
818 | .irq_handler = msm_irq, | |
819 | .irq_preinstall = msm_irq_preinstall, | |
820 | .irq_postinstall = msm_irq_postinstall, | |
821 | .irq_uninstall = msm_irq_uninstall, | |
c8afe684 RC |
822 | .enable_vblank = msm_enable_vblank, |
823 | .disable_vblank = msm_disable_vblank, | |
824 | .gem_free_object = msm_gem_free_object, | |
825 | .gem_vm_ops = &vm_ops, | |
826 | .dumb_create = msm_gem_dumb_create, | |
827 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 828 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
829 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
830 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
831 | .gem_prime_export = drm_gem_prime_export, | |
832 | .gem_prime_import = drm_gem_prime_import, | |
43523eba | 833 | .gem_prime_res_obj = msm_gem_prime_res_obj, |
05b84911 RC |
834 | .gem_prime_pin = msm_gem_prime_pin, |
835 | .gem_prime_unpin = msm_gem_prime_unpin, | |
836 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
837 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
838 | .gem_prime_vmap = msm_gem_prime_vmap, | |
839 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
77a147e7 | 840 | .gem_prime_mmap = msm_gem_prime_mmap, |
c8afe684 RC |
841 | #ifdef CONFIG_DEBUG_FS |
842 | .debugfs_init = msm_debugfs_init, | |
c8afe684 | 843 | #endif |
7198e6b0 RC |
844 | .ioctls = msm_ioctls, |
845 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
846 | .fops = &fops, |
847 | .name = "msm", | |
848 | .desc = "MSM Snapdragon DRM", | |
849 | .date = "20130625", | |
a8d854c1 RC |
850 | .major = MSM_VERSION_MAJOR, |
851 | .minor = MSM_VERSION_MINOR, | |
852 | .patchlevel = MSM_VERSION_PATCHLEVEL, | |
c8afe684 RC |
853 | }; |
854 | ||
855 | #ifdef CONFIG_PM_SLEEP | |
856 | static int msm_pm_suspend(struct device *dev) | |
857 | { | |
858 | struct drm_device *ddev = dev_get_drvdata(dev); | |
859 | ||
860 | drm_kms_helper_poll_disable(ddev); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
865 | static int msm_pm_resume(struct device *dev) | |
866 | { | |
867 | struct drm_device *ddev = dev_get_drvdata(dev); | |
868 | ||
869 | drm_kms_helper_poll_enable(ddev); | |
870 | ||
871 | return 0; | |
872 | } | |
873 | #endif | |
874 | ||
875 | static const struct dev_pm_ops msm_pm_ops = { | |
876 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
877 | }; | |
878 | ||
060530f1 RC |
879 | /* |
880 | * Componentized driver support: | |
881 | */ | |
882 | ||
e9fbdaf2 AT |
883 | /* |
884 | * NOTE: duplication of the same code as exynos or imx (or probably any other). | |
885 | * so probably some room for some helpers | |
060530f1 RC |
886 | */ |
887 | static int compare_of(struct device *dev, void *data) | |
888 | { | |
889 | return dev->of_node == data; | |
890 | } | |
41e69778 | 891 | |
812070eb AT |
892 | /* |
893 | * Identify what components need to be added by parsing what remote-endpoints | |
894 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there | |
895 | * is no external component that we need to add since LVDS is within MDP4 | |
896 | * itself. | |
897 | */ | |
898 | static int add_components_mdp(struct device *mdp_dev, | |
899 | struct component_match **matchptr) | |
900 | { | |
901 | struct device_node *np = mdp_dev->of_node; | |
902 | struct device_node *ep_node; | |
54011e26 AT |
903 | struct device *master_dev; |
904 | ||
905 | /* | |
906 | * on MDP4 based platforms, the MDP platform device is the component | |
907 | * master that adds other display interface components to itself. | |
908 | * | |
909 | * on MDP5 based platforms, the MDSS platform device is the component | |
910 | * master that adds MDP5 and other display interface components to | |
911 | * itself. | |
912 | */ | |
913 | if (of_device_is_compatible(np, "qcom,mdp4")) | |
914 | master_dev = mdp_dev; | |
915 | else | |
916 | master_dev = mdp_dev->parent; | |
812070eb AT |
917 | |
918 | for_each_endpoint_of_node(np, ep_node) { | |
919 | struct device_node *intf; | |
920 | struct of_endpoint ep; | |
921 | int ret; | |
922 | ||
923 | ret = of_graph_parse_endpoint(ep_node, &ep); | |
924 | if (ret) { | |
925 | dev_err(mdp_dev, "unable to parse port endpoint\n"); | |
926 | of_node_put(ep_node); | |
927 | return ret; | |
928 | } | |
929 | ||
930 | /* | |
931 | * The LCDC/LVDS port on MDP4 is a speacial case where the | |
932 | * remote-endpoint isn't a component that we need to add | |
933 | */ | |
934 | if (of_device_is_compatible(np, "qcom,mdp4") && | |
d8dd8052 | 935 | ep.port == 0) |
812070eb | 936 | continue; |
812070eb AT |
937 | |
938 | /* | |
939 | * It's okay if some of the ports don't have a remote endpoint | |
940 | * specified. It just means that the port isn't connected to | |
941 | * any external interface. | |
942 | */ | |
943 | intf = of_graph_get_remote_port_parent(ep_node); | |
d8dd8052 | 944 | if (!intf) |
812070eb | 945 | continue; |
812070eb | 946 | |
97ac0e47 RK |
947 | drm_of_component_match_add(master_dev, matchptr, compare_of, |
948 | intf); | |
812070eb | 949 | of_node_put(intf); |
812070eb AT |
950 | } |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
54011e26 AT |
955 | static int compare_name_mdp(struct device *dev, void *data) |
956 | { | |
957 | return (strstr(dev_name(dev), "mdp") != NULL); | |
958 | } | |
959 | ||
7d526fcf AT |
960 | static int add_display_components(struct device *dev, |
961 | struct component_match **matchptr) | |
962 | { | |
54011e26 AT |
963 | struct device *mdp_dev; |
964 | int ret; | |
965 | ||
966 | /* | |
967 | * MDP5 based devices don't have a flat hierarchy. There is a top level | |
968 | * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the | |
969 | * children devices, find the MDP5 node, and then add the interfaces | |
970 | * to our components list. | |
971 | */ | |
972 | if (of_device_is_compatible(dev->of_node, "qcom,mdss")) { | |
973 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); | |
974 | if (ret) { | |
975 | dev_err(dev, "failed to populate children devices\n"); | |
976 | return ret; | |
977 | } | |
978 | ||
979 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); | |
980 | if (!mdp_dev) { | |
981 | dev_err(dev, "failed to find MDSS MDP node\n"); | |
982 | of_platform_depopulate(dev); | |
983 | return -ENODEV; | |
984 | } | |
985 | ||
986 | put_device(mdp_dev); | |
987 | ||
988 | /* add the MDP component itself */ | |
97ac0e47 RK |
989 | drm_of_component_match_add(dev, matchptr, compare_of, |
990 | mdp_dev->of_node); | |
54011e26 AT |
991 | } else { |
992 | /* MDP4 */ | |
993 | mdp_dev = dev; | |
994 | } | |
995 | ||
996 | ret = add_components_mdp(mdp_dev, matchptr); | |
997 | if (ret) | |
998 | of_platform_depopulate(dev); | |
999 | ||
1000 | return ret; | |
7d526fcf AT |
1001 | } |
1002 | ||
dc3ea265 AT |
1003 | /* |
1004 | * We don't know what's the best binding to link the gpu with the drm device. | |
1005 | * Fow now, we just hunt for all the possible gpus that we support, and add them | |
1006 | * as components. | |
1007 | */ | |
1008 | static const struct of_device_id msm_gpu_match[] = { | |
1db7afa4 | 1009 | { .compatible = "qcom,adreno" }, |
dc3ea265 AT |
1010 | { .compatible = "qcom,adreno-3xx" }, |
1011 | { .compatible = "qcom,kgsl-3d0" }, | |
1012 | { }, | |
1013 | }; | |
1014 | ||
7d526fcf AT |
1015 | static int add_gpu_components(struct device *dev, |
1016 | struct component_match **matchptr) | |
1017 | { | |
dc3ea265 AT |
1018 | struct device_node *np; |
1019 | ||
1020 | np = of_find_matching_node(NULL, msm_gpu_match); | |
1021 | if (!np) | |
1022 | return 0; | |
1023 | ||
97ac0e47 | 1024 | drm_of_component_match_add(dev, matchptr, compare_of, np); |
dc3ea265 AT |
1025 | |
1026 | of_node_put(np); | |
1027 | ||
1028 | return 0; | |
7d526fcf AT |
1029 | } |
1030 | ||
84448288 RK |
1031 | static int msm_drm_bind(struct device *dev) |
1032 | { | |
2b669875 | 1033 | return msm_drm_init(dev, &msm_driver); |
84448288 RK |
1034 | } |
1035 | ||
1036 | static void msm_drm_unbind(struct device *dev) | |
1037 | { | |
2b669875 | 1038 | msm_drm_uninit(dev); |
84448288 RK |
1039 | } |
1040 | ||
1041 | static const struct component_master_ops msm_drm_ops = { | |
1042 | .bind = msm_drm_bind, | |
1043 | .unbind = msm_drm_unbind, | |
1044 | }; | |
1045 | ||
1046 | /* | |
1047 | * Platform driver: | |
1048 | */ | |
060530f1 | 1049 | |
84448288 | 1050 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 1051 | { |
84448288 | 1052 | struct component_match *match = NULL; |
7d526fcf AT |
1053 | int ret; |
1054 | ||
1055 | ret = add_display_components(&pdev->dev, &match); | |
1056 | if (ret) | |
1057 | return ret; | |
e9fbdaf2 | 1058 | |
7d526fcf AT |
1059 | ret = add_gpu_components(&pdev->dev, &match); |
1060 | if (ret) | |
1061 | return ret; | |
060530f1 | 1062 | |
c83ea576 RC |
1063 | /* on all devices that I am aware of, iommu's which can map |
1064 | * any address the cpu can see are used: | |
1065 | */ | |
1066 | ret = dma_set_mask_and_coherent(&pdev->dev, ~0); | |
1067 | if (ret) | |
1068 | return ret; | |
1069 | ||
84448288 | 1070 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
1071 | } |
1072 | ||
1073 | static int msm_pdev_remove(struct platform_device *pdev) | |
1074 | { | |
060530f1 | 1075 | component_master_del(&pdev->dev, &msm_drm_ops); |
54011e26 | 1076 | of_platform_depopulate(&pdev->dev); |
c8afe684 RC |
1077 | |
1078 | return 0; | |
1079 | } | |
1080 | ||
06c0dd96 | 1081 | static const struct of_device_id dt_match[] = { |
96a611b5 AT |
1082 | { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */ |
1083 | { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */ | |
06c0dd96 RC |
1084 | {} |
1085 | }; | |
1086 | MODULE_DEVICE_TABLE(of, dt_match); | |
1087 | ||
c8afe684 RC |
1088 | static struct platform_driver msm_platform_driver = { |
1089 | .probe = msm_pdev_probe, | |
1090 | .remove = msm_pdev_remove, | |
1091 | .driver = { | |
c8afe684 | 1092 | .name = "msm", |
06c0dd96 | 1093 | .of_match_table = dt_match, |
c8afe684 RC |
1094 | .pm = &msm_pm_ops, |
1095 | }, | |
c8afe684 RC |
1096 | }; |
1097 | ||
1098 | static int __init msm_drm_register(void) | |
1099 | { | |
1100 | DBG("init"); | |
1dd0a0b1 | 1101 | msm_mdp_register(); |
d5af49c9 | 1102 | msm_dsi_register(); |
00453981 | 1103 | msm_edp_register(); |
fcda50c8 | 1104 | msm_hdmi_register(); |
bfd28b13 | 1105 | adreno_register(); |
c8afe684 RC |
1106 | return platform_driver_register(&msm_platform_driver); |
1107 | } | |
1108 | ||
1109 | static void __exit msm_drm_unregister(void) | |
1110 | { | |
1111 | DBG("fini"); | |
1112 | platform_driver_unregister(&msm_platform_driver); | |
fcda50c8 | 1113 | msm_hdmi_unregister(); |
bfd28b13 | 1114 | adreno_unregister(); |
00453981 | 1115 | msm_edp_unregister(); |
d5af49c9 | 1116 | msm_dsi_unregister(); |
1dd0a0b1 | 1117 | msm_mdp_unregister(); |
c8afe684 RC |
1118 | } |
1119 | ||
1120 | module_init(msm_drm_register); | |
1121 | module_exit(msm_drm_unregister); | |
1122 | ||
1123 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1124 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1125 | MODULE_LICENSE("GPL"); |