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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_drv.h" | |
7198e6b0 | 19 | #include "msm_gpu.h" |
dd2da6e3 | 20 | #include "msm_kms.h" |
c8afe684 | 21 | |
c8afe684 RC |
22 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
23 | { | |
24 | struct msm_drm_private *priv = dev->dev_private; | |
25 | if (priv->fbdev) | |
26 | drm_fb_helper_hotplug_event(priv->fbdev); | |
27 | } | |
28 | ||
29 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
30 | .fb_create = msm_framebuffer_create, | |
31 | .output_poll_changed = msm_fb_output_poll_changed, | |
32 | }; | |
33 | ||
871d812a | 34 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
c8afe684 RC |
35 | { |
36 | struct msm_drm_private *priv = dev->dev_private; | |
871d812a | 37 | int idx = priv->num_mmus++; |
c8afe684 | 38 | |
871d812a | 39 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
c8afe684 RC |
40 | return -EINVAL; |
41 | ||
871d812a | 42 | priv->mmus[idx] = mmu; |
c8afe684 RC |
43 | |
44 | return idx; | |
45 | } | |
46 | ||
c8afe684 RC |
47 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
48 | static bool reglog = false; | |
49 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); | |
50 | module_param(reglog, bool, 0600); | |
51 | #else | |
52 | #define reglog 0 | |
53 | #endif | |
54 | ||
871d812a RC |
55 | static char *vram; |
56 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU"); | |
57 | module_param(vram, charp, 0); | |
58 | ||
060530f1 RC |
59 | /* |
60 | * Util/helpers: | |
61 | */ | |
62 | ||
c8afe684 RC |
63 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
64 | const char *dbgname) | |
65 | { | |
66 | struct resource *res; | |
67 | unsigned long size; | |
68 | void __iomem *ptr; | |
69 | ||
70 | if (name) | |
71 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
72 | else | |
73 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
74 | ||
75 | if (!res) { | |
76 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); | |
77 | return ERR_PTR(-EINVAL); | |
78 | } | |
79 | ||
80 | size = resource_size(res); | |
81 | ||
82 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); | |
83 | if (!ptr) { | |
84 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); | |
85 | return ERR_PTR(-ENOMEM); | |
86 | } | |
87 | ||
88 | if (reglog) | |
89 | printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size); | |
90 | ||
91 | return ptr; | |
92 | } | |
93 | ||
94 | void msm_writel(u32 data, void __iomem *addr) | |
95 | { | |
96 | if (reglog) | |
97 | printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data); | |
98 | writel(data, addr); | |
99 | } | |
100 | ||
101 | u32 msm_readl(const void __iomem *addr) | |
102 | { | |
103 | u32 val = readl(addr); | |
104 | if (reglog) | |
105 | printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val); | |
106 | return val; | |
107 | } | |
108 | ||
109 | /* | |
110 | * DRM operations: | |
111 | */ | |
112 | ||
113 | static int msm_unload(struct drm_device *dev) | |
114 | { | |
115 | struct msm_drm_private *priv = dev->dev_private; | |
116 | struct msm_kms *kms = priv->kms; | |
7198e6b0 | 117 | struct msm_gpu *gpu = priv->gpu; |
c8afe684 RC |
118 | |
119 | drm_kms_helper_poll_fini(dev); | |
120 | drm_mode_config_cleanup(dev); | |
121 | drm_vblank_cleanup(dev); | |
122 | ||
123 | pm_runtime_get_sync(dev->dev); | |
124 | drm_irq_uninstall(dev); | |
125 | pm_runtime_put_sync(dev->dev); | |
126 | ||
127 | flush_workqueue(priv->wq); | |
128 | destroy_workqueue(priv->wq); | |
129 | ||
130 | if (kms) { | |
131 | pm_runtime_disable(dev->dev); | |
132 | kms->funcs->destroy(kms); | |
133 | } | |
134 | ||
7198e6b0 RC |
135 | if (gpu) { |
136 | mutex_lock(&dev->struct_mutex); | |
137 | gpu->funcs->pm_suspend(gpu); | |
138 | gpu->funcs->destroy(gpu); | |
139 | mutex_unlock(&dev->struct_mutex); | |
140 | } | |
c8afe684 | 141 | |
871d812a RC |
142 | if (priv->vram.paddr) { |
143 | DEFINE_DMA_ATTRS(attrs); | |
144 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
145 | drm_mm_takedown(&priv->vram.mm); | |
146 | dma_free_attrs(dev->dev, priv->vram.size, NULL, | |
147 | priv->vram.paddr, &attrs); | |
148 | } | |
149 | ||
060530f1 RC |
150 | component_unbind_all(dev->dev, dev); |
151 | ||
c8afe684 RC |
152 | dev->dev_private = NULL; |
153 | ||
154 | kfree(priv); | |
155 | ||
156 | return 0; | |
157 | } | |
158 | ||
06c0dd96 RC |
159 | static int get_mdp_ver(struct platform_device *pdev) |
160 | { | |
161 | #ifdef CONFIG_OF | |
370a4d8a | 162 | static const struct of_device_id match_types[] = { { |
06c0dd96 RC |
163 | .compatible = "qcom,mdss_mdp", |
164 | .data = (void *)5, | |
165 | }, { | |
166 | /* end node */ | |
167 | } }; | |
168 | struct device *dev = &pdev->dev; | |
169 | const struct of_device_id *match; | |
170 | match = of_match_node(match_types, dev->of_node); | |
171 | if (match) | |
172 | return (int)match->data; | |
173 | #endif | |
174 | return 4; | |
175 | } | |
176 | ||
c8afe684 RC |
177 | static int msm_load(struct drm_device *dev, unsigned long flags) |
178 | { | |
179 | struct platform_device *pdev = dev->platformdev; | |
180 | struct msm_drm_private *priv; | |
181 | struct msm_kms *kms; | |
182 | int ret; | |
183 | ||
184 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
185 | if (!priv) { | |
186 | dev_err(dev->dev, "failed to allocate private data\n"); | |
187 | return -ENOMEM; | |
188 | } | |
189 | ||
190 | dev->dev_private = priv; | |
191 | ||
192 | priv->wq = alloc_ordered_workqueue("msm", 0); | |
7198e6b0 | 193 | init_waitqueue_head(&priv->fence_event); |
c8afe684 RC |
194 | |
195 | INIT_LIST_HEAD(&priv->inactive_list); | |
edd4fc63 | 196 | INIT_LIST_HEAD(&priv->fence_cbs); |
c8afe684 RC |
197 | |
198 | drm_mode_config_init(dev); | |
199 | ||
871d812a RC |
200 | /* if we have no IOMMU, then we need to use carveout allocator. |
201 | * Grab the entire CMA chunk carved out in early startup in | |
202 | * mach-msm: | |
203 | */ | |
204 | if (!iommu_present(&platform_bus_type)) { | |
205 | DEFINE_DMA_ATTRS(attrs); | |
206 | unsigned long size; | |
207 | void *p; | |
208 | ||
209 | DBG("using %s VRAM carveout", vram); | |
210 | size = memparse(vram, NULL); | |
211 | priv->vram.size = size; | |
212 | ||
213 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); | |
214 | ||
215 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | |
216 | dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs); | |
217 | ||
218 | /* note that for no-kernel-mapping, the vaddr returned | |
219 | * is bogus, but non-null if allocation succeeded: | |
220 | */ | |
221 | p = dma_alloc_attrs(dev->dev, size, | |
543d3011 | 222 | &priv->vram.paddr, GFP_KERNEL, &attrs); |
871d812a RC |
223 | if (!p) { |
224 | dev_err(dev->dev, "failed to allocate VRAM\n"); | |
225 | priv->vram.paddr = 0; | |
226 | ret = -ENOMEM; | |
227 | goto fail; | |
228 | } | |
229 | ||
230 | dev_info(dev->dev, "VRAM: %08x->%08x\n", | |
231 | (uint32_t)priv->vram.paddr, | |
232 | (uint32_t)(priv->vram.paddr + size)); | |
233 | } | |
234 | ||
060530f1 RC |
235 | platform_set_drvdata(pdev, dev); |
236 | ||
237 | /* Bind all our sub-components: */ | |
238 | ret = component_bind_all(dev->dev, dev); | |
239 | if (ret) | |
240 | return ret; | |
241 | ||
06c0dd96 RC |
242 | switch (get_mdp_ver(pdev)) { |
243 | case 4: | |
244 | kms = mdp4_kms_init(dev); | |
245 | break; | |
246 | case 5: | |
247 | kms = mdp5_kms_init(dev); | |
248 | break; | |
249 | default: | |
250 | kms = ERR_PTR(-ENODEV); | |
251 | break; | |
252 | } | |
253 | ||
c8afe684 RC |
254 | if (IS_ERR(kms)) { |
255 | /* | |
256 | * NOTE: once we have GPU support, having no kms should not | |
257 | * be considered fatal.. ideally we would still support gpu | |
258 | * and (for example) use dmabuf/prime to share buffers with | |
259 | * imx drm driver on iMX5 | |
260 | */ | |
261 | dev_err(dev->dev, "failed to load kms\n"); | |
e4826a94 | 262 | ret = PTR_ERR(kms); |
c8afe684 RC |
263 | goto fail; |
264 | } | |
265 | ||
266 | priv->kms = kms; | |
267 | ||
268 | if (kms) { | |
269 | pm_runtime_enable(dev->dev); | |
270 | ret = kms->funcs->hw_init(kms); | |
271 | if (ret) { | |
272 | dev_err(dev->dev, "kms hw init failed: %d\n", ret); | |
273 | goto fail; | |
274 | } | |
275 | } | |
276 | ||
277 | dev->mode_config.min_width = 0; | |
278 | dev->mode_config.min_height = 0; | |
279 | dev->mode_config.max_width = 2048; | |
280 | dev->mode_config.max_height = 2048; | |
281 | dev->mode_config.funcs = &mode_config_funcs; | |
282 | ||
d65bd0e4 | 283 | ret = drm_vblank_init(dev, priv->num_crtcs); |
c8afe684 RC |
284 | if (ret < 0) { |
285 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
286 | goto fail; | |
287 | } | |
288 | ||
289 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 290 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
c8afe684 RC |
291 | pm_runtime_put_sync(dev->dev); |
292 | if (ret < 0) { | |
293 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
294 | goto fail; | |
295 | } | |
296 | ||
c8afe684 RC |
297 | #ifdef CONFIG_DRM_MSM_FBDEV |
298 | priv->fbdev = msm_fbdev_init(dev); | |
299 | #endif | |
300 | ||
a7d3c950 RC |
301 | ret = msm_debugfs_late_init(dev); |
302 | if (ret) | |
303 | goto fail; | |
304 | ||
c8afe684 RC |
305 | drm_kms_helper_poll_init(dev); |
306 | ||
307 | return 0; | |
308 | ||
309 | fail: | |
310 | msm_unload(dev); | |
311 | return ret; | |
312 | } | |
313 | ||
7198e6b0 RC |
314 | static void load_gpu(struct drm_device *dev) |
315 | { | |
a1ad3523 | 316 | static DEFINE_MUTEX(init_lock); |
7198e6b0 RC |
317 | struct msm_drm_private *priv = dev->dev_private; |
318 | struct msm_gpu *gpu; | |
319 | ||
a1ad3523 RC |
320 | mutex_lock(&init_lock); |
321 | ||
7198e6b0 | 322 | if (priv->gpu) |
a1ad3523 | 323 | goto out; |
7198e6b0 | 324 | |
7198e6b0 RC |
325 | gpu = a3xx_gpu_init(dev); |
326 | if (IS_ERR(gpu)) { | |
327 | dev_warn(dev->dev, "failed to load a3xx gpu\n"); | |
328 | gpu = NULL; | |
329 | /* not fatal */ | |
330 | } | |
7198e6b0 RC |
331 | |
332 | if (gpu) { | |
333 | int ret; | |
a1ad3523 | 334 | mutex_lock(&dev->struct_mutex); |
7198e6b0 | 335 | gpu->funcs->pm_resume(gpu); |
a1ad3523 | 336 | mutex_unlock(&dev->struct_mutex); |
7198e6b0 RC |
337 | ret = gpu->funcs->hw_init(gpu); |
338 | if (ret) { | |
339 | dev_err(dev->dev, "gpu hw init failed: %d\n", ret); | |
340 | gpu->funcs->destroy(gpu); | |
341 | gpu = NULL; | |
37d77c3a RC |
342 | } else { |
343 | /* give inactive pm a chance to kick in: */ | |
344 | msm_gpu_retire(gpu); | |
7198e6b0 RC |
345 | } |
346 | } | |
347 | ||
348 | priv->gpu = gpu; | |
37d77c3a | 349 | |
a1ad3523 RC |
350 | out: |
351 | mutex_unlock(&init_lock); | |
7198e6b0 RC |
352 | } |
353 | ||
354 | static int msm_open(struct drm_device *dev, struct drm_file *file) | |
355 | { | |
356 | struct msm_file_private *ctx; | |
357 | ||
358 | /* For now, load gpu on open.. to avoid the requirement of having | |
359 | * firmware in the initrd. | |
360 | */ | |
361 | load_gpu(dev); | |
362 | ||
363 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
364 | if (!ctx) | |
365 | return -ENOMEM; | |
366 | ||
367 | file->driver_priv = ctx; | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
c8afe684 RC |
372 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
373 | { | |
374 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 | 375 | struct msm_file_private *ctx = file->driver_priv; |
c8afe684 | 376 | struct msm_kms *kms = priv->kms; |
7198e6b0 | 377 | |
c8afe684 RC |
378 | if (kms) |
379 | kms->funcs->preclose(kms, file); | |
7198e6b0 RC |
380 | |
381 | mutex_lock(&dev->struct_mutex); | |
382 | if (ctx == priv->lastctx) | |
383 | priv->lastctx = NULL; | |
384 | mutex_unlock(&dev->struct_mutex); | |
385 | ||
386 | kfree(ctx); | |
c8afe684 RC |
387 | } |
388 | ||
389 | static void msm_lastclose(struct drm_device *dev) | |
390 | { | |
391 | struct msm_drm_private *priv = dev->dev_private; | |
5ea1f752 RC |
392 | if (priv->fbdev) |
393 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); | |
c8afe684 RC |
394 | } |
395 | ||
e9f0d76f | 396 | static irqreturn_t msm_irq(int irq, void *arg) |
c8afe684 RC |
397 | { |
398 | struct drm_device *dev = arg; | |
399 | struct msm_drm_private *priv = dev->dev_private; | |
400 | struct msm_kms *kms = priv->kms; | |
401 | BUG_ON(!kms); | |
402 | return kms->funcs->irq(kms); | |
403 | } | |
404 | ||
405 | static void msm_irq_preinstall(struct drm_device *dev) | |
406 | { | |
407 | struct msm_drm_private *priv = dev->dev_private; | |
408 | struct msm_kms *kms = priv->kms; | |
409 | BUG_ON(!kms); | |
410 | kms->funcs->irq_preinstall(kms); | |
411 | } | |
412 | ||
413 | static int msm_irq_postinstall(struct drm_device *dev) | |
414 | { | |
415 | struct msm_drm_private *priv = dev->dev_private; | |
416 | struct msm_kms *kms = priv->kms; | |
417 | BUG_ON(!kms); | |
418 | return kms->funcs->irq_postinstall(kms); | |
419 | } | |
420 | ||
421 | static void msm_irq_uninstall(struct drm_device *dev) | |
422 | { | |
423 | struct msm_drm_private *priv = dev->dev_private; | |
424 | struct msm_kms *kms = priv->kms; | |
425 | BUG_ON(!kms); | |
426 | kms->funcs->irq_uninstall(kms); | |
427 | } | |
428 | ||
429 | static int msm_enable_vblank(struct drm_device *dev, int crtc_id) | |
430 | { | |
431 | struct msm_drm_private *priv = dev->dev_private; | |
432 | struct msm_kms *kms = priv->kms; | |
433 | if (!kms) | |
434 | return -ENXIO; | |
435 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
436 | return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]); | |
437 | } | |
438 | ||
439 | static void msm_disable_vblank(struct drm_device *dev, int crtc_id) | |
440 | { | |
441 | struct msm_drm_private *priv = dev->dev_private; | |
442 | struct msm_kms *kms = priv->kms; | |
443 | if (!kms) | |
444 | return; | |
445 | DBG("dev=%p, crtc=%d", dev, crtc_id); | |
446 | kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]); | |
447 | } | |
448 | ||
449 | /* | |
450 | * DRM debugfs: | |
451 | */ | |
452 | ||
453 | #ifdef CONFIG_DEBUG_FS | |
7198e6b0 RC |
454 | static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) |
455 | { | |
456 | struct msm_drm_private *priv = dev->dev_private; | |
457 | struct msm_gpu *gpu = priv->gpu; | |
458 | ||
459 | if (gpu) { | |
460 | seq_printf(m, "%s Status:\n", gpu->name); | |
461 | gpu->funcs->show(gpu, m); | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
c8afe684 RC |
467 | static int msm_gem_show(struct drm_device *dev, struct seq_file *m) |
468 | { | |
469 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
470 | struct msm_gpu *gpu = priv->gpu; |
471 | ||
472 | if (gpu) { | |
473 | seq_printf(m, "Active Objects (%s):\n", gpu->name); | |
474 | msm_gem_describe_objects(&gpu->active_list, m); | |
475 | } | |
c8afe684 | 476 | |
7198e6b0 | 477 | seq_printf(m, "Inactive Objects:\n"); |
c8afe684 RC |
478 | msm_gem_describe_objects(&priv->inactive_list, m); |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int msm_mm_show(struct drm_device *dev, struct seq_file *m) | |
484 | { | |
b04a5906 | 485 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
c8afe684 RC |
486 | } |
487 | ||
488 | static int msm_fb_show(struct drm_device *dev, struct seq_file *m) | |
489 | { | |
490 | struct msm_drm_private *priv = dev->dev_private; | |
491 | struct drm_framebuffer *fb, *fbdev_fb = NULL; | |
492 | ||
493 | if (priv->fbdev) { | |
494 | seq_printf(m, "fbcon "); | |
495 | fbdev_fb = priv->fbdev->fb; | |
496 | msm_framebuffer_describe(fbdev_fb, m); | |
497 | } | |
498 | ||
499 | mutex_lock(&dev->mode_config.fb_lock); | |
500 | list_for_each_entry(fb, &dev->mode_config.fb_list, head) { | |
501 | if (fb == fbdev_fb) | |
502 | continue; | |
503 | ||
504 | seq_printf(m, "user "); | |
505 | msm_framebuffer_describe(fb, m); | |
506 | } | |
507 | mutex_unlock(&dev->mode_config.fb_lock); | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int show_locked(struct seq_file *m, void *arg) | |
513 | { | |
514 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
515 | struct drm_device *dev = node->minor->dev; | |
516 | int (*show)(struct drm_device *dev, struct seq_file *m) = | |
517 | node->info_ent->data; | |
518 | int ret; | |
519 | ||
520 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
521 | if (ret) | |
522 | return ret; | |
523 | ||
524 | ret = show(dev, m); | |
525 | ||
526 | mutex_unlock(&dev->struct_mutex); | |
527 | ||
528 | return ret; | |
529 | } | |
530 | ||
531 | static struct drm_info_list msm_debugfs_list[] = { | |
7198e6b0 | 532 | {"gpu", show_locked, 0, msm_gpu_show}, |
c8afe684 RC |
533 | {"gem", show_locked, 0, msm_gem_show}, |
534 | { "mm", show_locked, 0, msm_mm_show }, | |
535 | { "fb", show_locked, 0, msm_fb_show }, | |
536 | }; | |
537 | ||
a7d3c950 RC |
538 | static int late_init_minor(struct drm_minor *minor) |
539 | { | |
540 | int ret; | |
541 | ||
542 | if (!minor) | |
543 | return 0; | |
544 | ||
545 | ret = msm_rd_debugfs_init(minor); | |
546 | if (ret) { | |
547 | dev_err(minor->dev->dev, "could not install rd debugfs\n"); | |
548 | return ret; | |
549 | } | |
550 | ||
70c70f09 RC |
551 | ret = msm_perf_debugfs_init(minor); |
552 | if (ret) { | |
553 | dev_err(minor->dev->dev, "could not install perf debugfs\n"); | |
554 | return ret; | |
555 | } | |
556 | ||
a7d3c950 RC |
557 | return 0; |
558 | } | |
559 | ||
560 | int msm_debugfs_late_init(struct drm_device *dev) | |
561 | { | |
562 | int ret; | |
563 | ret = late_init_minor(dev->primary); | |
564 | if (ret) | |
565 | return ret; | |
566 | ret = late_init_minor(dev->render); | |
567 | if (ret) | |
568 | return ret; | |
569 | ret = late_init_minor(dev->control); | |
570 | return ret; | |
571 | } | |
572 | ||
c8afe684 RC |
573 | static int msm_debugfs_init(struct drm_minor *minor) |
574 | { | |
575 | struct drm_device *dev = minor->dev; | |
576 | int ret; | |
577 | ||
578 | ret = drm_debugfs_create_files(msm_debugfs_list, | |
579 | ARRAY_SIZE(msm_debugfs_list), | |
580 | minor->debugfs_root, minor); | |
581 | ||
582 | if (ret) { | |
583 | dev_err(dev->dev, "could not install msm_debugfs_list\n"); | |
584 | return ret; | |
585 | } | |
586 | ||
a7d3c950 | 587 | return 0; |
c8afe684 RC |
588 | } |
589 | ||
590 | static void msm_debugfs_cleanup(struct drm_minor *minor) | |
591 | { | |
592 | drm_debugfs_remove_files(msm_debugfs_list, | |
593 | ARRAY_SIZE(msm_debugfs_list), minor); | |
a7d3c950 RC |
594 | if (!minor->dev->dev_private) |
595 | return; | |
596 | msm_rd_debugfs_cleanup(minor); | |
70c70f09 | 597 | msm_perf_debugfs_cleanup(minor); |
c8afe684 RC |
598 | } |
599 | #endif | |
600 | ||
7198e6b0 RC |
601 | /* |
602 | * Fences: | |
603 | */ | |
604 | ||
605 | int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, | |
606 | struct timespec *timeout) | |
607 | { | |
608 | struct msm_drm_private *priv = dev->dev_private; | |
7198e6b0 RC |
609 | int ret; |
610 | ||
f816f272 RC |
611 | if (!priv->gpu) |
612 | return 0; | |
613 | ||
614 | if (fence > priv->gpu->submitted_fence) { | |
615 | DRM_ERROR("waiting on invalid fence: %u (of %u)\n", | |
616 | fence, priv->gpu->submitted_fence); | |
617 | return -EINVAL; | |
618 | } | |
619 | ||
620 | if (!timeout) { | |
621 | /* no-wait: */ | |
622 | ret = fence_completed(dev, fence) ? 0 : -EBUSY; | |
623 | } else { | |
624 | unsigned long timeout_jiffies = timespec_to_jiffies(timeout); | |
625 | unsigned long start_jiffies = jiffies; | |
626 | unsigned long remaining_jiffies; | |
627 | ||
628 | if (time_after(start_jiffies, timeout_jiffies)) | |
629 | remaining_jiffies = 0; | |
630 | else | |
631 | remaining_jiffies = timeout_jiffies - start_jiffies; | |
632 | ||
633 | ret = wait_event_interruptible_timeout(priv->fence_event, | |
634 | fence_completed(dev, fence), | |
635 | remaining_jiffies); | |
636 | ||
637 | if (ret == 0) { | |
638 | DBG("timeout waiting for fence: %u (completed: %u)", | |
639 | fence, priv->completed_fence); | |
640 | ret = -ETIMEDOUT; | |
641 | } else if (ret != -ERESTARTSYS) { | |
642 | ret = 0; | |
643 | } | |
7198e6b0 RC |
644 | } |
645 | ||
646 | return ret; | |
647 | } | |
648 | ||
edd4fc63 | 649 | /* called from workqueue */ |
7198e6b0 RC |
650 | void msm_update_fence(struct drm_device *dev, uint32_t fence) |
651 | { | |
652 | struct msm_drm_private *priv = dev->dev_private; | |
653 | ||
edd4fc63 RC |
654 | mutex_lock(&dev->struct_mutex); |
655 | priv->completed_fence = max(fence, priv->completed_fence); | |
656 | ||
657 | while (!list_empty(&priv->fence_cbs)) { | |
658 | struct msm_fence_cb *cb; | |
659 | ||
660 | cb = list_first_entry(&priv->fence_cbs, | |
661 | struct msm_fence_cb, work.entry); | |
662 | ||
663 | if (cb->fence > priv->completed_fence) | |
664 | break; | |
665 | ||
666 | list_del_init(&cb->work.entry); | |
667 | queue_work(priv->wq, &cb->work); | |
7198e6b0 | 668 | } |
edd4fc63 RC |
669 | |
670 | mutex_unlock(&dev->struct_mutex); | |
671 | ||
672 | wake_up_all(&priv->fence_event); | |
673 | } | |
674 | ||
675 | void __msm_fence_worker(struct work_struct *work) | |
676 | { | |
677 | struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work); | |
678 | cb->func(cb); | |
7198e6b0 RC |
679 | } |
680 | ||
681 | /* | |
682 | * DRM ioctls: | |
683 | */ | |
684 | ||
685 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, | |
686 | struct drm_file *file) | |
687 | { | |
688 | struct msm_drm_private *priv = dev->dev_private; | |
689 | struct drm_msm_param *args = data; | |
690 | struct msm_gpu *gpu; | |
691 | ||
692 | /* for now, we just have 3d pipe.. eventually this would need to | |
693 | * be more clever to dispatch to appropriate gpu module: | |
694 | */ | |
695 | if (args->pipe != MSM_PIPE_3D0) | |
696 | return -EINVAL; | |
697 | ||
698 | gpu = priv->gpu; | |
699 | ||
700 | if (!gpu) | |
701 | return -ENXIO; | |
702 | ||
703 | return gpu->funcs->get_param(gpu, args->param, &args->value); | |
704 | } | |
705 | ||
706 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, | |
707 | struct drm_file *file) | |
708 | { | |
709 | struct drm_msm_gem_new *args = data; | |
93ddb0d3 RC |
710 | |
711 | if (args->flags & ~MSM_BO_FLAGS) { | |
712 | DRM_ERROR("invalid flags: %08x\n", args->flags); | |
713 | return -EINVAL; | |
714 | } | |
715 | ||
7198e6b0 RC |
716 | return msm_gem_new_handle(dev, file, args->size, |
717 | args->flags, &args->handle); | |
718 | } | |
719 | ||
720 | #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec }) | |
721 | ||
722 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
723 | struct drm_file *file) | |
724 | { | |
725 | struct drm_msm_gem_cpu_prep *args = data; | |
726 | struct drm_gem_object *obj; | |
727 | int ret; | |
728 | ||
93ddb0d3 RC |
729 | if (args->op & ~MSM_PREP_FLAGS) { |
730 | DRM_ERROR("invalid op: %08x\n", args->op); | |
731 | return -EINVAL; | |
732 | } | |
733 | ||
7198e6b0 RC |
734 | obj = drm_gem_object_lookup(dev, file, args->handle); |
735 | if (!obj) | |
736 | return -ENOENT; | |
737 | ||
738 | ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout)); | |
739 | ||
740 | drm_gem_object_unreference_unlocked(obj); | |
741 | ||
742 | return ret; | |
743 | } | |
744 | ||
745 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
746 | struct drm_file *file) | |
747 | { | |
748 | struct drm_msm_gem_cpu_fini *args = data; | |
749 | struct drm_gem_object *obj; | |
750 | int ret; | |
751 | ||
752 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
753 | if (!obj) | |
754 | return -ENOENT; | |
755 | ||
756 | ret = msm_gem_cpu_fini(obj); | |
757 | ||
758 | drm_gem_object_unreference_unlocked(obj); | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
763 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, | |
764 | struct drm_file *file) | |
765 | { | |
766 | struct drm_msm_gem_info *args = data; | |
767 | struct drm_gem_object *obj; | |
768 | int ret = 0; | |
769 | ||
770 | if (args->pad) | |
771 | return -EINVAL; | |
772 | ||
773 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
774 | if (!obj) | |
775 | return -ENOENT; | |
776 | ||
777 | args->offset = msm_gem_mmap_offset(obj); | |
778 | ||
779 | drm_gem_object_unreference_unlocked(obj); | |
780 | ||
781 | return ret; | |
782 | } | |
783 | ||
784 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, | |
785 | struct drm_file *file) | |
786 | { | |
787 | struct drm_msm_wait_fence *args = data; | |
93ddb0d3 RC |
788 | |
789 | if (args->pad) { | |
790 | DRM_ERROR("invalid pad: %08x\n", args->pad); | |
791 | return -EINVAL; | |
792 | } | |
793 | ||
794 | return msm_wait_fence_interruptable(dev, args->fence, | |
795 | &TS(args->timeout)); | |
7198e6b0 RC |
796 | } |
797 | ||
798 | static const struct drm_ioctl_desc msm_ioctls[] = { | |
b4b15c86 RC |
799 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), |
800 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
801 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
802 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
803 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
804 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
805 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), | |
7198e6b0 RC |
806 | }; |
807 | ||
c8afe684 RC |
808 | static const struct vm_operations_struct vm_ops = { |
809 | .fault = msm_gem_fault, | |
810 | .open = drm_gem_vm_open, | |
811 | .close = drm_gem_vm_close, | |
812 | }; | |
813 | ||
814 | static const struct file_operations fops = { | |
815 | .owner = THIS_MODULE, | |
816 | .open = drm_open, | |
817 | .release = drm_release, | |
818 | .unlocked_ioctl = drm_ioctl, | |
819 | #ifdef CONFIG_COMPAT | |
820 | .compat_ioctl = drm_compat_ioctl, | |
821 | #endif | |
822 | .poll = drm_poll, | |
823 | .read = drm_read, | |
824 | .llseek = no_llseek, | |
825 | .mmap = msm_gem_mmap, | |
826 | }; | |
827 | ||
828 | static struct drm_driver msm_driver = { | |
05b84911 RC |
829 | .driver_features = DRIVER_HAVE_IRQ | |
830 | DRIVER_GEM | | |
831 | DRIVER_PRIME | | |
b4b15c86 | 832 | DRIVER_RENDER | |
05b84911 | 833 | DRIVER_MODESET, |
c8afe684 RC |
834 | .load = msm_load, |
835 | .unload = msm_unload, | |
7198e6b0 | 836 | .open = msm_open, |
c8afe684 RC |
837 | .preclose = msm_preclose, |
838 | .lastclose = msm_lastclose, | |
915b4d11 | 839 | .set_busid = drm_platform_set_busid, |
c8afe684 RC |
840 | .irq_handler = msm_irq, |
841 | .irq_preinstall = msm_irq_preinstall, | |
842 | .irq_postinstall = msm_irq_postinstall, | |
843 | .irq_uninstall = msm_irq_uninstall, | |
844 | .get_vblank_counter = drm_vblank_count, | |
845 | .enable_vblank = msm_enable_vblank, | |
846 | .disable_vblank = msm_disable_vblank, | |
847 | .gem_free_object = msm_gem_free_object, | |
848 | .gem_vm_ops = &vm_ops, | |
849 | .dumb_create = msm_gem_dumb_create, | |
850 | .dumb_map_offset = msm_gem_dumb_map_offset, | |
30600a90 | 851 | .dumb_destroy = drm_gem_dumb_destroy, |
05b84911 RC |
852 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
853 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
854 | .gem_prime_export = drm_gem_prime_export, | |
855 | .gem_prime_import = drm_gem_prime_import, | |
856 | .gem_prime_pin = msm_gem_prime_pin, | |
857 | .gem_prime_unpin = msm_gem_prime_unpin, | |
858 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, | |
859 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, | |
860 | .gem_prime_vmap = msm_gem_prime_vmap, | |
861 | .gem_prime_vunmap = msm_gem_prime_vunmap, | |
c8afe684 RC |
862 | #ifdef CONFIG_DEBUG_FS |
863 | .debugfs_init = msm_debugfs_init, | |
864 | .debugfs_cleanup = msm_debugfs_cleanup, | |
865 | #endif | |
7198e6b0 RC |
866 | .ioctls = msm_ioctls, |
867 | .num_ioctls = DRM_MSM_NUM_IOCTLS, | |
c8afe684 RC |
868 | .fops = &fops, |
869 | .name = "msm", | |
870 | .desc = "MSM Snapdragon DRM", | |
871 | .date = "20130625", | |
872 | .major = 1, | |
873 | .minor = 0, | |
874 | }; | |
875 | ||
876 | #ifdef CONFIG_PM_SLEEP | |
877 | static int msm_pm_suspend(struct device *dev) | |
878 | { | |
879 | struct drm_device *ddev = dev_get_drvdata(dev); | |
880 | ||
881 | drm_kms_helper_poll_disable(ddev); | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
886 | static int msm_pm_resume(struct device *dev) | |
887 | { | |
888 | struct drm_device *ddev = dev_get_drvdata(dev); | |
889 | ||
890 | drm_kms_helper_poll_enable(ddev); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | #endif | |
895 | ||
896 | static const struct dev_pm_ops msm_pm_ops = { | |
897 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) | |
898 | }; | |
899 | ||
060530f1 RC |
900 | /* |
901 | * Componentized driver support: | |
902 | */ | |
903 | ||
904 | #ifdef CONFIG_OF | |
905 | /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx | |
906 | * (or probably any other).. so probably some room for some helpers | |
907 | */ | |
908 | static int compare_of(struct device *dev, void *data) | |
909 | { | |
910 | return dev->of_node == data; | |
911 | } | |
41e69778 RC |
912 | |
913 | static int add_components(struct device *dev, struct component_match **matchptr, | |
914 | const char *name) | |
915 | { | |
916 | struct device_node *np = dev->of_node; | |
917 | unsigned i; | |
918 | ||
919 | for (i = 0; ; i++) { | |
920 | struct device_node *node; | |
921 | ||
922 | node = of_parse_phandle(np, name, i); | |
923 | if (!node) | |
924 | break; | |
925 | ||
926 | component_match_add(dev, matchptr, compare_of, node); | |
927 | } | |
928 | ||
929 | return 0; | |
930 | } | |
84448288 RK |
931 | #else |
932 | static int compare_dev(struct device *dev, void *data) | |
933 | { | |
934 | return dev == data; | |
935 | } | |
936 | #endif | |
937 | ||
938 | static int msm_drm_bind(struct device *dev) | |
939 | { | |
940 | return drm_platform_init(&msm_driver, to_platform_device(dev)); | |
941 | } | |
942 | ||
943 | static void msm_drm_unbind(struct device *dev) | |
944 | { | |
945 | drm_put_dev(platform_get_drvdata(to_platform_device(dev))); | |
946 | } | |
947 | ||
948 | static const struct component_master_ops msm_drm_ops = { | |
949 | .bind = msm_drm_bind, | |
950 | .unbind = msm_drm_unbind, | |
951 | }; | |
952 | ||
953 | /* | |
954 | * Platform driver: | |
955 | */ | |
060530f1 | 956 | |
84448288 | 957 | static int msm_pdev_probe(struct platform_device *pdev) |
060530f1 | 958 | { |
84448288 RK |
959 | struct component_match *match = NULL; |
960 | #ifdef CONFIG_OF | |
41e69778 RC |
961 | add_components(&pdev->dev, &match, "connectors"); |
962 | add_components(&pdev->dev, &match, "gpus"); | |
060530f1 | 963 | #else |
060530f1 RC |
964 | /* For non-DT case, it kinda sucks. We don't actually have a way |
965 | * to know whether or not we are waiting for certain devices (or if | |
966 | * they are simply not present). But for non-DT we only need to | |
967 | * care about apq8064/apq8060/etc (all mdp4/a3xx): | |
968 | */ | |
969 | static const char *devnames[] = { | |
970 | "hdmi_msm.0", "kgsl-3d0.0", | |
971 | }; | |
972 | int i; | |
973 | ||
974 | DBG("Adding components.."); | |
975 | ||
976 | for (i = 0; i < ARRAY_SIZE(devnames); i++) { | |
977 | struct device *dev; | |
978 | int ret; | |
979 | ||
980 | dev = bus_find_device_by_name(&platform_bus_type, | |
981 | NULL, devnames[i]); | |
982 | if (!dev) { | |
983 | dev_info(master, "still waiting for %s\n", devnames[i]); | |
984 | return -EPROBE_DEFER; | |
985 | } | |
986 | ||
84448288 | 987 | component_match_add(&pdev->dev, &match, compare_dev, dev); |
060530f1 | 988 | } |
060530f1 RC |
989 | #endif |
990 | ||
871d812a | 991 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
84448288 | 992 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
c8afe684 RC |
993 | } |
994 | ||
995 | static int msm_pdev_remove(struct platform_device *pdev) | |
996 | { | |
060530f1 | 997 | component_master_del(&pdev->dev, &msm_drm_ops); |
c8afe684 RC |
998 | |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static const struct platform_device_id msm_id[] = { | |
1003 | { "mdp", 0 }, | |
1004 | { } | |
1005 | }; | |
1006 | ||
06c0dd96 | 1007 | static const struct of_device_id dt_match[] = { |
41e69778 RC |
1008 | { .compatible = "qcom,mdp" }, /* mdp4 */ |
1009 | { .compatible = "qcom,mdss_mdp" }, /* mdp5 */ | |
06c0dd96 RC |
1010 | {} |
1011 | }; | |
1012 | MODULE_DEVICE_TABLE(of, dt_match); | |
1013 | ||
c8afe684 RC |
1014 | static struct platform_driver msm_platform_driver = { |
1015 | .probe = msm_pdev_probe, | |
1016 | .remove = msm_pdev_remove, | |
1017 | .driver = { | |
1018 | .owner = THIS_MODULE, | |
1019 | .name = "msm", | |
06c0dd96 | 1020 | .of_match_table = dt_match, |
c8afe684 RC |
1021 | .pm = &msm_pm_ops, |
1022 | }, | |
1023 | .id_table = msm_id, | |
1024 | }; | |
1025 | ||
1026 | static int __init msm_drm_register(void) | |
1027 | { | |
1028 | DBG("init"); | |
1029 | hdmi_register(); | |
7198e6b0 | 1030 | a3xx_register(); |
c8afe684 RC |
1031 | return platform_driver_register(&msm_platform_driver); |
1032 | } | |
1033 | ||
1034 | static void __exit msm_drm_unregister(void) | |
1035 | { | |
1036 | DBG("fini"); | |
1037 | platform_driver_unregister(&msm_platform_driver); | |
1038 | hdmi_unregister(); | |
7198e6b0 | 1039 | a3xx_unregister(); |
c8afe684 RC |
1040 | } |
1041 | ||
1042 | module_init(msm_drm_register); | |
1043 | module_exit(msm_drm_unregister); | |
1044 | ||
1045 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1046 | MODULE_DESCRIPTION("MSM DRM Driver"); | |
1047 | MODULE_LICENSE("GPL"); |