[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / msm_drv.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <asm/sizes.h>


#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
/* stubs we need for compile-test: */
static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
{
	return NULL;
}
#endif

#ifndef CONFIG_OF
#include <mach/board.h>
#include <mach/socinfo.h>
#include <mach/iommu_domains.h>
#endif

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;

#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */

struct msm_file_private {
	/* currently we don't do anything useful with this.. but when
	 * per-context address spaces are supported we'd keep track of
	 * the context's page-tables here.
	 */
	int dummy;
};

struct msm_drm_private {

	struct msm_kms *kms;

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;

	struct drm_fb_helper *fbdev;

	uint32_t next_fence, completed_fence;
	wait_queue_head_t fence_event;

	/* list of GEM objects: */
	struct list_head inactive_list;

	struct workqueue_struct *wq;

	/* callbacks deferred until bo is inactive: */
	struct list_head fence_cbs;

	/* registered MMUs: */
	unsigned int num_mmus;
	struct msm_mmu *mmus[NUM_DOMAINS];

	unsigned int num_planes;
	struct drm_plane *planes[8];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[8];

	unsigned int num_encoders;
	struct drm_encoder *encoders[8];

	unsigned int num_bridges;
	struct drm_bridge *bridges[8];

	unsigned int num_connectors;
	struct drm_connector *connectors[8];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
	} vram;
};

struct msm_format {
	uint32_t pixel_format;
};

/* callback from wq once fence has passed: */
struct msm_fence_cb {
	struct work_struct work;
	uint32_t fence;
	void (*func)(struct msm_fence_cb *cb);
};

void __msm_fence_worker(struct work_struct *work);

#define INIT_FENCE_CB(_cb, _func)  do {                     \
		INIT_WORK(&(_cb)->work, __msm_fence_worker); \
		(_cb)->func = _func;                         \
	} while (0)

/* As there are different display controller blocks depending on the
 * snapdragon version, the kms support is split out and the appropriate
 * implementation is loaded at runtime.  The kms module is responsible
 * for constructing the appropriate planes/crtcs/encoders/connectors.
 */
struct msm_kms_funcs {
	/* hw initialization: */
	int (*hw_init)(struct msm_kms *kms);
	/* irq handling: */
	void (*irq_preinstall)(struct msm_kms *kms);
	int (*irq_postinstall)(struct msm_kms *kms);
	void (*irq_uninstall)(struct msm_kms *kms);
	irqreturn_t (*irq)(struct msm_kms *kms);
	int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
	void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
	/* misc: */
	const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
	long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
			struct drm_encoder *encoder);
	/* cleanup: */
	void (*preclose)(struct msm_kms *kms, struct drm_file *file);
	void (*destroy)(struct msm_kms *kms);
};

struct msm_kms {
	const struct msm_kms_funcs *funcs;
};

struct msm_kms *mdp4_kms_init(struct drm_device *dev);

int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);

int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
		struct timespec *timeout);
void msm_update_fence(struct drm_device *dev, uint32_t fence);

int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
		uint32_t *iova);
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
void msm_gem_put_iova(struct drm_gem_object *obj, int id);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		size_t size, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
void *msm_gem_vaddr(struct drm_gem_object *obj);
int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
		struct msm_fence_cb *cb);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool write, uint32_t fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
		struct timespec *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		uint32_t size, struct sg_table *sgt);

struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
		struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);

int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
void __init hdmi_register(void);
void __exit hdmi_unregister(void);

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
#endif

void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)

static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
{
	struct msm_drm_private *priv = dev->dev_private;
	return priv->completed_fence >= fence;
}

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)


#endif /* __MSM_DRV_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRV_H__
	19	#define __MSM_DRV_H__
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/module.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/pm.h>
	27	#include <linux/pm_runtime.h>
	28	#include <linux/slab.h>
	29	#include <linux/list.h>
	30	#include <linux/iommu.h>
	31	#include <linux/types.h>
	32	#include <asm/sizes.h>
	33
3083894f RC	34
	35	#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
	36	/* stubs we need for compile-test: */
	37	static inline struct device msm_iommu_get_ctx(const char ctx_name)
	38	{
	39	return NULL;
	40	}
	41	#endif
	42
c8afe684 RC	43	#ifndef CONFIG_OF
	44	#include <mach/board.h>
	45	#include <mach/socinfo.h>
	46	#include <mach/iommu_domains.h>
	47	#endif
	48
	49	#include <drm/drmP.h>
	50	#include <drm/drm_crtc_helper.h>
	51	#include <drm/drm_fb_helper.h>
7198e6b0	52	#include <drm/msm_drm.h>
c8afe684 RC	53
c8afe684 RC	54	struct msm_kms;
7198e6b0	55	struct msm_gpu;
871d812a	56	struct msm_mmu;
c8afe684	57
7198e6b0 RC	58	#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
	59
	60	struct msm_file_private {
	61	/* currently we don't do anything useful with this.. but when
	62	* per-context address spaces are supported we'd keep track of
	63	* the context's page-tables here.
	64	*/
	65	int dummy;
	66	};
c8afe684 RC	67
	68	struct msm_drm_private {
	69
	70	struct msm_kms *kms;
	71
7198e6b0 RC	72	/* when we have more than one 'msm_gpu' these need to be an array: */
	73	struct msm_gpu *gpu;
	74	struct msm_file_private *lastctx;
	75
c8afe684 RC	76	struct drm_fb_helper *fbdev;
c8afe684 RC	77
7198e6b0 RC	78	uint32_t next_fence, completed_fence;
	79	wait_queue_head_t fence_event;
	80
c8afe684 RC	81	/* list of GEM objects: */
	82	struct list_head inactive_list;
	83
	84	struct workqueue_struct *wq;
	85
edd4fc63 RC	86	/* callbacks deferred until bo is inactive: */
	87	struct list_head fence_cbs;
	88
871d812a RC	89	/* registered MMUs: */
	90	unsigned int num_mmus;
	91	struct msm_mmu *mmus[NUM_DOMAINS];
c8afe684	92
a8623918 RC	93	unsigned int num_planes;
	94	struct drm_plane *planes[8];
	95
c8afe684 RC	96	unsigned int num_crtcs;
	97	struct drm_crtc *crtcs[8];
	98
	99	unsigned int num_encoders;
	100	struct drm_encoder *encoders[8];
	101
a3376e3e RC	102	unsigned int num_bridges;
	103	struct drm_bridge *bridges[8];
	104
c8afe684 RC	105	unsigned int num_connectors;
c8afe684 RC	106	struct drm_connector *connectors[8];
871d812a RC	107
	108	/* VRAM carveout, used when no IOMMU: */
	109	struct {
	110	unsigned long size;
	111	dma_addr_t paddr;
	112	/* NOTE: mm managed at the page level, size is in # of pages
	113	* and position mm_node->start is in # of pages:
	114	*/
	115	struct drm_mm mm;
	116	} vram;
c8afe684 RC	117	};
	118
	119	struct msm_format {
	120	uint32_t pixel_format;
	121	};
	122
edd4fc63 RC	123	/* callback from wq once fence has passed: */
	124	struct msm_fence_cb {
	125	struct work_struct work;
	126	uint32_t fence;
	127	void (func)(struct msm_fence_cb cb);
	128	};
	129
	130	void __msm_fence_worker(struct work_struct *work);
	131
	132	#define INIT_FENCE_CB(_cb, _func) do { \
	133	INIT_WORK(&(_cb)->work, __msm_fence_worker); \
	134	(_cb)->func = _func; \
	135	} while (0)
	136
c8afe684 RC	137	/* As there are different display controller blocks depending on the
	138	* snapdragon version, the kms support is split out and the appropriate
	139	* implementation is loaded at runtime. The kms module is responsible
	140	* for constructing the appropriate planes/crtcs/encoders/connectors.
	141	*/
	142	struct msm_kms_funcs {
	143	/* hw initialization: */
	144	int (hw_init)(struct msm_kms kms);
	145	/* irq handling: */
	146	void (irq_preinstall)(struct msm_kms kms);
	147	int (irq_postinstall)(struct msm_kms kms);
	148	void (irq_uninstall)(struct msm_kms kms);
	149	irqreturn_t (irq)(struct msm_kms kms);
	150	int (enable_vblank)(struct msm_kms kms, struct drm_crtc *crtc);
	151	void (disable_vblank)(struct msm_kms kms, struct drm_crtc *crtc);
	152	/* misc: */
	153	const struct msm_format (get_format)(struct msm_kms *kms, uint32_t format);
	154	long (round_pixclk)(struct msm_kms kms, unsigned long rate,
	155	struct drm_encoder *encoder);
	156	/* cleanup: */
	157	void (preclose)(struct msm_kms kms, struct drm_file *file);
	158	void (destroy)(struct msm_kms kms);
	159	};
	160
	161	struct msm_kms {
	162	const struct msm_kms_funcs *funcs;
	163	};
	164
	165	struct msm_kms mdp4_kms_init(struct drm_device dev);
	166
871d812a	167	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);
c8afe684	168
7198e6b0 RC	169	int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
	170	struct timespec *timeout);
	171	void msm_update_fence(struct drm_device *dev, uint32_t fence);
	172
	173	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	174	struct drm_file *file);
	175
c8afe684 RC	176	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
	177	int msm_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
	178	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
	179	int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
	180	uint32_t *iova);
	181	int msm_gem_get_iova(struct drm_gem_object obj, int id, uint32_t iova);
05b84911 RC	182	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	183	void msm_gem_put_pages(struct drm_gem_object *obj);
c8afe684 RC	184	void msm_gem_put_iova(struct drm_gem_object *obj, int id);
	185	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
	186	struct drm_mode_create_dumb *args);
c8afe684 RC	187	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	188	uint32_t handle, uint64_t *offset);
05b84911 RC	189	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	190	void msm_gem_prime_vmap(struct drm_gem_object obj);
	191	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
	192	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
	193	size_t size, struct sg_table *sg);
	194	int msm_gem_prime_pin(struct drm_gem_object *obj);
	195	void msm_gem_prime_unpin(struct drm_gem_object *obj);
c8afe684 RC	196	void msm_gem_vaddr_locked(struct drm_gem_object obj);
c8afe684 RC	197	void msm_gem_vaddr(struct drm_gem_object obj);
edd4fc63 RC	198	int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
edd4fc63 RC	199	struct msm_fence_cb *cb);
7198e6b0	200	void msm_gem_move_to_active(struct drm_gem_object *obj,
bf6811f3	201	struct msm_gpu *gpu, bool write, uint32_t fence);
7198e6b0 RC	202	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
	203	int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
	204	struct timespec *timeout);
	205	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	206	void msm_gem_free_object(struct drm_gem_object *obj);
	207	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
	208	uint32_t size, uint32_t flags, uint32_t *handle);
	209	struct drm_gem_object msm_gem_new(struct drm_device dev,
	210	uint32_t size, uint32_t flags);
05b84911 RC	211	struct drm_gem_object msm_gem_import(struct drm_device dev,
05b84911 RC	212	uint32_t size, struct sg_table *sgt);
c8afe684 RC	213
	214	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
	215	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
	216	struct drm_framebuffer msm_framebuffer_init(struct drm_device dev,
	217	struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_object *bos);
	218	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
	219	struct drm_file file, struct drm_mode_fb_cmd2 mode_cmd);
	220
	221	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
	222
a3376e3e	223	int hdmi_init(struct drm_device dev, struct drm_encoder encoder);
c8afe684 RC	224	void __init hdmi_register(void);
	225	void __exit hdmi_unregister(void);
	226
	227	#ifdef CONFIG_DEBUG_FS
	228	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	229	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	230	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
	231	#endif
	232
	233	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	234	const char *dbgname);
	235	void msm_writel(u32 data, void __iomem *addr);
	236	u32 msm_readl(const void __iomem *addr);
	237
	238	#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	239	#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	240
f816f272 RC	241	static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
	242	{
	243	struct msm_drm_private *priv = dev->dev_private;
	244	return priv->completed_fence >= fence;
	245	}
	246
c8afe684 RC	247	static inline int align_pitch(int width, int bpp)
	248	{
	249	int bytespp = (bpp + 7) / 8;
	250	/* adreno needs pitch aligned to 32 pixels: */
	251	return bytespp * ALIGN(width, 32);
	252	}
	253
	254	/* for the generated headers: */
	255	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	256	#define fui(x) ({BUG(); 0;})
	257	#define util_float_to_half(x) ({BUG(); 0;})
	258
c8afe684 RC	259
	260	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	261
	262	/* for conditionally setting boolean flag(s): */
	263	#define COND(bool, val) ((bool) ? (val) : 0)
	264
c8afe684 RC	265
c8afe684 RC	266	#endif /* __MSM_DRV_H__ */