[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / msm_drv.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/component.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/of_graph.h>
#include <asm/sizes.h>

#ifndef CONFIG_OF
#include <mach/board.h>
#include <mach/socinfo.h>
#include <mach/iommu_domains.h>
#endif

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;
struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;

#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */

struct msm_file_private {
	/* currently we don't do anything useful with this.. but when
	 * per-context address spaces are supported we'd keep track of
	 * the context's page-tables here.
	 */
	int dummy;
};

enum msm_mdp_plane_property {
	PLANE_PROP_ZPOS,
	PLANE_PROP_ALPHA,
	PLANE_PROP_PREMULTIPLIED,
	PLANE_PROP_MAX_NUM
};

struct msm_vblank_ctrl {
	struct work_struct work;
	struct list_head event_list;
	spinlock_t lock;
};

struct msm_drm_private {

	struct msm_kms *kms;

	/* subordinate devices, if present: */
	struct platform_device *gpu_pdev;

	/* possibly this should be in the kms component, but it is
	 * shared by both mdp4 and mdp5..
	 */
	struct hdmi *hdmi;

	/* eDP is for mdp5 only, but kms has not been created
	 * when edp_bind() and edp_init() are called. Here is the only
	 * place to keep the edp instance.
	 */
	struct msm_edp *edp;

	/* DSI is shared by mdp4 and mdp5 */
	struct msm_dsi *dsi[2];

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;

	struct drm_fb_helper *fbdev;

	uint32_t next_fence, completed_fence;
	wait_queue_head_t fence_event;

	struct msm_rd_state *rd;
	struct msm_perf_state *perf;

	/* list of GEM objects: */
	struct list_head inactive_list;

	struct workqueue_struct *wq;

	/* callbacks deferred until bo is inactive: */
	struct list_head fence_cbs;

	/* crtcs pending async atomic updates: */
	uint32_t pending_crtcs;
	wait_queue_head_t pending_crtcs_event;

	/* registered MMUs: */
	unsigned int num_mmus;
	struct msm_mmu *mmus[NUM_DOMAINS];

	unsigned int num_planes;
	struct drm_plane *planes[8];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[8];

	unsigned int num_encoders;
	struct drm_encoder *encoders[8];

	unsigned int num_bridges;
	struct drm_bridge *bridges[8];

	unsigned int num_connectors;
	struct drm_connector *connectors[8];

	/* Properties */
	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
	} vram;

	struct msm_vblank_ctrl vblank_ctrl;
};

struct msm_format {
	uint32_t pixel_format;
};

/* callback from wq once fence has passed: */
struct msm_fence_cb {
	struct work_struct work;
	uint32_t fence;
	void (*func)(struct msm_fence_cb *cb);
};

void __msm_fence_worker(struct work_struct *work);

#define INIT_FENCE_CB(_cb, _func)  do {                     \
		INIT_WORK(&(_cb)->work, __msm_fence_worker); \
		(_cb)->func = _func;                         \
	} while (0)

int msm_atomic_check(struct drm_device *dev,
		     struct drm_atomic_state *state);
int msm_atomic_commit(struct drm_device *dev,
		struct drm_atomic_state *state, bool async);

int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);

int msm_wait_fence(struct drm_device *dev, uint32_t fence,
		ktime_t *timeout, bool interruptible);
int msm_queue_fence_cb(struct drm_device *dev,
		struct msm_fence_cb *cb, uint32_t fence);
void msm_update_fence(struct drm_device *dev, uint32_t fence);

int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

int msm_gem_mmap_obj(struct drm_gem_object *obj,
			struct vm_area_struct *vma);
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
		uint32_t *iova);
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
void msm_gem_put_iova(struct drm_gem_object *obj, int id);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		struct dma_buf_attachment *attach, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
void *msm_gem_vaddr(struct drm_gem_object *obj);
int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
		struct msm_fence_cb *cb);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool write, uint32_t fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
		ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		uint32_t size, struct sg_table *sgt);

int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
		struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);

struct hdmi;
int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
		struct drm_encoder *encoder);
void __init hdmi_register(void);
void __exit hdmi_unregister(void);

struct msm_edp;
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
		struct drm_encoder *encoder);

struct msm_dsi;
enum msm_dsi_encoder_id {
	MSM_DSI_VIDEO_ENCODER_ID = 0,
	MSM_DSI_CMD_ENCODER_ID = 1,
	MSM_DSI_ENCODER_NUM = 2
};
#ifdef CONFIG_DRM_MSM_DSI
void __init msm_dsi_register(void);
void __exit msm_dsi_unregister(void);
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
#else
static inline void __init msm_dsi_register(void)
{
}
static inline void __exit msm_dsi_unregister(void)
{
}
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
		struct drm_device *dev,
		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
{
	return -EINVAL;
}
#endif

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
int msm_debugfs_late_init(struct drm_device *dev);
int msm_rd_debugfs_init(struct drm_minor *minor);
void msm_rd_debugfs_cleanup(struct drm_minor *minor);
void msm_rd_dump_submit(struct msm_gem_submit *submit);
int msm_perf_debugfs_init(struct drm_minor *minor);
void msm_perf_debugfs_cleanup(struct drm_minor *minor);
#else
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
#endif

void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)

static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
{
	struct msm_drm_private *priv = dev->dev_private;
	return priv->completed_fence >= fence;
}

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)


#endif /* __MSM_DRV_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRV_H__
	19	#define __MSM_DRV_H__
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/module.h>
060530f1	25	#include <linux/component.h>
c8afe684 RC	26	#include <linux/platform_device.h>
	27	#include <linux/pm.h>
	28	#include <linux/pm_runtime.h>
	29	#include <linux/slab.h>
	30	#include <linux/list.h>
	31	#include <linux/iommu.h>
	32	#include <linux/types.h>
3d6df062	33	#include <linux/of_graph.h>
c8afe684 RC	34	#include <asm/sizes.h>
	35
	36	#ifndef CONFIG_OF
	37	#include <mach/board.h>
	38	#include <mach/socinfo.h>
	39	#include <mach/iommu_domains.h>
	40	#endif
	41
	42	#include <drm/drmP.h>
cf3a7e4c RC	43	#include <drm/drm_atomic.h>
cf3a7e4c RC	44	#include <drm/drm_atomic_helper.h>
c8afe684	45	#include <drm/drm_crtc_helper.h>
cf3a7e4c	46	#include <drm/drm_plane_helper.h>
c8afe684	47	#include <drm/drm_fb_helper.h>
7198e6b0	48	#include <drm/msm_drm.h>
d9fc9413	49	#include <drm/drm_gem.h>
c8afe684 RC	50
c8afe684 RC	51	struct msm_kms;
7198e6b0	52	struct msm_gpu;
871d812a	53	struct msm_mmu;
a7d3c950	54	struct msm_rd_state;
70c70f09	55	struct msm_perf_state;
a7d3c950	56	struct msm_gem_submit;
c8afe684	57
7198e6b0 RC	58	#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
	59
	60	struct msm_file_private {
	61	/* currently we don't do anything useful with this.. but when
	62	* per-context address spaces are supported we'd keep track of
	63	* the context's page-tables here.
	64	*/
	65	int dummy;
	66	};
c8afe684	67
12987781	68	enum msm_mdp_plane_property {
	69	PLANE_PROP_ZPOS,
	70	PLANE_PROP_ALPHA,
	71	PLANE_PROP_PREMULTIPLIED,
	72	PLANE_PROP_MAX_NUM
	73	};
	74
78b1d470 HL	75	struct msm_vblank_ctrl {
	76	struct work_struct work;
	77	struct list_head event_list;
	78	spinlock_t lock;
	79	};
	80
c8afe684 RC	81	struct msm_drm_private {
	82
	83	struct msm_kms *kms;
	84
060530f1	85	/* subordinate devices, if present: */
067fef37 RC	86	struct platform_device *gpu_pdev;
	87
	88	/* possibly this should be in the kms component, but it is
	89	* shared by both mdp4 and mdp5..
	90	*/
	91	struct hdmi *hdmi;
060530f1	92
ab5b0107 HL	93	/* eDP is for mdp5 only, but kms has not been created
	94	* when edp_bind() and edp_init() are called. Here is the only
	95	* place to keep the edp instance.
	96	*/
	97	struct msm_edp *edp;
	98
a689554b HL	99	/* DSI is shared by mdp4 and mdp5 */
	100	struct msm_dsi *dsi[2];
	101
7198e6b0 RC	102	/* when we have more than one 'msm_gpu' these need to be an array: */
	103	struct msm_gpu *gpu;
	104	struct msm_file_private *lastctx;
	105
c8afe684 RC	106	struct drm_fb_helper *fbdev;
c8afe684 RC	107
7198e6b0 RC	108	uint32_t next_fence, completed_fence;
	109	wait_queue_head_t fence_event;
	110
a7d3c950	111	struct msm_rd_state *rd;
70c70f09	112	struct msm_perf_state *perf;
a7d3c950	113
c8afe684 RC	114	/* list of GEM objects: */
	115	struct list_head inactive_list;
	116
	117	struct workqueue_struct *wq;
	118
edd4fc63 RC	119	/* callbacks deferred until bo is inactive: */
	120	struct list_head fence_cbs;
	121
f86afecf RC	122	/* crtcs pending async atomic updates: */
	123	uint32_t pending_crtcs;
	124	wait_queue_head_t pending_crtcs_event;
	125
871d812a RC	126	/* registered MMUs: */
	127	unsigned int num_mmus;
	128	struct msm_mmu *mmus[NUM_DOMAINS];
c8afe684	129
a8623918 RC	130	unsigned int num_planes;
	131	struct drm_plane *planes[8];
	132
c8afe684 RC	133	unsigned int num_crtcs;
	134	struct drm_crtc *crtcs[8];
	135
	136	unsigned int num_encoders;
	137	struct drm_encoder *encoders[8];
	138
a3376e3e RC	139	unsigned int num_bridges;
	140	struct drm_bridge *bridges[8];
	141
c8afe684 RC	142	unsigned int num_connectors;
c8afe684 RC	143	struct drm_connector *connectors[8];
871d812a	144
12987781	145	/* Properties */
	146	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
	147
871d812a RC	148	/* VRAM carveout, used when no IOMMU: */
	149	struct {
	150	unsigned long size;
	151	dma_addr_t paddr;
	152	/* NOTE: mm managed at the page level, size is in # of pages
	153	* and position mm_node->start is in # of pages:
	154	*/
	155	struct drm_mm mm;
	156	} vram;
78b1d470 HL	157
78b1d470 HL	158	struct msm_vblank_ctrl vblank_ctrl;
c8afe684 RC	159	};
	160
	161	struct msm_format {
	162	uint32_t pixel_format;
	163	};
	164
edd4fc63 RC	165	/* callback from wq once fence has passed: */
	166	struct msm_fence_cb {
	167	struct work_struct work;
	168	uint32_t fence;
	169	void (func)(struct msm_fence_cb cb);
	170	};
	171
	172	void __msm_fence_worker(struct work_struct *work);
	173
	174	#define INIT_FENCE_CB(_cb, _func) do { \
	175	INIT_WORK(&(_cb)->work, __msm_fence_worker); \
	176	(_cb)->func = _func; \
	177	} while (0)
	178
b4274fbe DV	179	int msm_atomic_check(struct drm_device *dev,
b4274fbe DV	180	struct drm_atomic_state *state);
cf3a7e4c RC	181	int msm_atomic_commit(struct drm_device *dev,
	182	struct drm_atomic_state *state, bool async);
	183
871d812a	184	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);
c8afe684	185
a9702ca2 WX	186	int msm_wait_fence(struct drm_device *dev, uint32_t fence,
a9702ca2 WX	187	ktime_t *timeout, bool interruptible);
69193e50 RC	188	int msm_queue_fence_cb(struct drm_device *dev,
69193e50 RC	189	struct msm_fence_cb *cb, uint32_t fence);
7198e6b0 RC	190	void msm_update_fence(struct drm_device *dev, uint32_t fence);
	191
	192	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	193	struct drm_file *file);
	194
77a147e7 DT	195	int msm_gem_mmap_obj(struct drm_gem_object *obj,
77a147e7 DT	196	struct vm_area_struct *vma);
c8afe684 RC	197	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
	198	int msm_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
	199	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
	200	int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
	201	uint32_t *iova);
	202	int msm_gem_get_iova(struct drm_gem_object obj, int id, uint32_t iova);
2638d90a	203	uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
05b84911 RC	204	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	205	void msm_gem_put_pages(struct drm_gem_object *obj);
c8afe684 RC	206	void msm_gem_put_iova(struct drm_gem_object *obj, int id);
	207	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
	208	struct drm_mode_create_dumb *args);
c8afe684 RC	209	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	210	uint32_t handle, uint64_t *offset);
05b84911 RC	211	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	212	void msm_gem_prime_vmap(struct drm_gem_object obj);
	213	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
77a147e7	214	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
05b84911	215	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
b5e9c1a2	216	struct dma_buf_attachment attach, struct sg_table sg);
05b84911 RC	217	int msm_gem_prime_pin(struct drm_gem_object *obj);
05b84911 RC	218	void msm_gem_prime_unpin(struct drm_gem_object *obj);
c8afe684 RC	219	void msm_gem_vaddr_locked(struct drm_gem_object obj);
c8afe684 RC	220	void msm_gem_vaddr(struct drm_gem_object obj);
edd4fc63 RC	221	int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
edd4fc63 RC	222	struct msm_fence_cb *cb);
7198e6b0	223	void msm_gem_move_to_active(struct drm_gem_object *obj,
bf6811f3	224	struct msm_gpu *gpu, bool write, uint32_t fence);
7198e6b0 RC	225	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
7198e6b0 RC	226	int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
56c2da83	227	ktime_t *timeout);
7198e6b0	228	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	229	void msm_gem_free_object(struct drm_gem_object *obj);
	230	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
	231	uint32_t size, uint32_t flags, uint32_t *handle);
	232	struct drm_gem_object msm_gem_new(struct drm_device dev,
	233	uint32_t size, uint32_t flags);
05b84911 RC	234	struct drm_gem_object msm_gem_import(struct drm_device dev,
05b84911 RC	235	uint32_t size, struct sg_table *sgt);
c8afe684	236
2638d90a RC	237	int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
	238	void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
	239	uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
c8afe684 RC	240	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
	241	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
	242	struct drm_framebuffer msm_framebuffer_init(struct drm_device dev,
	243	struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_object *bos);
	244	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
	245	struct drm_file file, struct drm_mode_fb_cmd2 mode_cmd);
	246
	247	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
	248
dada25bd	249	struct hdmi;
067fef37 RC	250	int hdmi_modeset_init(struct hdmi hdmi, struct drm_device dev,
067fef37 RC	251	struct drm_encoder *encoder);
c8afe684 RC	252	void __init hdmi_register(void);
	253	void __exit hdmi_unregister(void);
	254
00453981 HL	255	struct msm_edp;
	256	void __init msm_edp_register(void);
	257	void __exit msm_edp_unregister(void);
	258	int msm_edp_modeset_init(struct msm_edp edp, struct drm_device dev,
	259	struct drm_encoder *encoder);
	260
a689554b HL	261	struct msm_dsi;
	262	enum msm_dsi_encoder_id {
	263	MSM_DSI_VIDEO_ENCODER_ID = 0,
	264	MSM_DSI_CMD_ENCODER_ID = 1,
	265	MSM_DSI_ENCODER_NUM = 2
	266	};
	267	#ifdef CONFIG_DRM_MSM_DSI
	268	void __init msm_dsi_register(void);
	269	void __exit msm_dsi_unregister(void);
	270	int msm_dsi_modeset_init(struct msm_dsi msm_dsi, struct drm_device dev,
	271	struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
	272	#else
	273	static inline void __init msm_dsi_register(void)
	274	{
	275	}
	276	static inline void __exit msm_dsi_unregister(void)
	277	{
	278	}
	279	static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
	280	struct drm_device *dev,
	281	struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
	282	{
	283	return -EINVAL;
	284	}
	285	#endif
	286
c8afe684 RC	287	#ifdef CONFIG_DEBUG_FS
	288	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	289	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	290	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
a7d3c950 RC	291	int msm_debugfs_late_init(struct drm_device *dev);
	292	int msm_rd_debugfs_init(struct drm_minor *minor);
	293	void msm_rd_debugfs_cleanup(struct drm_minor *minor);
	294	void msm_rd_dump_submit(struct msm_gem_submit *submit);
70c70f09 RC	295	int msm_perf_debugfs_init(struct drm_minor *minor);
70c70f09 RC	296	void msm_perf_debugfs_cleanup(struct drm_minor *minor);
a7d3c950 RC	297	#else
	298	static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
	299	static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
c8afe684 RC	300	#endif
	301
	302	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	303	const char *dbgname);
	304	void msm_writel(u32 data, void __iomem *addr);
	305	u32 msm_readl(const void __iomem *addr);
	306
	307	#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	308	#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	309
f816f272 RC	310	static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
	311	{
	312	struct msm_drm_private *priv = dev->dev_private;
	313	return priv->completed_fence >= fence;
	314	}
	315
c8afe684 RC	316	static inline int align_pitch(int width, int bpp)
	317	{
	318	int bytespp = (bpp + 7) / 8;
	319	/* adreno needs pitch aligned to 32 pixels: */
	320	return bytespp * ALIGN(width, 32);
	321	}
	322
	323	/* for the generated headers: */
	324	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	325	#define fui(x) ({BUG(); 0;})
	326	#define util_float_to_half(x) ({BUG(); 0;})
	327
c8afe684 RC	328
	329	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	330
	331	/* for conditionally setting boolean flag(s): */
	332	#define COND(bool, val) ((bool) ? (val) : 0)
	333
c8afe684 RC	334
c8afe684 RC	335	#endif /* __MSM_DRV_H__ */