[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / msm / msm_drv.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/component.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/of_graph.h>
#include <linux/of_device.h>
#include <asm/sizes.h>

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;
struct msm_mdss;
struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;
struct msm_fence_context;
struct msm_fence_cb;
struct msm_gem_address_space;
struct msm_gem_vma;

#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */

struct msm_file_private {
	/* currently we don't do anything useful with this.. but when
	 * per-context address spaces are supported we'd keep track of
	 * the context's page-tables here.
	 */
	int dummy;
};

enum msm_mdp_plane_property {
	PLANE_PROP_ZPOS,
	PLANE_PROP_ALPHA,
	PLANE_PROP_PREMULTIPLIED,
	PLANE_PROP_MAX_NUM
};

struct msm_vblank_ctrl {
	struct work_struct work;
	struct list_head event_list;
	spinlock_t lock;
};

struct msm_drm_private {

	struct drm_device *dev;

	struct msm_kms *kms;

	/* subordinate devices, if present: */
	struct platform_device *gpu_pdev;

	/* top level MDSS wrapper device (for MDP5 only) */
	struct msm_mdss *mdss;

	/* possibly this should be in the kms component, but it is
	 * shared by both mdp4 and mdp5..
	 */
	struct hdmi *hdmi;

	/* eDP is for mdp5 only, but kms has not been created
	 * when edp_bind() and edp_init() are called. Here is the only
	 * place to keep the edp instance.
	 */
	struct msm_edp *edp;

	/* DSI is shared by mdp4 and mdp5 */
	struct msm_dsi *dsi[2];

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;

	struct drm_fb_helper *fbdev;

	struct msm_rd_state *rd;
	struct msm_perf_state *perf;

	/* list of GEM objects: */
	struct list_head inactive_list;

	struct workqueue_struct *wq;
	struct workqueue_struct *atomic_wq;

	/* crtcs pending async atomic updates: */
	uint32_t pending_crtcs;
	wait_queue_head_t pending_crtcs_event;

	/* Registered address spaces.. currently this is fixed per # of
	 * iommu's.  Ie. one for display block and one for gpu block.
	 * Eventually, to do per-process gpu pagetables, we'll want one
	 * of these per-process.
	 */
	unsigned int num_aspaces;
	struct msm_gem_address_space *aspace[NUM_DOMAINS];

	unsigned int num_planes;
	struct drm_plane *planes[16];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[8];

	unsigned int num_encoders;
	struct drm_encoder *encoders[8];

	unsigned int num_bridges;
	struct drm_bridge *bridges[8];

	unsigned int num_connectors;
	struct drm_connector *connectors[8];

	/* Properties */
	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
	} vram;

	struct notifier_block vmap_notifier;
	struct shrinker shrinker;

	struct msm_vblank_ctrl vblank_ctrl;

	/* task holding struct_mutex.. currently only used in submit path
	 * to detect and reject faults from copy_from_user() for submit
	 * ioctl.
	 */
	struct task_struct *struct_mutex_task;
};

struct msm_format {
	uint32_t pixel_format;
};

int msm_atomic_check(struct drm_device *dev,
		     struct drm_atomic_state *state);
int msm_atomic_commit(struct drm_device *dev,
		struct drm_atomic_state *state, bool nonblock);
struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
void msm_atomic_state_clear(struct drm_atomic_state *state);
void msm_atomic_state_free(struct drm_atomic_state *state);

int msm_register_address_space(struct drm_device *dev,
		struct msm_gem_address_space *aspace);

void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, struct sg_table *sgt);
int msm_gem_map_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, struct sg_table *sgt, int npages);

void msm_gem_address_space_put(struct msm_gem_address_space *aspace);

struct msm_gem_address_space *
msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
		const char *name);

void msm_gem_submit_free(struct msm_gem_submit *submit);
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

void msm_gem_shrinker_init(struct drm_device *dev);
void msm_gem_shrinker_cleanup(struct drm_device *dev);

int msm_gem_mmap_obj(struct drm_gem_object *obj,
			struct vm_area_struct *vma);
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
int msm_gem_fault(struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
		uint64_t *iova);
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova);
uint64_t msm_gem_iova(struct drm_gem_object *obj, int id);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
void msm_gem_put_iova(struct drm_gem_object *obj, int id);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		struct dma_buf_attachment *attach, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
void msm_gem_put_vaddr(struct drm_gem_object *obj);
int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
void msm_gem_purge(struct drm_gem_object *obj);
void msm_gem_vunmap(struct drm_gem_object *obj);
int msm_gem_sync_object(struct drm_gem_object *obj,
		struct msm_fence_context *fctx, bool exclusive);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		struct dma_buf *dmabuf, struct sg_table *sgt);

int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
		const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
void msm_fbdev_free(struct drm_device *dev);

struct hdmi;
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
		struct drm_encoder *encoder);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);

struct msm_edp;
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
		struct drm_encoder *encoder);

struct msm_dsi;
#ifdef CONFIG_DRM_MSM_DSI
void __init msm_dsi_register(void);
void __exit msm_dsi_unregister(void);
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
			 struct drm_encoder *encoder);
#else
static inline void __init msm_dsi_register(void)
{
}
static inline void __exit msm_dsi_unregister(void)
{
}
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
				       struct drm_device *dev,
				       struct drm_encoder *encoder)
{
	return -EINVAL;
}
#endif

void __init msm_mdp_register(void);
void __exit msm_mdp_unregister(void);

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
int msm_debugfs_late_init(struct drm_device *dev);
int msm_rd_debugfs_init(struct drm_minor *minor);
void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
void msm_rd_dump_submit(struct msm_gem_submit *submit);
int msm_perf_debugfs_init(struct drm_minor *minor);
void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
#else
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
#endif

struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)

static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
{
	ktime_t now = ktime_get();
	unsigned long remaining_jiffies;

	if (ktime_compare(*timeout, now) < 0) {
		remaining_jiffies = 0;
	} else {
		ktime_t rem = ktime_sub(*timeout, now);
		struct timespec ts = ktime_to_timespec(rem);
		remaining_jiffies = timespec_to_jiffies(&ts);
	}

	return remaining_jiffies;
}

#endif /* __MSM_DRV_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRV_H__
	19	#define __MSM_DRV_H__
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/module.h>
060530f1	25	#include <linux/component.h>
c8afe684 RC	26	#include <linux/platform_device.h>
	27	#include <linux/pm.h>
	28	#include <linux/pm_runtime.h>
	29	#include <linux/slab.h>
	30	#include <linux/list.h>
	31	#include <linux/iommu.h>
	32	#include <linux/types.h>
3d6df062	33	#include <linux/of_graph.h>
e9fbdaf2	34	#include <linux/of_device.h>
c8afe684 RC	35	#include <asm/sizes.h>
c8afe684 RC	36
c8afe684	37	#include <drm/drmP.h>
cf3a7e4c RC	38	#include <drm/drm_atomic.h>
cf3a7e4c RC	39	#include <drm/drm_atomic_helper.h>
c8afe684	40	#include <drm/drm_crtc_helper.h>
cf3a7e4c	41	#include <drm/drm_plane_helper.h>
c8afe684	42	#include <drm/drm_fb_helper.h>
7198e6b0	43	#include <drm/msm_drm.h>
d9fc9413	44	#include <drm/drm_gem.h>
c8afe684 RC	45
c8afe684 RC	46	struct msm_kms;
7198e6b0	47	struct msm_gpu;
871d812a	48	struct msm_mmu;
990a4007	49	struct msm_mdss;
a7d3c950	50	struct msm_rd_state;
70c70f09	51	struct msm_perf_state;
a7d3c950	52	struct msm_gem_submit;
ca762a8a	53	struct msm_fence_context;
fde5de6c	54	struct msm_fence_cb;
667ce33e RC	55	struct msm_gem_address_space;
667ce33e RC	56	struct msm_gem_vma;
c8afe684	57
7198e6b0 RC	58	#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
	59
	60	struct msm_file_private {
	61	/* currently we don't do anything useful with this.. but when
	62	* per-context address spaces are supported we'd keep track of
	63	* the context's page-tables here.
	64	*/
	65	int dummy;
	66	};
c8afe684	67
12987781	68	enum msm_mdp_plane_property {
	69	PLANE_PROP_ZPOS,
	70	PLANE_PROP_ALPHA,
	71	PLANE_PROP_PREMULTIPLIED,
	72	PLANE_PROP_MAX_NUM
	73	};
	74
78b1d470 HL	75	struct msm_vblank_ctrl {
	76	struct work_struct work;
	77	struct list_head event_list;
	78	spinlock_t lock;
	79	};
	80
c8afe684 RC	81	struct msm_drm_private {
c8afe684 RC	82
68209390 RC	83	struct drm_device *dev;
68209390 RC	84
c8afe684 RC	85	struct msm_kms *kms;
c8afe684 RC	86
060530f1	87	/* subordinate devices, if present: */
067fef37 RC	88	struct platform_device *gpu_pdev;
067fef37 RC	89
990a4007 AT	90	/* top level MDSS wrapper device (for MDP5 only) */
	91	struct msm_mdss *mdss;
	92
067fef37 RC	93	/* possibly this should be in the kms component, but it is
	94	* shared by both mdp4 and mdp5..
	95	*/
	96	struct hdmi *hdmi;
060530f1	97
ab5b0107 HL	98	/* eDP is for mdp5 only, but kms has not been created
	99	* when edp_bind() and edp_init() are called. Here is the only
	100	* place to keep the edp instance.
	101	*/
	102	struct msm_edp *edp;
	103
a689554b HL	104	/* DSI is shared by mdp4 and mdp5 */
	105	struct msm_dsi *dsi[2];
	106
7198e6b0 RC	107	/* when we have more than one 'msm_gpu' these need to be an array: */
	108	struct msm_gpu *gpu;
	109	struct msm_file_private *lastctx;
	110
c8afe684 RC	111	struct drm_fb_helper *fbdev;
c8afe684 RC	112
a7d3c950	113	struct msm_rd_state *rd;
70c70f09	114	struct msm_perf_state *perf;
a7d3c950	115
c8afe684 RC	116	/* list of GEM objects: */
	117	struct list_head inactive_list;
	118
	119	struct workqueue_struct *wq;
ba00c3f2	120	struct workqueue_struct *atomic_wq;
c8afe684	121
f86afecf RC	122	/* crtcs pending async atomic updates: */
	123	uint32_t pending_crtcs;
	124	wait_queue_head_t pending_crtcs_event;
	125
667ce33e RC	126	/* Registered address spaces.. currently this is fixed per # of
	127	* iommu's. Ie. one for display block and one for gpu block.
	128	* Eventually, to do per-process gpu pagetables, we'll want one
	129	* of these per-process.
	130	*/
	131	unsigned int num_aspaces;
	132	struct msm_gem_address_space *aspace[NUM_DOMAINS];
c8afe684	133
a8623918	134	unsigned int num_planes;
bc5289ee	135	struct drm_plane *planes[16];
a8623918	136
c8afe684 RC	137	unsigned int num_crtcs;
	138	struct drm_crtc *crtcs[8];
	139
	140	unsigned int num_encoders;
	141	struct drm_encoder *encoders[8];
	142
a3376e3e RC	143	unsigned int num_bridges;
	144	struct drm_bridge *bridges[8];
	145
c8afe684 RC	146	unsigned int num_connectors;
c8afe684 RC	147	struct drm_connector *connectors[8];
871d812a	148
12987781	149	/* Properties */
	150	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
	151
871d812a RC	152	/* VRAM carveout, used when no IOMMU: */
	153	struct {
	154	unsigned long size;
	155	dma_addr_t paddr;
	156	/* NOTE: mm managed at the page level, size is in # of pages
	157	* and position mm_node->start is in # of pages:
	158	*/
	159	struct drm_mm mm;
	160	} vram;
78b1d470	161
e1e9db2c	162	struct notifier_block vmap_notifier;
68209390 RC	163	struct shrinker shrinker;
68209390 RC	164
78b1d470	165	struct msm_vblank_ctrl vblank_ctrl;
d78d383a RC	166
	167	/* task holding struct_mutex.. currently only used in submit path
	168	* to detect and reject faults from copy_from_user() for submit
	169	* ioctl.
	170	*/
	171	struct task_struct *struct_mutex_task;
c8afe684 RC	172	};
	173
	174	struct msm_format {
	175	uint32_t pixel_format;
	176	};
	177
b4274fbe DV	178	int msm_atomic_check(struct drm_device *dev,
b4274fbe DV	179	struct drm_atomic_state *state);
cf3a7e4c	180	int msm_atomic_commit(struct drm_device *dev,
a3ccfb9f	181	struct drm_atomic_state *state, bool nonblock);
870d738a RC	182	struct drm_atomic_state msm_atomic_state_alloc(struct drm_device dev);
	183	void msm_atomic_state_clear(struct drm_atomic_state *state);
	184	void msm_atomic_state_free(struct drm_atomic_state *state);
cf3a7e4c	185
667ce33e RC	186	int msm_register_address_space(struct drm_device *dev,
	187	struct msm_gem_address_space *aspace);
	188
	189	void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
	190	struct msm_gem_vma vma, struct sg_table sgt);
	191	int msm_gem_map_vma(struct msm_gem_address_space *aspace,
	192	struct msm_gem_vma vma, struct sg_table sgt, int npages);
	193
ee546cd3 JC	194	void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
ee546cd3 JC	195
667ce33e RC	196	struct msm_gem_address_space *
	197	msm_gem_address_space_create(struct device dev, struct iommu_domain domain,
	198	const char *name);
c8afe684	199
40e6815b	200	void msm_gem_submit_free(struct msm_gem_submit *submit);
7198e6b0 RC	201	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	202	struct drm_file *file);
	203
68209390 RC	204	void msm_gem_shrinker_init(struct drm_device *dev);
	205	void msm_gem_shrinker_cleanup(struct drm_device *dev);
	206
77a147e7 DT	207	int msm_gem_mmap_obj(struct drm_gem_object *obj,
77a147e7 DT	208	struct vm_area_struct *vma);
c8afe684	209	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
11bac800	210	int msm_gem_fault(struct vm_fault *vmf);
c8afe684 RC	211	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
c8afe684 RC	212	int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
78babc16 RC	213	uint64_t *iova);
	214	int msm_gem_get_iova(struct drm_gem_object obj, int id, uint64_t iova);
	215	uint64_t msm_gem_iova(struct drm_gem_object *obj, int id);
05b84911 RC	216	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	217	void msm_gem_put_pages(struct drm_gem_object *obj);
c8afe684 RC	218	void msm_gem_put_iova(struct drm_gem_object *obj, int id);
	219	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
	220	struct drm_mode_create_dumb *args);
c8afe684 RC	221	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	222	uint32_t handle, uint64_t *offset);
05b84911 RC	223	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	224	void msm_gem_prime_vmap(struct drm_gem_object obj);
	225	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
77a147e7	226	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
43523eba	227	struct reservation_object msm_gem_prime_res_obj(struct drm_gem_object obj);
05b84911	228	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
b5e9c1a2	229	struct dma_buf_attachment attach, struct sg_table sg);
05b84911 RC	230	int msm_gem_prime_pin(struct drm_gem_object *obj);
05b84911 RC	231	void msm_gem_prime_unpin(struct drm_gem_object *obj);
18f23049 RC	232	void msm_gem_get_vaddr_locked(struct drm_gem_object obj);
	233	void msm_gem_get_vaddr(struct drm_gem_object obj);
	234	void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
	235	void msm_gem_put_vaddr(struct drm_gem_object *obj);
4cd33c48	236	int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
68209390	237	void msm_gem_purge(struct drm_gem_object *obj);
e1e9db2c	238	void msm_gem_vunmap(struct drm_gem_object *obj);
b6295f9a RC	239	int msm_gem_sync_object(struct drm_gem_object *obj,
b6295f9a RC	240	struct msm_fence_context *fctx, bool exclusive);
7198e6b0	241	void msm_gem_move_to_active(struct drm_gem_object *obj,
f54d1867	242	struct msm_gpu gpu, bool exclusive, struct dma_fence fence);
7198e6b0	243	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
ba00c3f2	244	int msm_gem_cpu_prep(struct drm_gem_object obj, uint32_t op, ktime_t timeout);
7198e6b0	245	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	246	void msm_gem_free_object(struct drm_gem_object *obj);
	247	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
	248	uint32_t size, uint32_t flags, uint32_t *handle);
	249	struct drm_gem_object msm_gem_new(struct drm_device dev,
	250	uint32_t size, uint32_t flags);
05b84911	251	struct drm_gem_object msm_gem_import(struct drm_device dev,
79f0e202	252	struct dma_buf dmabuf, struct sg_table sgt);
c8afe684	253
2638d90a RC	254	int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
	255	void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
	256	uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
c8afe684 RC	257	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
	258	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
	259	struct drm_framebuffer msm_framebuffer_init(struct drm_device dev,
1eb83451	260	const struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_object *bos);
c8afe684	261	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
1eb83451	262	struct drm_file file, const struct drm_mode_fb_cmd2 mode_cmd);
c8afe684 RC	263
c8afe684 RC	264	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
1aaa57f5	265	void msm_fbdev_free(struct drm_device *dev);
c8afe684	266
dada25bd	267	struct hdmi;
fcda50c8	268	int msm_hdmi_modeset_init(struct hdmi hdmi, struct drm_device dev,
067fef37	269	struct drm_encoder *encoder);
fcda50c8 AB	270	void __init msm_hdmi_register(void);
fcda50c8 AB	271	void __exit msm_hdmi_unregister(void);
c8afe684	272
00453981 HL	273	struct msm_edp;
	274	void __init msm_edp_register(void);
	275	void __exit msm_edp_unregister(void);
	276	int msm_edp_modeset_init(struct msm_edp edp, struct drm_device dev,
	277	struct drm_encoder *encoder);
	278
a689554b	279	struct msm_dsi;
a689554b HL	280	#ifdef CONFIG_DRM_MSM_DSI
	281	void __init msm_dsi_register(void);
	282	void __exit msm_dsi_unregister(void);
	283	int msm_dsi_modeset_init(struct msm_dsi msm_dsi, struct drm_device dev,
97e00119	284	struct drm_encoder *encoder);
a689554b HL	285	#else
	286	static inline void __init msm_dsi_register(void)
	287	{
	288	}
	289	static inline void __exit msm_dsi_unregister(void)
	290	{
	291	}
	292	static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
97e00119 AT	293	struct drm_device *dev,
97e00119 AT	294	struct drm_encoder *encoder)
a689554b HL	295	{
	296	return -EINVAL;
	297	}
	298	#endif
	299
1dd0a0b1 AT	300	void __init msm_mdp_register(void);
	301	void __exit msm_mdp_unregister(void);
	302
c8afe684 RC	303	#ifdef CONFIG_DEBUG_FS
	304	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	305	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	306	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
a7d3c950 RC	307	int msm_debugfs_late_init(struct drm_device *dev);
a7d3c950 RC	308	int msm_rd_debugfs_init(struct drm_minor *minor);
85eac470	309	void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
a7d3c950	310	void msm_rd_dump_submit(struct msm_gem_submit *submit);
70c70f09	311	int msm_perf_debugfs_init(struct drm_minor *minor);
85eac470	312	void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
a7d3c950 RC	313	#else
	314	static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
	315	static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
3a270e4d AB	316	static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
3a270e4d AB	317	static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
c8afe684 RC	318	#endif
c8afe684 RC	319
720c3bb8	320	struct clk msm_clk_get(struct platform_device pdev, const char *name);
c8afe684 RC	321	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	322	const char *dbgname);
	323	void msm_writel(u32 data, void __iomem *addr);
	324	u32 msm_readl(const void __iomem *addr);
	325
7ed216e5 RC	326	#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
7ed216e5 RC	327	#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
c8afe684 RC	328
	329	static inline int align_pitch(int width, int bpp)
	330	{
	331	int bytespp = (bpp + 7) / 8;
	332	/* adreno needs pitch aligned to 32 pixels: */
	333	return bytespp * ALIGN(width, 32);
	334	}
	335
	336	/* for the generated headers: */
	337	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	338	#define fui(x) ({BUG(); 0;})
	339	#define util_float_to_half(x) ({BUG(); 0;})
	340
c8afe684 RC	341
	342	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	343
	344	/* for conditionally setting boolean flag(s): */
	345	#define COND(bool, val) ((bool) ? (val) : 0)
	346
340ff410 RC	347	static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
	348	{
	349	ktime_t now = ktime_get();
	350	unsigned long remaining_jiffies;
	351
	352	if (ktime_compare(*timeout, now) < 0) {
	353	remaining_jiffies = 0;
	354	} else {
	355	ktime_t rem = ktime_sub(*timeout, now);
	356	struct timespec ts = ktime_to_timespec(rem);
	357	remaining_jiffies = timespec_to_jiffies(&ts);
	358	}
	359
	360	return remaining_jiffies;
	361	}
c8afe684 RC	362
c8afe684 RC	363	#endif /* __MSM_DRV_H__ */