[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / msm_drv.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/component.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/of_graph.h>
#include <linux/of_device.h>
#include <asm/sizes.h>

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;
struct msm_mdss;
struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;
struct msm_fence_context;
struct msm_fence_cb;
struct msm_gem_address_space;
struct msm_gem_vma;

struct msm_file_private {
	rwlock_t queuelock;
	struct list_head submitqueues;
	int queueid;
};

enum msm_mdp_plane_property {
	PLANE_PROP_ZPOS,
	PLANE_PROP_ALPHA,
	PLANE_PROP_PREMULTIPLIED,
	PLANE_PROP_MAX_NUM
};

struct msm_vblank_ctrl {
	struct work_struct work;
	struct list_head event_list;
	spinlock_t lock;
};

#define MSM_GPU_MAX_RINGS 4

struct msm_drm_private {

	struct drm_device *dev;

	struct msm_kms *kms;

	/* subordinate devices, if present: */
	struct platform_device *gpu_pdev;

	/* top level MDSS wrapper device (for MDP5 only) */
	struct msm_mdss *mdss;

	/* possibly this should be in the kms component, but it is
	 * shared by both mdp4 and mdp5..
	 */
	struct hdmi *hdmi;

	/* eDP is for mdp5 only, but kms has not been created
	 * when edp_bind() and edp_init() are called. Here is the only
	 * place to keep the edp instance.
	 */
	struct msm_edp *edp;

	/* DSI is shared by mdp4 and mdp5 */
	struct msm_dsi *dsi[2];

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;

	struct drm_fb_helper *fbdev;

	struct msm_rd_state *rd;       /* debugfs to dump all submits */
	struct msm_rd_state *hangrd;   /* debugfs to dump hanging submits */
	struct msm_perf_state *perf;

	/* list of GEM objects: */
	struct list_head inactive_list;

	struct workqueue_struct *wq;
	struct workqueue_struct *atomic_wq;

	/* crtcs pending async atomic updates: */
	uint32_t pending_crtcs;
	wait_queue_head_t pending_crtcs_event;

	unsigned int num_planes;
	struct drm_plane *planes[16];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[8];

	unsigned int num_encoders;
	struct drm_encoder *encoders[8];

	unsigned int num_bridges;
	struct drm_bridge *bridges[8];

	unsigned int num_connectors;
	struct drm_connector *connectors[8];

	/* Properties */
	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
		spinlock_t lock; /* Protects drm_mm node allocation/removal */
	} vram;

	struct notifier_block vmap_notifier;
	struct shrinker shrinker;

	struct msm_vblank_ctrl vblank_ctrl;
};

struct msm_format {
	uint32_t pixel_format;
};

int msm_atomic_commit(struct drm_device *dev,
		struct drm_atomic_state *state, bool nonblock);
struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
void msm_atomic_state_clear(struct drm_atomic_state *state);
void msm_atomic_state_free(struct drm_atomic_state *state);

void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, struct sg_table *sgt);
int msm_gem_map_vma(struct msm_gem_address_space *aspace,
		struct msm_gem_vma *vma, struct sg_table *sgt, int npages);

void msm_gem_address_space_put(struct msm_gem_address_space *aspace);

struct msm_gem_address_space *
msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
		const char *name);

void msm_gem_submit_free(struct msm_gem_submit *submit);
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

void msm_gem_shrinker_init(struct drm_device *dev);
void msm_gem_shrinker_cleanup(struct drm_device *dev);

int msm_gem_mmap_obj(struct drm_gem_object *obj,
			struct vm_area_struct *vma);
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
int msm_gem_fault(struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace, uint64_t *iova);
uint64_t msm_gem_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
void msm_gem_put_iova(struct drm_gem_object *obj,
		struct msm_gem_address_space *aspace);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		struct dma_buf_attachment *attach, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
void msm_gem_put_vaddr(struct drm_gem_object *obj);
int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
int msm_gem_sync_object(struct drm_gem_object *obj,
		struct msm_fence_context *fctx, bool exclusive);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
		uint32_t size, uint32_t flags);
void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
		uint32_t flags, struct msm_gem_address_space *aspace,
		struct drm_gem_object **bo, uint64_t *iova);
void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
		uint32_t flags, struct msm_gem_address_space *aspace,
		struct drm_gem_object **bo, uint64_t *iova);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		struct dma_buf *dmabuf, struct sg_table *sgt);

int msm_framebuffer_prepare(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace);
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace);
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
		struct msm_gem_address_space *aspace, int plane);
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
		int w, int h, int p, uint32_t format);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
void msm_fbdev_free(struct drm_device *dev);

struct hdmi;
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
		struct drm_encoder *encoder);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);

struct msm_edp;
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
		struct drm_encoder *encoder);

struct msm_dsi;
#ifdef CONFIG_DRM_MSM_DSI
void __init msm_dsi_register(void);
void __exit msm_dsi_unregister(void);
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
			 struct drm_encoder *encoder);
#else
static inline void __init msm_dsi_register(void)
{
}
static inline void __exit msm_dsi_unregister(void)
{
}
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
				       struct drm_device *dev,
				       struct drm_encoder *encoder)
{
	return -EINVAL;
}
#endif

void __init msm_mdp_register(void);
void __exit msm_mdp_unregister(void);

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
int msm_debugfs_late_init(struct drm_device *dev);
int msm_rd_debugfs_init(struct drm_minor *minor);
void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
		const char *fmt, ...);
int msm_perf_debugfs_init(struct drm_minor *minor);
void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
#else
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
		const char *fmt, ...) {}
static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
#endif

struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

struct msm_gpu_submitqueue;
int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
		u32 id);
int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
		u32 prio, u32 flags, u32 *id);
int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
void msm_submitqueue_close(struct msm_file_private *ctx);

void msm_submitqueue_destroy(struct kref *kref);


#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)

static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
{
	ktime_t now = ktime_get();
	unsigned long remaining_jiffies;

	if (ktime_compare(*timeout, now) < 0) {
		remaining_jiffies = 0;
	} else {
		ktime_t rem = ktime_sub(*timeout, now);
		struct timespec ts = ktime_to_timespec(rem);
		remaining_jiffies = timespec_to_jiffies(&ts);
	}

	return remaining_jiffies;
}

#endif /* __MSM_DRV_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRV_H__
	19	#define __MSM_DRV_H__
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/module.h>
060530f1	25	#include <linux/component.h>
c8afe684 RC	26	#include <linux/platform_device.h>
	27	#include <linux/pm.h>
	28	#include <linux/pm_runtime.h>
	29	#include <linux/slab.h>
	30	#include <linux/list.h>
	31	#include <linux/iommu.h>
	32	#include <linux/types.h>
3d6df062	33	#include <linux/of_graph.h>
e9fbdaf2	34	#include <linux/of_device.h>
c8afe684 RC	35	#include <asm/sizes.h>
c8afe684 RC	36
c8afe684	37	#include <drm/drmP.h>
cf3a7e4c RC	38	#include <drm/drm_atomic.h>
cf3a7e4c RC	39	#include <drm/drm_atomic_helper.h>
c8afe684	40	#include <drm/drm_crtc_helper.h>
cf3a7e4c	41	#include <drm/drm_plane_helper.h>
c8afe684	42	#include <drm/drm_fb_helper.h>
7198e6b0	43	#include <drm/msm_drm.h>
d9fc9413	44	#include <drm/drm_gem.h>
c8afe684 RC	45
c8afe684 RC	46	struct msm_kms;
7198e6b0	47	struct msm_gpu;
871d812a	48	struct msm_mmu;
990a4007	49	struct msm_mdss;
a7d3c950	50	struct msm_rd_state;
70c70f09	51	struct msm_perf_state;
a7d3c950	52	struct msm_gem_submit;
ca762a8a	53	struct msm_fence_context;
fde5de6c	54	struct msm_fence_cb;
667ce33e RC	55	struct msm_gem_address_space;
667ce33e RC	56	struct msm_gem_vma;
c8afe684	57
7198e6b0	58	struct msm_file_private {
f7de1545 JC	59	rwlock_t queuelock;
	60	struct list_head submitqueues;
	61	int queueid;
7198e6b0	62	};
c8afe684	63
12987781	64	enum msm_mdp_plane_property {
	65	PLANE_PROP_ZPOS,
	66	PLANE_PROP_ALPHA,
	67	PLANE_PROP_PREMULTIPLIED,
	68	PLANE_PROP_MAX_NUM
	69	};
	70
78b1d470 HL	71	struct msm_vblank_ctrl {
	72	struct work_struct work;
	73	struct list_head event_list;
	74	spinlock_t lock;
	75	};
	76
b1fc2839	77	#define MSM_GPU_MAX_RINGS 4
f97decac	78
c8afe684 RC	79	struct msm_drm_private {
c8afe684 RC	80
68209390 RC	81	struct drm_device *dev;
68209390 RC	82
c8afe684 RC	83	struct msm_kms *kms;
c8afe684 RC	84
060530f1	85	/* subordinate devices, if present: */
067fef37 RC	86	struct platform_device *gpu_pdev;
067fef37 RC	87
990a4007 AT	88	/* top level MDSS wrapper device (for MDP5 only) */
	89	struct msm_mdss *mdss;
	90
067fef37 RC	91	/* possibly this should be in the kms component, but it is
	92	* shared by both mdp4 and mdp5..
	93	*/
	94	struct hdmi *hdmi;
060530f1	95
ab5b0107 HL	96	/* eDP is for mdp5 only, but kms has not been created
	97	* when edp_bind() and edp_init() are called. Here is the only
	98	* place to keep the edp instance.
	99	*/
	100	struct msm_edp *edp;
	101
a689554b HL	102	/* DSI is shared by mdp4 and mdp5 */
	103	struct msm_dsi *dsi[2];
	104
7198e6b0 RC	105	/* when we have more than one 'msm_gpu' these need to be an array: */
	106	struct msm_gpu *gpu;
	107	struct msm_file_private *lastctx;
	108
c8afe684 RC	109	struct drm_fb_helper *fbdev;
c8afe684 RC	110
2165e2b9 RC	111	struct msm_rd_state rd; / debugfs to dump all submits */
2165e2b9 RC	112	struct msm_rd_state hangrd; / debugfs to dump hanging submits */
70c70f09	113	struct msm_perf_state *perf;
a7d3c950	114
c8afe684 RC	115	/* list of GEM objects: */
	116	struct list_head inactive_list;
	117
	118	struct workqueue_struct *wq;
ba00c3f2	119	struct workqueue_struct *atomic_wq;
c8afe684	120
f86afecf RC	121	/* crtcs pending async atomic updates: */
	122	uint32_t pending_crtcs;
	123	wait_queue_head_t pending_crtcs_event;
	124
a8623918	125	unsigned int num_planes;
bc5289ee	126	struct drm_plane *planes[16];
a8623918	127
c8afe684 RC	128	unsigned int num_crtcs;
	129	struct drm_crtc *crtcs[8];
	130
	131	unsigned int num_encoders;
	132	struct drm_encoder *encoders[8];
	133
a3376e3e RC	134	unsigned int num_bridges;
	135	struct drm_bridge *bridges[8];
	136
c8afe684 RC	137	unsigned int num_connectors;
c8afe684 RC	138	struct drm_connector *connectors[8];
871d812a	139
12987781	140	/* Properties */
	141	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
	142
871d812a RC	143	/* VRAM carveout, used when no IOMMU: */
	144	struct {
	145	unsigned long size;
	146	dma_addr_t paddr;
	147	/* NOTE: mm managed at the page level, size is in # of pages
	148	* and position mm_node->start is in # of pages:
	149	*/
	150	struct drm_mm mm;
0e08270a	151	spinlock_t lock; /* Protects drm_mm node allocation/removal */
871d812a	152	} vram;
78b1d470	153
e1e9db2c	154	struct notifier_block vmap_notifier;
68209390 RC	155	struct shrinker shrinker;
68209390 RC	156
78b1d470	157	struct msm_vblank_ctrl vblank_ctrl;
c8afe684 RC	158	};
	159
	160	struct msm_format {
	161	uint32_t pixel_format;
	162	};
	163
cf3a7e4c	164	int msm_atomic_commit(struct drm_device *dev,
a3ccfb9f	165	struct drm_atomic_state *state, bool nonblock);
870d738a RC	166	struct drm_atomic_state msm_atomic_state_alloc(struct drm_device dev);
	167	void msm_atomic_state_clear(struct drm_atomic_state *state);
	168	void msm_atomic_state_free(struct drm_atomic_state *state);
cf3a7e4c	169
667ce33e RC	170	void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
	171	struct msm_gem_vma vma, struct sg_table sgt);
	172	int msm_gem_map_vma(struct msm_gem_address_space *aspace,
	173	struct msm_gem_vma vma, struct sg_table sgt, int npages);
	174
ee546cd3 JC	175	void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
ee546cd3 JC	176
667ce33e RC	177	struct msm_gem_address_space *
	178	msm_gem_address_space_create(struct device dev, struct iommu_domain domain,
	179	const char *name);
c8afe684	180
40e6815b	181	void msm_gem_submit_free(struct msm_gem_submit *submit);
7198e6b0 RC	182	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	183	struct drm_file *file);
	184
68209390 RC	185	void msm_gem_shrinker_init(struct drm_device *dev);
	186	void msm_gem_shrinker_cleanup(struct drm_device *dev);
	187
77a147e7 DT	188	int msm_gem_mmap_obj(struct drm_gem_object *obj,
77a147e7 DT	189	struct vm_area_struct *vma);
c8afe684	190	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
11bac800	191	int msm_gem_fault(struct vm_fault *vmf);
c8afe684	192	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
8bdcd949 RC	193	int msm_gem_get_iova(struct drm_gem_object *obj,
	194	struct msm_gem_address_space aspace, uint64_t iova);
	195	uint64_t msm_gem_iova(struct drm_gem_object *obj,
	196	struct msm_gem_address_space *aspace);
05b84911 RC	197	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	198	void msm_gem_put_pages(struct drm_gem_object *obj);
8bdcd949 RC	199	void msm_gem_put_iova(struct drm_gem_object *obj,
8bdcd949 RC	200	struct msm_gem_address_space *aspace);
c8afe684 RC	201	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
c8afe684 RC	202	struct drm_mode_create_dumb *args);
c8afe684 RC	203	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	204	uint32_t handle, uint64_t *offset);
05b84911 RC	205	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	206	void msm_gem_prime_vmap(struct drm_gem_object obj);
	207	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
77a147e7	208	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
43523eba	209	struct reservation_object msm_gem_prime_res_obj(struct drm_gem_object obj);
05b84911	210	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
b5e9c1a2	211	struct dma_buf_attachment attach, struct sg_table sg);
05b84911 RC	212	int msm_gem_prime_pin(struct drm_gem_object *obj);
05b84911 RC	213	void msm_gem_prime_unpin(struct drm_gem_object *obj);
18f23049	214	void msm_gem_get_vaddr(struct drm_gem_object obj);
fad33f4b	215	void msm_gem_get_vaddr_active(struct drm_gem_object obj);
18f23049	216	void msm_gem_put_vaddr(struct drm_gem_object *obj);
4cd33c48	217	int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
b6295f9a RC	218	int msm_gem_sync_object(struct drm_gem_object *obj,
b6295f9a RC	219	struct msm_fence_context *fctx, bool exclusive);
7198e6b0	220	void msm_gem_move_to_active(struct drm_gem_object *obj,
f54d1867	221	struct msm_gpu gpu, bool exclusive, struct dma_fence fence);
7198e6b0	222	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
ba00c3f2	223	int msm_gem_cpu_prep(struct drm_gem_object obj, uint32_t op, ktime_t timeout);
7198e6b0	224	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	225	void msm_gem_free_object(struct drm_gem_object *obj);
	226	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
	227	uint32_t size, uint32_t flags, uint32_t *handle);
	228	struct drm_gem_object msm_gem_new(struct drm_device dev,
	229	uint32_t size, uint32_t flags);
0e08270a SS	230	struct drm_gem_object msm_gem_new_locked(struct drm_device dev,
0e08270a SS	231	uint32_t size, uint32_t flags);
8223286d JC	232	void msm_gem_kernel_new(struct drm_device dev, uint32_t size,
	233	uint32_t flags, struct msm_gem_address_space *aspace,
	234	struct drm_gem_object *bo, uint64_t iova);
	235	void msm_gem_kernel_new_locked(struct drm_device dev, uint32_t size,
	236	uint32_t flags, struct msm_gem_address_space *aspace,
	237	struct drm_gem_object *bo, uint64_t iova);
05b84911	238	struct drm_gem_object msm_gem_import(struct drm_device dev,
79f0e202	239	struct dma_buf dmabuf, struct sg_table sgt);
c8afe684	240
8bdcd949 RC	241	int msm_framebuffer_prepare(struct drm_framebuffer *fb,
	242	struct msm_gem_address_space *aspace);
	243	void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
	244	struct msm_gem_address_space *aspace);
	245	uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
	246	struct msm_gem_address_space *aspace, int plane);
c8afe684 RC	247	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
c8afe684 RC	248	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
c8afe684	249	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
1eb83451	250	struct drm_file file, const struct drm_mode_fb_cmd2 mode_cmd);
466e5606 RC	251	struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
466e5606 RC	252	int w, int h, int p, uint32_t format);
c8afe684 RC	253
c8afe684 RC	254	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
1aaa57f5	255	void msm_fbdev_free(struct drm_device *dev);
c8afe684	256
dada25bd	257	struct hdmi;
fcda50c8	258	int msm_hdmi_modeset_init(struct hdmi hdmi, struct drm_device dev,
067fef37	259	struct drm_encoder *encoder);
fcda50c8 AB	260	void __init msm_hdmi_register(void);
fcda50c8 AB	261	void __exit msm_hdmi_unregister(void);
c8afe684	262
00453981 HL	263	struct msm_edp;
	264	void __init msm_edp_register(void);
	265	void __exit msm_edp_unregister(void);
	266	int msm_edp_modeset_init(struct msm_edp edp, struct drm_device dev,
	267	struct drm_encoder *encoder);
	268
a689554b	269	struct msm_dsi;
a689554b HL	270	#ifdef CONFIG_DRM_MSM_DSI
	271	void __init msm_dsi_register(void);
	272	void __exit msm_dsi_unregister(void);
	273	int msm_dsi_modeset_init(struct msm_dsi msm_dsi, struct drm_device dev,
97e00119	274	struct drm_encoder *encoder);
a689554b HL	275	#else
	276	static inline void __init msm_dsi_register(void)
	277	{
	278	}
	279	static inline void __exit msm_dsi_unregister(void)
	280	{
	281	}
	282	static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
97e00119 AT	283	struct drm_device *dev,
97e00119 AT	284	struct drm_encoder *encoder)
a689554b HL	285	{
	286	return -EINVAL;
	287	}
	288	#endif
	289
1dd0a0b1 AT	290	void __init msm_mdp_register(void);
	291	void __exit msm_mdp_unregister(void);
	292
c8afe684 RC	293	#ifdef CONFIG_DEBUG_FS
	294	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	295	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	296	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
a7d3c950 RC	297	int msm_debugfs_late_init(struct drm_device *dev);
a7d3c950 RC	298	int msm_rd_debugfs_init(struct drm_minor *minor);
85eac470	299	void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
998b9a58 RC	300	void msm_rd_dump_submit(struct msm_rd_state rd, struct msm_gem_submit submit,
998b9a58 RC	301	const char *fmt, ...);
70c70f09	302	int msm_perf_debugfs_init(struct drm_minor *minor);
85eac470	303	void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
a7d3c950 RC	304	#else
a7d3c950 RC	305	static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
f2d9ece7 AB	306	static inline void msm_rd_dump_submit(struct msm_rd_state rd, struct msm_gem_submit submit,
f2d9ece7 AB	307	const char *fmt, ...) {}
3a270e4d AB	308	static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
3a270e4d AB	309	static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
c8afe684 RC	310	#endif
c8afe684 RC	311
720c3bb8	312	struct clk msm_clk_get(struct platform_device pdev, const char *name);
c8afe684 RC	313	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	314	const char *dbgname);
	315	void msm_writel(u32 data, void __iomem *addr);
	316	u32 msm_readl(const void __iomem *addr);
	317
f7de1545	318	struct msm_gpu_submitqueue;
f97decac	319	int msm_submitqueue_init(struct drm_device drm, struct msm_file_private ctx);
f7de1545 JC	320	struct msm_gpu_submitqueue msm_submitqueue_get(struct msm_file_private ctx,
f7de1545 JC	321	u32 id);
f97decac JC	322	int msm_submitqueue_create(struct drm_device drm, struct msm_file_private ctx,
f97decac JC	323	u32 prio, u32 flags, u32 *id);
f7de1545 JC	324	int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
	325	void msm_submitqueue_close(struct msm_file_private *ctx);
	326
	327	void msm_submitqueue_destroy(struct kref *kref);
	328
	329
7ed216e5 RC	330	#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
7ed216e5 RC	331	#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
c8afe684 RC	332
	333	static inline int align_pitch(int width, int bpp)
	334	{
	335	int bytespp = (bpp + 7) / 8;
	336	/* adreno needs pitch aligned to 32 pixels: */
	337	return bytespp * ALIGN(width, 32);
	338	}
	339
	340	/* for the generated headers: */
	341	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	342	#define fui(x) ({BUG(); 0;})
	343	#define util_float_to_half(x) ({BUG(); 0;})
	344
c8afe684 RC	345
	346	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	347
	348	/* for conditionally setting boolean flag(s): */
	349	#define COND(bool, val) ((bool) ? (val) : 0)
	350
340ff410 RC	351	static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
	352	{
	353	ktime_t now = ktime_get();
	354	unsigned long remaining_jiffies;
	355
	356	if (ktime_compare(*timeout, now) < 0) {
	357	remaining_jiffies = 0;
	358	} else {
	359	ktime_t rem = ktime_sub(*timeout, now);
	360	struct timespec ts = ktime_to_timespec(rem);
	361	remaining_jiffies = timespec_to_jiffies(&ts);
	362	}
	363
	364	return remaining_jiffies;
	365	}
c8afe684 RC	366
c8afe684 RC	367	#endif /* __MSM_DRV_H__ */