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1 | /* |
2 | * Copyright (C) 2013-2016 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
f54d1867 | 18 | #include <linux/dma-fence.h> |
ca762a8a | 19 | |
fde5de6c RC |
20 | #include "msm_drv.h" |
21 | #include "msm_fence.h" | |
fde5de6c | 22 | |
ca762a8a RC |
23 | |
24 | struct msm_fence_context * | |
25 | msm_fence_context_alloc(struct drm_device *dev, const char *name) | |
fde5de6c | 26 | { |
ca762a8a RC |
27 | struct msm_fence_context *fctx; |
28 | ||
29 | fctx = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
30 | if (!fctx) | |
31 | return ERR_PTR(-ENOMEM); | |
32 | ||
33 | fctx->dev = dev; | |
34 | fctx->name = name; | |
f54d1867 | 35 | fctx->context = dma_fence_context_alloc(1); |
ca762a8a | 36 | init_waitqueue_head(&fctx->event); |
b6295f9a | 37 | spin_lock_init(&fctx->spinlock); |
ca762a8a RC |
38 | |
39 | return fctx; | |
fde5de6c RC |
40 | } |
41 | ||
ca762a8a | 42 | void msm_fence_context_free(struct msm_fence_context *fctx) |
fde5de6c | 43 | { |
ca762a8a RC |
44 | kfree(fctx); |
45 | } | |
46 | ||
47 | static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence) | |
48 | { | |
49 | return (int32_t)(fctx->completed_fence - fence) >= 0; | |
50 | } | |
fde5de6c | 51 | |
b6295f9a | 52 | /* legacy path for WAIT_FENCE ioctl: */ |
ca762a8a RC |
53 | int msm_wait_fence(struct msm_fence_context *fctx, uint32_t fence, |
54 | ktime_t *timeout, bool interruptible) | |
55 | { | |
56 | int ret; | |
fde5de6c | 57 | |
ca762a8a RC |
58 | if (fence > fctx->last_fence) { |
59 | DRM_ERROR("%s: waiting on invalid fence: %u (of %u)\n", | |
60 | fctx->name, fence, fctx->last_fence); | |
fde5de6c RC |
61 | return -EINVAL; |
62 | } | |
63 | ||
64 | if (!timeout) { | |
65 | /* no-wait: */ | |
ca762a8a | 66 | ret = fence_completed(fctx, fence) ? 0 : -EBUSY; |
fde5de6c | 67 | } else { |
340ff410 | 68 | unsigned long remaining_jiffies = timeout_to_jiffies(timeout); |
fde5de6c RC |
69 | |
70 | if (interruptible) | |
ca762a8a RC |
71 | ret = wait_event_interruptible_timeout(fctx->event, |
72 | fence_completed(fctx, fence), | |
fde5de6c RC |
73 | remaining_jiffies); |
74 | else | |
ca762a8a RC |
75 | ret = wait_event_timeout(fctx->event, |
76 | fence_completed(fctx, fence), | |
fde5de6c RC |
77 | remaining_jiffies); |
78 | ||
79 | if (ret == 0) { | |
80 | DBG("timeout waiting for fence: %u (completed: %u)", | |
ca762a8a | 81 | fence, fctx->completed_fence); |
fde5de6c RC |
82 | ret = -ETIMEDOUT; |
83 | } else if (ret != -ERESTARTSYS) { | |
84 | ret = 0; | |
85 | } | |
86 | } | |
87 | ||
88 | return ret; | |
89 | } | |
90 | ||
fde5de6c | 91 | /* called from workqueue */ |
ca762a8a | 92 | void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence) |
fde5de6c | 93 | { |
b6295f9a | 94 | spin_lock(&fctx->spinlock); |
ca762a8a | 95 | fctx->completed_fence = max(fence, fctx->completed_fence); |
b6295f9a | 96 | spin_unlock(&fctx->spinlock); |
fde5de6c | 97 | |
ca762a8a | 98 | wake_up_all(&fctx->event); |
fde5de6c | 99 | } |
b6295f9a RC |
100 | |
101 | struct msm_fence { | |
102 | struct msm_fence_context *fctx; | |
f54d1867 | 103 | struct dma_fence base; |
b6295f9a RC |
104 | }; |
105 | ||
f54d1867 | 106 | static inline struct msm_fence *to_msm_fence(struct dma_fence *fence) |
b6295f9a RC |
107 | { |
108 | return container_of(fence, struct msm_fence, base); | |
109 | } | |
110 | ||
f54d1867 | 111 | static const char *msm_fence_get_driver_name(struct dma_fence *fence) |
b6295f9a RC |
112 | { |
113 | return "msm"; | |
114 | } | |
115 | ||
f54d1867 | 116 | static const char *msm_fence_get_timeline_name(struct dma_fence *fence) |
b6295f9a RC |
117 | { |
118 | struct msm_fence *f = to_msm_fence(fence); | |
119 | return f->fctx->name; | |
120 | } | |
121 | ||
f54d1867 | 122 | static bool msm_fence_enable_signaling(struct dma_fence *fence) |
b6295f9a RC |
123 | { |
124 | return true; | |
125 | } | |
126 | ||
f54d1867 | 127 | static bool msm_fence_signaled(struct dma_fence *fence) |
b6295f9a RC |
128 | { |
129 | struct msm_fence *f = to_msm_fence(fence); | |
130 | return fence_completed(f->fctx, f->base.seqno); | |
131 | } | |
132 | ||
f54d1867 | 133 | static void msm_fence_release(struct dma_fence *fence) |
b6295f9a RC |
134 | { |
135 | struct msm_fence *f = to_msm_fence(fence); | |
136 | kfree_rcu(f, base.rcu); | |
137 | } | |
138 | ||
f54d1867 | 139 | static const struct dma_fence_ops msm_fence_ops = { |
b6295f9a RC |
140 | .get_driver_name = msm_fence_get_driver_name, |
141 | .get_timeline_name = msm_fence_get_timeline_name, | |
142 | .enable_signaling = msm_fence_enable_signaling, | |
143 | .signaled = msm_fence_signaled, | |
f54d1867 | 144 | .wait = dma_fence_default_wait, |
b6295f9a RC |
145 | .release = msm_fence_release, |
146 | }; | |
147 | ||
f54d1867 | 148 | struct dma_fence * |
b6295f9a RC |
149 | msm_fence_alloc(struct msm_fence_context *fctx) |
150 | { | |
151 | struct msm_fence *f; | |
152 | ||
153 | f = kzalloc(sizeof(*f), GFP_KERNEL); | |
154 | if (!f) | |
155 | return ERR_PTR(-ENOMEM); | |
156 | ||
157 | f->fctx = fctx; | |
158 | ||
f54d1867 CW |
159 | dma_fence_init(&f->base, &msm_fence_ops, &fctx->spinlock, |
160 | fctx->context, ++fctx->last_fence); | |
b6295f9a RC |
161 | |
162 | return &f->base; | |
163 | } |