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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7198e6b0 RC |
2 | /* |
3 | * Copyright (C) 2013 Red Hat | |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
7198e6b0 RC |
5 | */ |
6 | ||
7 | #include "msm_gpu.h" | |
8 | #include "msm_gem.h" | |
871d812a | 9 | #include "msm_mmu.h" |
fde5de6c | 10 | #include "msm_fence.h" |
4241db42 | 11 | #include "msm_gpu_trace.h" |
c2052a4e | 12 | #include "adreno/adreno_gpu.h" |
7198e6b0 | 13 | |
c0fec7f5 | 14 | #include <generated/utsrelease.h> |
18bb8a6c | 15 | #include <linux/string_helpers.h> |
f91c14ab JC |
16 | #include <linux/pm_opp.h> |
17 | #include <linux/devfreq.h> | |
c0fec7f5 | 18 | #include <linux/devcoredump.h> |
7198e6b0 RC |
19 | |
20 | /* | |
21 | * Power Management: | |
22 | */ | |
23 | ||
f91c14ab JC |
24 | static int msm_devfreq_target(struct device *dev, unsigned long *freq, |
25 | u32 flags) | |
26 | { | |
27 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
28 | struct dev_pm_opp *opp; | |
29 | ||
30 | opp = devfreq_recommended_opp(dev, freq, flags); | |
31 | ||
32 | if (IS_ERR(opp)) | |
33 | return PTR_ERR(opp); | |
34 | ||
de0a3d09 SM |
35 | if (gpu->funcs->gpu_set_freq) |
36 | gpu->funcs->gpu_set_freq(gpu, (u64)*freq); | |
37 | else | |
38 | clk_set_rate(gpu->core_clk, *freq); | |
39 | ||
f91c14ab JC |
40 | dev_pm_opp_put(opp); |
41 | ||
42 | return 0; | |
43 | } | |
44 | ||
45 | static int msm_devfreq_get_dev_status(struct device *dev, | |
46 | struct devfreq_dev_status *status) | |
47 | { | |
48 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
f91c14ab JC |
49 | ktime_t time; |
50 | ||
de0a3d09 SM |
51 | if (gpu->funcs->gpu_get_freq) |
52 | status->current_frequency = gpu->funcs->gpu_get_freq(gpu); | |
53 | else | |
54 | status->current_frequency = clk_get_rate(gpu->core_clk); | |
f91c14ab | 55 | |
de0a3d09 | 56 | status->busy_time = gpu->funcs->gpu_busy(gpu); |
f91c14ab JC |
57 | |
58 | time = ktime_get(); | |
59 | status->total_time = ktime_us_delta(time, gpu->devfreq.time); | |
60 | gpu->devfreq.time = time; | |
61 | ||
62 | return 0; | |
63 | } | |
64 | ||
65 | static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) | |
66 | { | |
67 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
68 | ||
de0a3d09 SM |
69 | if (gpu->funcs->gpu_get_freq) |
70 | *freq = gpu->funcs->gpu_get_freq(gpu); | |
71 | else | |
72 | *freq = clk_get_rate(gpu->core_clk); | |
f91c14ab JC |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static struct devfreq_dev_profile msm_devfreq_profile = { | |
78 | .polling_ms = 10, | |
79 | .target = msm_devfreq_target, | |
80 | .get_dev_status = msm_devfreq_get_dev_status, | |
81 | .get_cur_freq = msm_devfreq_get_cur_freq, | |
82 | }; | |
83 | ||
84 | static void msm_devfreq_init(struct msm_gpu *gpu) | |
85 | { | |
86 | /* We need target support to do devfreq */ | |
de0a3d09 | 87 | if (!gpu->funcs->gpu_busy) |
f91c14ab JC |
88 | return; |
89 | ||
90 | msm_devfreq_profile.initial_freq = gpu->fast_rate; | |
91 | ||
92 | /* | |
93 | * Don't set the freq_table or max_state and let devfreq build the table | |
94 | * from OPP | |
95 | */ | |
96 | ||
97 | gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev, | |
98 | &msm_devfreq_profile, "simple_ondemand", NULL); | |
99 | ||
100 | if (IS_ERR(gpu->devfreq.devfreq)) { | |
6a41da17 | 101 | DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n"); |
f91c14ab JC |
102 | gpu->devfreq.devfreq = NULL; |
103 | } | |
d3fa91c9 SM |
104 | |
105 | devfreq_suspend_device(gpu->devfreq.devfreq); | |
f91c14ab JC |
106 | } |
107 | ||
7198e6b0 RC |
108 | static int enable_pwrrail(struct msm_gpu *gpu) |
109 | { | |
110 | struct drm_device *dev = gpu->dev; | |
111 | int ret = 0; | |
112 | ||
113 | if (gpu->gpu_reg) { | |
114 | ret = regulator_enable(gpu->gpu_reg); | |
115 | if (ret) { | |
6a41da17 | 116 | DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); |
7198e6b0 RC |
117 | return ret; |
118 | } | |
119 | } | |
120 | ||
121 | if (gpu->gpu_cx) { | |
122 | ret = regulator_enable(gpu->gpu_cx); | |
123 | if (ret) { | |
6a41da17 | 124 | DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); |
7198e6b0 RC |
125 | return ret; |
126 | } | |
127 | } | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
132 | static int disable_pwrrail(struct msm_gpu *gpu) | |
133 | { | |
134 | if (gpu->gpu_cx) | |
135 | regulator_disable(gpu->gpu_cx); | |
136 | if (gpu->gpu_reg) | |
137 | regulator_disable(gpu->gpu_reg); | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static int enable_clk(struct msm_gpu *gpu) | |
142 | { | |
98db803f JC |
143 | if (gpu->core_clk && gpu->fast_rate) |
144 | clk_set_rate(gpu->core_clk, gpu->fast_rate); | |
7198e6b0 | 145 | |
b5f103ab | 146 | /* Set the RBBM timer rate to 19.2Mhz */ |
98db803f JC |
147 | if (gpu->rbbmtimer_clk) |
148 | clk_set_rate(gpu->rbbmtimer_clk, 19200000); | |
b5f103ab | 149 | |
8e54eea5 | 150 | return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); |
7198e6b0 RC |
151 | } |
152 | ||
153 | static int disable_clk(struct msm_gpu *gpu) | |
154 | { | |
8e54eea5 | 155 | clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); |
7198e6b0 | 156 | |
bf5af4ae JC |
157 | /* |
158 | * Set the clock to a deliberately low rate. On older targets the clock | |
159 | * speed had to be non zero to avoid problems. On newer targets this | |
160 | * will be rounded down to zero anyway so it all works out. | |
161 | */ | |
98db803f JC |
162 | if (gpu->core_clk) |
163 | clk_set_rate(gpu->core_clk, 27000000); | |
89d777a5 | 164 | |
98db803f JC |
165 | if (gpu->rbbmtimer_clk) |
166 | clk_set_rate(gpu->rbbmtimer_clk, 0); | |
b5f103ab | 167 | |
7198e6b0 RC |
168 | return 0; |
169 | } | |
170 | ||
171 | static int enable_axi(struct msm_gpu *gpu) | |
172 | { | |
173 | if (gpu->ebi1_clk) | |
174 | clk_prepare_enable(gpu->ebi1_clk); | |
7198e6b0 RC |
175 | return 0; |
176 | } | |
177 | ||
178 | static int disable_axi(struct msm_gpu *gpu) | |
179 | { | |
180 | if (gpu->ebi1_clk) | |
181 | clk_disable_unprepare(gpu->ebi1_clk); | |
7198e6b0 RC |
182 | return 0; |
183 | } | |
184 | ||
de0a3d09 SM |
185 | void msm_gpu_resume_devfreq(struct msm_gpu *gpu) |
186 | { | |
187 | gpu->devfreq.busy_cycles = 0; | |
188 | gpu->devfreq.time = ktime_get(); | |
189 | ||
190 | devfreq_resume_device(gpu->devfreq.devfreq); | |
191 | } | |
192 | ||
7198e6b0 RC |
193 | int msm_gpu_pm_resume(struct msm_gpu *gpu) |
194 | { | |
195 | int ret; | |
196 | ||
eeb75474 | 197 | DBG("%s", gpu->name); |
7198e6b0 RC |
198 | |
199 | ret = enable_pwrrail(gpu); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
203 | ret = enable_clk(gpu); | |
204 | if (ret) | |
205 | return ret; | |
206 | ||
207 | ret = enable_axi(gpu); | |
208 | if (ret) | |
209 | return ret; | |
210 | ||
de0a3d09 | 211 | msm_gpu_resume_devfreq(gpu); |
f91c14ab | 212 | |
eeb75474 RC |
213 | gpu->needs_hw_init = true; |
214 | ||
7198e6b0 RC |
215 | return 0; |
216 | } | |
217 | ||
218 | int msm_gpu_pm_suspend(struct msm_gpu *gpu) | |
219 | { | |
220 | int ret; | |
221 | ||
eeb75474 | 222 | DBG("%s", gpu->name); |
7198e6b0 | 223 | |
de0a3d09 | 224 | devfreq_suspend_device(gpu->devfreq.devfreq); |
f91c14ab | 225 | |
7198e6b0 RC |
226 | ret = disable_axi(gpu); |
227 | if (ret) | |
228 | return ret; | |
229 | ||
230 | ret = disable_clk(gpu); | |
231 | if (ret) | |
232 | return ret; | |
233 | ||
234 | ret = disable_pwrrail(gpu); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
eeb75474 | 241 | int msm_gpu_hw_init(struct msm_gpu *gpu) |
37d77c3a | 242 | { |
eeb75474 | 243 | int ret; |
37d77c3a | 244 | |
cb1e3818 RC |
245 | WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex)); |
246 | ||
eeb75474 RC |
247 | if (!gpu->needs_hw_init) |
248 | return 0; | |
37d77c3a | 249 | |
eeb75474 RC |
250 | disable_irq(gpu->irq); |
251 | ret = gpu->funcs->hw_init(gpu); | |
252 | if (!ret) | |
253 | gpu->needs_hw_init = false; | |
254 | enable_irq(gpu->irq); | |
37d77c3a | 255 | |
eeb75474 | 256 | return ret; |
37d77c3a RC |
257 | } |
258 | ||
c0fec7f5 JC |
259 | #ifdef CONFIG_DEV_COREDUMP |
260 | static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, | |
261 | size_t count, void *data, size_t datalen) | |
262 | { | |
263 | struct msm_gpu *gpu = data; | |
264 | struct drm_print_iterator iter; | |
265 | struct drm_printer p; | |
266 | struct msm_gpu_state *state; | |
267 | ||
268 | state = msm_gpu_crashstate_get(gpu); | |
269 | if (!state) | |
270 | return 0; | |
271 | ||
272 | iter.data = buffer; | |
273 | iter.offset = 0; | |
274 | iter.start = offset; | |
275 | iter.remain = count; | |
276 | ||
277 | p = drm_coredump_printer(&iter); | |
278 | ||
279 | drm_printf(&p, "---\n"); | |
280 | drm_printf(&p, "kernel: " UTS_RELEASE "\n"); | |
281 | drm_printf(&p, "module: " KBUILD_MODNAME "\n"); | |
3530a17f AB |
282 | drm_printf(&p, "time: %lld.%09ld\n", |
283 | state->time.tv_sec, state->time.tv_nsec); | |
c0fec7f5 JC |
284 | if (state->comm) |
285 | drm_printf(&p, "comm: %s\n", state->comm); | |
286 | if (state->cmd) | |
287 | drm_printf(&p, "cmdline: %s\n", state->cmd); | |
288 | ||
289 | gpu->funcs->show(gpu, state, &p); | |
290 | ||
291 | msm_gpu_crashstate_put(gpu); | |
292 | ||
293 | return count - iter.remain; | |
294 | } | |
295 | ||
296 | static void msm_gpu_devcoredump_free(void *data) | |
297 | { | |
298 | struct msm_gpu *gpu = data; | |
299 | ||
300 | msm_gpu_crashstate_put(gpu); | |
301 | } | |
302 | ||
cdb95931 JC |
303 | static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, |
304 | struct msm_gem_object *obj, u64 iova, u32 flags) | |
305 | { | |
306 | struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; | |
307 | ||
308 | /* Don't record write only objects */ | |
cdb95931 JC |
309 | state_bo->size = obj->base.size; |
310 | state_bo->iova = iova; | |
311 | ||
896a248a JC |
312 | /* Only store data for non imported buffer objects marked for read */ |
313 | if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) { | |
cdb95931 JC |
314 | void *ptr; |
315 | ||
316 | state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); | |
317 | if (!state_bo->data) | |
896a248a | 318 | goto out; |
cdb95931 JC |
319 | |
320 | ptr = msm_gem_get_vaddr_active(&obj->base); | |
321 | if (IS_ERR(ptr)) { | |
322 | kvfree(state_bo->data); | |
896a248a JC |
323 | state_bo->data = NULL; |
324 | goto out; | |
cdb95931 JC |
325 | } |
326 | ||
327 | memcpy(state_bo->data, ptr, obj->base.size); | |
328 | msm_gem_put_vaddr(&obj->base); | |
329 | } | |
896a248a | 330 | out: |
cdb95931 JC |
331 | state->nr_bos++; |
332 | } | |
333 | ||
334 | static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, | |
335 | struct msm_gem_submit *submit, char *comm, char *cmd) | |
c0fec7f5 JC |
336 | { |
337 | struct msm_gpu_state *state; | |
338 | ||
4f3a31a8 SM |
339 | /* Check if the target supports capturing crash state */ |
340 | if (!gpu->funcs->gpu_state_get) | |
341 | return; | |
342 | ||
c0fec7f5 JC |
343 | /* Only save one crash state at a time */ |
344 | if (gpu->crashstate) | |
345 | return; | |
346 | ||
347 | state = gpu->funcs->gpu_state_get(gpu); | |
348 | if (IS_ERR_OR_NULL(state)) | |
349 | return; | |
350 | ||
351 | /* Fill in the additional crash state information */ | |
352 | state->comm = kstrdup(comm, GFP_KERNEL); | |
353 | state->cmd = kstrdup(cmd, GFP_KERNEL); | |
354 | ||
cdb95931 JC |
355 | if (submit) { |
356 | int i; | |
357 | ||
896a248a | 358 | state->bos = kcalloc(submit->nr_cmds, |
cdb95931 JC |
359 | sizeof(struct msm_gpu_state_bo), GFP_KERNEL); |
360 | ||
896a248a JC |
361 | for (i = 0; state->bos && i < submit->nr_cmds; i++) { |
362 | int idx = submit->cmd[i].idx; | |
363 | ||
364 | msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj, | |
365 | submit->bos[idx].iova, submit->bos[idx].flags); | |
366 | } | |
cdb95931 JC |
367 | } |
368 | ||
c0fec7f5 JC |
369 | /* Set the active crash state to be dumped on failure */ |
370 | gpu->crashstate = state; | |
371 | ||
372 | /* FIXME: Release the crashstate if this errors out? */ | |
373 | dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, | |
374 | msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); | |
375 | } | |
376 | #else | |
6969019f AR |
377 | static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, |
378 | struct msm_gem_submit *submit, char *comm, char *cmd) | |
c0fec7f5 JC |
379 | { |
380 | } | |
381 | #endif | |
382 | ||
bd6f82d8 RC |
383 | /* |
384 | * Hangcheck detection for locked gpu: | |
385 | */ | |
386 | ||
f97decac JC |
387 | static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, |
388 | uint32_t fence) | |
389 | { | |
390 | struct msm_gem_submit *submit; | |
391 | ||
392 | list_for_each_entry(submit, &ring->submits, node) { | |
393 | if (submit->seqno > fence) | |
394 | break; | |
395 | ||
396 | msm_update_fence(submit->ring->fctx, | |
397 | submit->fence->seqno); | |
398 | } | |
399 | } | |
400 | ||
18bb8a6c RC |
401 | static struct msm_gem_submit * |
402 | find_submit(struct msm_ringbuffer *ring, uint32_t fence) | |
403 | { | |
404 | struct msm_gem_submit *submit; | |
405 | ||
406 | WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex)); | |
407 | ||
408 | list_for_each_entry(submit, &ring->submits, node) | |
409 | if (submit->seqno == fence) | |
410 | return submit; | |
411 | ||
412 | return NULL; | |
413 | } | |
414 | ||
b6295f9a | 415 | static void retire_submits(struct msm_gpu *gpu); |
1a370be9 | 416 | |
bd6f82d8 RC |
417 | static void recover_worker(struct work_struct *work) |
418 | { | |
419 | struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); | |
420 | struct drm_device *dev = gpu->dev; | |
96169f4e | 421 | struct msm_drm_private *priv = dev->dev_private; |
4816b626 | 422 | struct msm_gem_submit *submit; |
f97decac | 423 | struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); |
65a3c274 | 424 | char *comm = NULL, *cmd = NULL; |
f97decac JC |
425 | int i; |
426 | ||
bd6f82d8 | 427 | mutex_lock(&dev->struct_mutex); |
1a370be9 | 428 | |
6a41da17 | 429 | DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); |
f97decac | 430 | |
96169f4e | 431 | submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); |
18bb8a6c RC |
432 | if (submit) { |
433 | struct task_struct *task; | |
434 | ||
b0fb6604 | 435 | /* Increment the fault counts */ |
48dc4241 | 436 | gpu->global_faults++; |
b0fb6604 | 437 | submit->queue->faults++; |
48dc4241 | 438 | |
482f9632 | 439 | task = get_pid_task(submit->pid, PIDTYPE_PID); |
18bb8a6c | 440 | if (task) { |
482f9632 | 441 | comm = kstrdup(task->comm, GFP_KERNEL); |
482f9632 SM |
442 | cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); |
443 | put_task_struct(task); | |
65a3c274 | 444 | } |
18bb8a6c | 445 | |
65a3c274 | 446 | if (comm && cmd) { |
6a41da17 | 447 | DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", |
65a3c274 | 448 | gpu->name, comm, cmd); |
96169f4e RC |
449 | |
450 | msm_rd_dump_submit(priv->hangrd, submit, | |
65a3c274 JC |
451 | "offending task: %s (%s)", comm, cmd); |
452 | } else | |
96169f4e | 453 | msm_rd_dump_submit(priv->hangrd, submit, NULL); |
96169f4e RC |
454 | } |
455 | ||
c0fec7f5 JC |
456 | /* Record the crash state */ |
457 | pm_runtime_get_sync(&gpu->pdev->dev); | |
cdb95931 | 458 | msm_gpu_crashstate_capture(gpu, submit, comm, cmd); |
c0fec7f5 JC |
459 | pm_runtime_put_sync(&gpu->pdev->dev); |
460 | ||
65a3c274 JC |
461 | kfree(cmd); |
462 | kfree(comm); | |
96169f4e RC |
463 | |
464 | /* | |
465 | * Update all the rings with the latest and greatest fence.. this | |
466 | * needs to happen after msm_rd_dump_submit() to ensure that the | |
467 | * bo's referenced by the offending submit are still around. | |
468 | */ | |
7ddae82e | 469 | for (i = 0; i < gpu->nr_rings; i++) { |
96169f4e RC |
470 | struct msm_ringbuffer *ring = gpu->rb[i]; |
471 | ||
472 | uint32_t fence = ring->memptrs->fence; | |
18bb8a6c | 473 | |
96169f4e RC |
474 | /* |
475 | * For the current (faulting?) ring/submit advance the fence by | |
476 | * one more to clear the faulting submit | |
477 | */ | |
478 | if (ring == cur_ring) | |
479 | fence++; | |
480 | ||
481 | update_fences(gpu, ring, fence); | |
4816b626 RC |
482 | } |
483 | ||
484 | if (msm_gpu_active(gpu)) { | |
1a370be9 | 485 | /* retire completed submits, plus the one that hung: */ |
b6295f9a | 486 | retire_submits(gpu); |
1a370be9 | 487 | |
eeb75474 | 488 | pm_runtime_get_sync(&gpu->pdev->dev); |
37d77c3a | 489 | gpu->funcs->recover(gpu); |
eeb75474 | 490 | pm_runtime_put_sync(&gpu->pdev->dev); |
1a370be9 | 491 | |
f97decac JC |
492 | /* |
493 | * Replay all remaining submits starting with highest priority | |
494 | * ring | |
495 | */ | |
b1fc2839 | 496 | for (i = 0; i < gpu->nr_rings; i++) { |
f97decac JC |
497 | struct msm_ringbuffer *ring = gpu->rb[i]; |
498 | ||
499 | list_for_each_entry(submit, &ring->submits, node) | |
500 | gpu->funcs->submit(gpu, submit, NULL); | |
1a370be9 | 501 | } |
37d77c3a | 502 | } |
4816b626 | 503 | |
bd6f82d8 RC |
504 | mutex_unlock(&dev->struct_mutex); |
505 | ||
506 | msm_gpu_retire(gpu); | |
507 | } | |
508 | ||
509 | static void hangcheck_timer_reset(struct msm_gpu *gpu) | |
510 | { | |
511 | DBG("%s", gpu->name); | |
512 | mod_timer(&gpu->hangcheck_timer, | |
513 | round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); | |
514 | } | |
515 | ||
e99e88a9 | 516 | static void hangcheck_handler(struct timer_list *t) |
bd6f82d8 | 517 | { |
e99e88a9 | 518 | struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); |
6b8819c8 RC |
519 | struct drm_device *dev = gpu->dev; |
520 | struct msm_drm_private *priv = dev->dev_private; | |
f97decac JC |
521 | struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); |
522 | uint32_t fence = ring->memptrs->fence; | |
bd6f82d8 | 523 | |
f97decac | 524 | if (fence != ring->hangcheck_fence) { |
bd6f82d8 | 525 | /* some progress has been made.. ya! */ |
f97decac JC |
526 | ring->hangcheck_fence = fence; |
527 | } else if (fence < ring->seqno) { | |
bd6f82d8 | 528 | /* no progress and not done.. hung! */ |
f97decac | 529 | ring->hangcheck_fence = fence; |
6a41da17 | 530 | DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", |
f97decac | 531 | gpu->name, ring->id); |
6a41da17 | 532 | DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", |
26791c48 | 533 | gpu->name, fence); |
6a41da17 | 534 | DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", |
f97decac JC |
535 | gpu->name, ring->seqno); |
536 | ||
bd6f82d8 RC |
537 | queue_work(priv->wq, &gpu->recover_work); |
538 | } | |
539 | ||
540 | /* if still more pending work, reset the hangcheck timer: */ | |
f97decac | 541 | if (ring->seqno > ring->hangcheck_fence) |
bd6f82d8 | 542 | hangcheck_timer_reset(gpu); |
6b8819c8 RC |
543 | |
544 | /* workaround for missing irq: */ | |
545 | queue_work(priv->wq, &gpu->retire_work); | |
bd6f82d8 RC |
546 | } |
547 | ||
70c70f09 RC |
548 | /* |
549 | * Performance Counters: | |
550 | */ | |
551 | ||
552 | /* called under perf_lock */ | |
553 | static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) | |
554 | { | |
555 | uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; | |
556 | int i, n = min(ncntrs, gpu->num_perfcntrs); | |
557 | ||
558 | /* read current values: */ | |
559 | for (i = 0; i < gpu->num_perfcntrs; i++) | |
560 | current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); | |
561 | ||
562 | /* update cntrs: */ | |
563 | for (i = 0; i < n; i++) | |
564 | cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; | |
565 | ||
566 | /* save current values: */ | |
567 | for (i = 0; i < gpu->num_perfcntrs; i++) | |
568 | gpu->last_cntrs[i] = current_cntrs[i]; | |
569 | ||
570 | return n; | |
571 | } | |
572 | ||
573 | static void update_sw_cntrs(struct msm_gpu *gpu) | |
574 | { | |
575 | ktime_t time; | |
576 | uint32_t elapsed; | |
577 | unsigned long flags; | |
578 | ||
579 | spin_lock_irqsave(&gpu->perf_lock, flags); | |
580 | if (!gpu->perfcntr_active) | |
581 | goto out; | |
582 | ||
583 | time = ktime_get(); | |
584 | elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); | |
585 | ||
586 | gpu->totaltime += elapsed; | |
587 | if (gpu->last_sample.active) | |
588 | gpu->activetime += elapsed; | |
589 | ||
590 | gpu->last_sample.active = msm_gpu_active(gpu); | |
591 | gpu->last_sample.time = time; | |
592 | ||
593 | out: | |
594 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
595 | } | |
596 | ||
597 | void msm_gpu_perfcntr_start(struct msm_gpu *gpu) | |
598 | { | |
599 | unsigned long flags; | |
600 | ||
eeb75474 RC |
601 | pm_runtime_get_sync(&gpu->pdev->dev); |
602 | ||
70c70f09 RC |
603 | spin_lock_irqsave(&gpu->perf_lock, flags); |
604 | /* we could dynamically enable/disable perfcntr registers too.. */ | |
605 | gpu->last_sample.active = msm_gpu_active(gpu); | |
606 | gpu->last_sample.time = ktime_get(); | |
607 | gpu->activetime = gpu->totaltime = 0; | |
608 | gpu->perfcntr_active = true; | |
609 | update_hw_cntrs(gpu, 0, NULL); | |
610 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
611 | } | |
612 | ||
613 | void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) | |
614 | { | |
615 | gpu->perfcntr_active = false; | |
eeb75474 | 616 | pm_runtime_put_sync(&gpu->pdev->dev); |
70c70f09 RC |
617 | } |
618 | ||
619 | /* returns -errno or # of cntrs sampled */ | |
620 | int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, | |
621 | uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) | |
622 | { | |
623 | unsigned long flags; | |
624 | int ret; | |
625 | ||
626 | spin_lock_irqsave(&gpu->perf_lock, flags); | |
627 | ||
628 | if (!gpu->perfcntr_active) { | |
629 | ret = -EINVAL; | |
630 | goto out; | |
631 | } | |
632 | ||
633 | *activetime = gpu->activetime; | |
634 | *totaltime = gpu->totaltime; | |
635 | ||
636 | gpu->activetime = gpu->totaltime = 0; | |
637 | ||
638 | ret = update_hw_cntrs(gpu, ncntrs, cntrs); | |
639 | ||
640 | out: | |
641 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
642 | ||
643 | return ret; | |
644 | } | |
645 | ||
7198e6b0 RC |
646 | /* |
647 | * Cmdstream submission/retirement: | |
648 | */ | |
649 | ||
4241db42 JC |
650 | static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, |
651 | struct msm_gem_submit *submit) | |
7d12a279 | 652 | { |
4241db42 JC |
653 | int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; |
654 | volatile struct msm_gpu_submit_stats *stats; | |
655 | u64 elapsed, clock = 0; | |
7d12a279 RC |
656 | int i; |
657 | ||
4241db42 JC |
658 | stats = &ring->memptrs->stats[index]; |
659 | /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ | |
660 | elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; | |
661 | do_div(elapsed, 192); | |
662 | ||
663 | /* Calculate the clock frequency from the number of CP cycles */ | |
664 | if (elapsed) { | |
665 | clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000; | |
666 | do_div(clock, elapsed); | |
667 | } | |
668 | ||
669 | trace_msm_gpu_submit_retired(submit, elapsed, clock, | |
670 | stats->alwayson_start, stats->alwayson_end); | |
671 | ||
7d12a279 RC |
672 | for (i = 0; i < submit->nr_bos; i++) { |
673 | struct msm_gem_object *msm_obj = submit->bos[i].obj; | |
674 | /* move to inactive: */ | |
675 | msm_gem_move_to_inactive(&msm_obj->base); | |
7ad0e8cf | 676 | msm_gem_unpin_iova(&msm_obj->base, gpu->aspace); |
dc9a9b32 | 677 | drm_gem_object_put(&msm_obj->base); |
7d12a279 RC |
678 | } |
679 | ||
eeb75474 RC |
680 | pm_runtime_mark_last_busy(&gpu->pdev->dev); |
681 | pm_runtime_put_autosuspend(&gpu->pdev->dev); | |
40e6815b | 682 | msm_gem_submit_free(submit); |
7d12a279 RC |
683 | } |
684 | ||
b6295f9a | 685 | static void retire_submits(struct msm_gpu *gpu) |
1a370be9 RC |
686 | { |
687 | struct drm_device *dev = gpu->dev; | |
f97decac JC |
688 | struct msm_gem_submit *submit, *tmp; |
689 | int i; | |
1a370be9 RC |
690 | |
691 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
692 | ||
f97decac | 693 | /* Retire the commits starting with highest priority */ |
b1fc2839 | 694 | for (i = 0; i < gpu->nr_rings; i++) { |
f97decac | 695 | struct msm_ringbuffer *ring = gpu->rb[i]; |
1a370be9 | 696 | |
f97decac JC |
697 | list_for_each_entry_safe(submit, tmp, &ring->submits, node) { |
698 | if (dma_fence_is_signaled(submit->fence)) | |
4241db42 | 699 | retire_submit(gpu, ring, submit); |
1a370be9 RC |
700 | } |
701 | } | |
702 | } | |
703 | ||
7198e6b0 RC |
704 | static void retire_worker(struct work_struct *work) |
705 | { | |
706 | struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); | |
707 | struct drm_device *dev = gpu->dev; | |
f97decac | 708 | int i; |
7198e6b0 | 709 | |
f97decac JC |
710 | for (i = 0; i < gpu->nr_rings; i++) |
711 | update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); | |
edd4fc63 | 712 | |
7198e6b0 | 713 | mutex_lock(&dev->struct_mutex); |
b6295f9a | 714 | retire_submits(gpu); |
7198e6b0 RC |
715 | mutex_unlock(&dev->struct_mutex); |
716 | } | |
717 | ||
718 | /* call from irq handler to schedule work to retire bo's */ | |
719 | void msm_gpu_retire(struct msm_gpu *gpu) | |
720 | { | |
721 | struct msm_drm_private *priv = gpu->dev->dev_private; | |
722 | queue_work(priv->wq, &gpu->retire_work); | |
70c70f09 | 723 | update_sw_cntrs(gpu); |
7198e6b0 RC |
724 | } |
725 | ||
726 | /* add bo's to gpu's ring, and kick gpu: */ | |
f44d32c7 | 727 | void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, |
7198e6b0 RC |
728 | struct msm_file_private *ctx) |
729 | { | |
730 | struct drm_device *dev = gpu->dev; | |
731 | struct msm_drm_private *priv = dev->dev_private; | |
f97decac | 732 | struct msm_ringbuffer *ring = submit->ring; |
f44d32c7 | 733 | int i; |
7198e6b0 | 734 | |
1a370be9 RC |
735 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
736 | ||
eeb75474 RC |
737 | pm_runtime_get_sync(&gpu->pdev->dev); |
738 | ||
739 | msm_gpu_hw_init(gpu); | |
37d77c3a | 740 | |
f97decac JC |
741 | submit->seqno = ++ring->seqno; |
742 | ||
743 | list_add_tail(&submit->node, &ring->submits); | |
1a370be9 | 744 | |
998b9a58 | 745 | msm_rd_dump_submit(priv->rd, submit, NULL); |
a7d3c950 | 746 | |
70c70f09 RC |
747 | update_sw_cntrs(gpu); |
748 | ||
7198e6b0 RC |
749 | for (i = 0; i < submit->nr_bos; i++) { |
750 | struct msm_gem_object *msm_obj = submit->bos[i].obj; | |
78babc16 | 751 | uint64_t iova; |
7198e6b0 RC |
752 | |
753 | /* can't happen yet.. but when we add 2d support we'll have | |
754 | * to deal w/ cross-ring synchronization: | |
755 | */ | |
756 | WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); | |
757 | ||
7d12a279 | 758 | /* submit takes a reference to the bo and iova until retired: */ |
dc9a9b32 | 759 | drm_gem_object_get(&msm_obj->base); |
9fe041f6 | 760 | msm_gem_get_and_pin_iova(&msm_obj->base, |
8bdcd949 | 761 | submit->gpu->aspace, &iova); |
7198e6b0 | 762 | |
bf6811f3 RC |
763 | if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) |
764 | msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); | |
b6295f9a RC |
765 | else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ) |
766 | msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); | |
7198e6b0 | 767 | } |
1a370be9 | 768 | |
1193c3bc | 769 | gpu->funcs->submit(gpu, submit, ctx); |
1a370be9 RC |
770 | priv->lastctx = ctx; |
771 | ||
bd6f82d8 | 772 | hangcheck_timer_reset(gpu); |
7198e6b0 RC |
773 | } |
774 | ||
775 | /* | |
776 | * Init/Cleanup: | |
777 | */ | |
778 | ||
779 | static irqreturn_t irq_handler(int irq, void *data) | |
780 | { | |
781 | struct msm_gpu *gpu = data; | |
782 | return gpu->funcs->irq(gpu); | |
783 | } | |
784 | ||
98db803f JC |
785 | static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) |
786 | { | |
8e54eea5 | 787 | int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks); |
98db803f | 788 | |
8e54eea5 | 789 | if (ret < 1) { |
98db803f | 790 | gpu->nr_clocks = 0; |
8e54eea5 | 791 | return ret; |
9d20a0e6 | 792 | } |
98db803f | 793 | |
8e54eea5 | 794 | gpu->nr_clocks = ret; |
98db803f | 795 | |
8e54eea5 JC |
796 | gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, |
797 | gpu->nr_clocks, "core"); | |
98db803f | 798 | |
8e54eea5 JC |
799 | gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, |
800 | gpu->nr_clocks, "rbbmtimer"); | |
98db803f JC |
801 | |
802 | return 0; | |
803 | } | |
7198e6b0 | 804 | |
1267a4df JC |
805 | static struct msm_gem_address_space * |
806 | msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, | |
807 | uint64_t va_start, uint64_t va_end) | |
808 | { | |
1267a4df JC |
809 | struct msm_gem_address_space *aspace; |
810 | int ret; | |
811 | ||
812 | /* | |
813 | * Setup IOMMU.. eventually we will (I think) do this once per context | |
814 | * and have separate page tables per context. For now, to keep things | |
815 | * simple and to get something working, just use a single address space: | |
816 | */ | |
c2052a4e JM |
817 | if (!adreno_is_a2xx(to_adreno_gpu(gpu))) { |
818 | struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type); | |
819 | if (!iommu) | |
820 | return NULL; | |
821 | ||
822 | iommu->geometry.aperture_start = va_start; | |
823 | iommu->geometry.aperture_end = va_end; | |
824 | ||
825 | DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); | |
826 | ||
827 | aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); | |
828 | if (IS_ERR(aspace)) | |
829 | iommu_domain_free(iommu); | |
830 | } else { | |
831 | aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu", | |
832 | va_start, va_end); | |
833 | } | |
1267a4df | 834 | |
1267a4df | 835 | if (IS_ERR(aspace)) { |
c2052a4e | 836 | DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n", |
1267a4df | 837 | PTR_ERR(aspace)); |
1267a4df JC |
838 | return ERR_CAST(aspace); |
839 | } | |
840 | ||
841 | ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); | |
842 | if (ret) { | |
843 | msm_gem_address_space_put(aspace); | |
844 | return ERR_PTR(ret); | |
845 | } | |
846 | ||
847 | return aspace; | |
848 | } | |
849 | ||
7198e6b0 RC |
850 | int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, |
851 | struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, | |
5770fc7a | 852 | const char *name, struct msm_gpu_config *config) |
7198e6b0 | 853 | { |
f97decac JC |
854 | int i, ret, nr_rings = config->nr_rings; |
855 | void *memptrs; | |
856 | uint64_t memptrs_iova; | |
7198e6b0 | 857 | |
70c70f09 RC |
858 | if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) |
859 | gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); | |
860 | ||
7198e6b0 RC |
861 | gpu->dev = drm; |
862 | gpu->funcs = funcs; | |
863 | gpu->name = name; | |
864 | ||
865 | INIT_LIST_HEAD(&gpu->active_list); | |
866 | INIT_WORK(&gpu->retire_work, retire_worker); | |
bd6f82d8 RC |
867 | INIT_WORK(&gpu->recover_work, recover_worker); |
868 | ||
1a370be9 | 869 | |
e99e88a9 | 870 | timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); |
7198e6b0 | 871 | |
70c70f09 RC |
872 | spin_lock_init(&gpu->perf_lock); |
873 | ||
7198e6b0 RC |
874 | |
875 | /* Map registers: */ | |
5770fc7a | 876 | gpu->mmio = msm_ioremap(pdev, config->ioname, name); |
7198e6b0 RC |
877 | if (IS_ERR(gpu->mmio)) { |
878 | ret = PTR_ERR(gpu->mmio); | |
879 | goto fail; | |
880 | } | |
881 | ||
882 | /* Get Interrupt: */ | |
878411ae | 883 | gpu->irq = platform_get_irq(pdev, 0); |
7198e6b0 RC |
884 | if (gpu->irq < 0) { |
885 | ret = gpu->irq; | |
6a41da17 | 886 | DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); |
7198e6b0 RC |
887 | goto fail; |
888 | } | |
889 | ||
890 | ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, | |
891 | IRQF_TRIGGER_HIGH, gpu->name, gpu); | |
892 | if (ret) { | |
6a41da17 | 893 | DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); |
7198e6b0 RC |
894 | goto fail; |
895 | } | |
896 | ||
98db803f JC |
897 | ret = get_clocks(pdev, gpu); |
898 | if (ret) | |
899 | goto fail; | |
7198e6b0 | 900 | |
720c3bb8 | 901 | gpu->ebi1_clk = msm_clk_get(pdev, "bus"); |
7198e6b0 RC |
902 | DBG("ebi1_clk: %p", gpu->ebi1_clk); |
903 | if (IS_ERR(gpu->ebi1_clk)) | |
904 | gpu->ebi1_clk = NULL; | |
905 | ||
906 | /* Acquire regulators: */ | |
907 | gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); | |
908 | DBG("gpu_reg: %p", gpu->gpu_reg); | |
909 | if (IS_ERR(gpu->gpu_reg)) | |
910 | gpu->gpu_reg = NULL; | |
911 | ||
912 | gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); | |
913 | DBG("gpu_cx: %p", gpu->gpu_cx); | |
914 | if (IS_ERR(gpu->gpu_cx)) | |
915 | gpu->gpu_cx = NULL; | |
916 | ||
1267a4df JC |
917 | gpu->pdev = pdev; |
918 | platform_set_drvdata(pdev, gpu); | |
919 | ||
f91c14ab JC |
920 | msm_devfreq_init(gpu); |
921 | ||
1267a4df JC |
922 | gpu->aspace = msm_gpu_create_address_space(gpu, pdev, |
923 | config->va_start, config->va_end); | |
924 | ||
925 | if (gpu->aspace == NULL) | |
6a41da17 | 926 | DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); |
1267a4df JC |
927 | else if (IS_ERR(gpu->aspace)) { |
928 | ret = PTR_ERR(gpu->aspace); | |
929 | goto fail; | |
7198e6b0 | 930 | } |
a1ad3523 | 931 | |
546ec7b4 JC |
932 | memptrs = msm_gem_kernel_new(drm, |
933 | sizeof(struct msm_rbmemptrs) * nr_rings, | |
cd414f3d | 934 | MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, |
f97decac | 935 | &memptrs_iova); |
cd414f3d | 936 | |
f97decac JC |
937 | if (IS_ERR(memptrs)) { |
938 | ret = PTR_ERR(memptrs); | |
6a41da17 | 939 | DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); |
cd414f3d JC |
940 | goto fail; |
941 | } | |
942 | ||
0815d774 JC |
943 | msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); |
944 | ||
f97decac | 945 | if (nr_rings > ARRAY_SIZE(gpu->rb)) { |
39ae0d3e | 946 | DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", |
f97decac JC |
947 | ARRAY_SIZE(gpu->rb)); |
948 | nr_rings = ARRAY_SIZE(gpu->rb); | |
7198e6b0 RC |
949 | } |
950 | ||
f97decac JC |
951 | /* Create ringbuffer(s): */ |
952 | for (i = 0; i < nr_rings; i++) { | |
953 | gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); | |
954 | ||
955 | if (IS_ERR(gpu->rb[i])) { | |
956 | ret = PTR_ERR(gpu->rb[i]); | |
6a41da17 | 957 | DRM_DEV_ERROR(drm->dev, |
f97decac JC |
958 | "could not create ringbuffer %d: %d\n", i, ret); |
959 | goto fail; | |
960 | } | |
961 | ||
962 | memptrs += sizeof(struct msm_rbmemptrs); | |
963 | memptrs_iova += sizeof(struct msm_rbmemptrs); | |
964 | } | |
965 | ||
966 | gpu->nr_rings = nr_rings; | |
967 | ||
7198e6b0 RC |
968 | return 0; |
969 | ||
970 | fail: | |
f97decac JC |
971 | for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { |
972 | msm_ringbuffer_destroy(gpu->rb[i]); | |
973 | gpu->rb[i] = NULL; | |
974 | } | |
975 | ||
1e29dff0 | 976 | msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); |
cd414f3d | 977 | |
1267a4df | 978 | platform_set_drvdata(pdev, NULL); |
7198e6b0 RC |
979 | return ret; |
980 | } | |
981 | ||
982 | void msm_gpu_cleanup(struct msm_gpu *gpu) | |
983 | { | |
f97decac JC |
984 | int i; |
985 | ||
7198e6b0 RC |
986 | DBG("%s", gpu->name); |
987 | ||
988 | WARN_ON(!list_empty(&gpu->active_list)); | |
989 | ||
f97decac JC |
990 | for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { |
991 | msm_ringbuffer_destroy(gpu->rb[i]); | |
992 | gpu->rb[i] = NULL; | |
7198e6b0 | 993 | } |
cd414f3d | 994 | |
1e29dff0 | 995 | msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); |
cd414f3d JC |
996 | |
997 | if (!IS_ERR_OR_NULL(gpu->aspace)) { | |
1267a4df JC |
998 | gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, |
999 | NULL, 0); | |
1000 | msm_gem_address_space_put(gpu->aspace); | |
1001 | } | |
7198e6b0 | 1002 | } |