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7198e6b0 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "msm_gpu.h" | |
19 | #include "msm_gem.h" | |
871d812a | 20 | #include "msm_mmu.h" |
fde5de6c | 21 | #include "msm_fence.h" |
4241db42 | 22 | #include "msm_gpu_trace.h" |
c2052a4e | 23 | #include "adreno/adreno_gpu.h" |
7198e6b0 | 24 | |
c0fec7f5 | 25 | #include <generated/utsrelease.h> |
18bb8a6c | 26 | #include <linux/string_helpers.h> |
f91c14ab JC |
27 | #include <linux/pm_opp.h> |
28 | #include <linux/devfreq.h> | |
c0fec7f5 | 29 | #include <linux/devcoredump.h> |
7198e6b0 RC |
30 | |
31 | /* | |
32 | * Power Management: | |
33 | */ | |
34 | ||
f91c14ab JC |
35 | static int msm_devfreq_target(struct device *dev, unsigned long *freq, |
36 | u32 flags) | |
37 | { | |
38 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
39 | struct dev_pm_opp *opp; | |
40 | ||
41 | opp = devfreq_recommended_opp(dev, freq, flags); | |
42 | ||
43 | if (IS_ERR(opp)) | |
44 | return PTR_ERR(opp); | |
45 | ||
de0a3d09 SM |
46 | if (gpu->funcs->gpu_set_freq) |
47 | gpu->funcs->gpu_set_freq(gpu, (u64)*freq); | |
48 | else | |
49 | clk_set_rate(gpu->core_clk, *freq); | |
50 | ||
f91c14ab JC |
51 | dev_pm_opp_put(opp); |
52 | ||
53 | return 0; | |
54 | } | |
55 | ||
56 | static int msm_devfreq_get_dev_status(struct device *dev, | |
57 | struct devfreq_dev_status *status) | |
58 | { | |
59 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
f91c14ab JC |
60 | ktime_t time; |
61 | ||
de0a3d09 SM |
62 | if (gpu->funcs->gpu_get_freq) |
63 | status->current_frequency = gpu->funcs->gpu_get_freq(gpu); | |
64 | else | |
65 | status->current_frequency = clk_get_rate(gpu->core_clk); | |
f91c14ab | 66 | |
de0a3d09 | 67 | status->busy_time = gpu->funcs->gpu_busy(gpu); |
f91c14ab JC |
68 | |
69 | time = ktime_get(); | |
70 | status->total_time = ktime_us_delta(time, gpu->devfreq.time); | |
71 | gpu->devfreq.time = time; | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq) | |
77 | { | |
78 | struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev)); | |
79 | ||
de0a3d09 SM |
80 | if (gpu->funcs->gpu_get_freq) |
81 | *freq = gpu->funcs->gpu_get_freq(gpu); | |
82 | else | |
83 | *freq = clk_get_rate(gpu->core_clk); | |
f91c14ab JC |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static struct devfreq_dev_profile msm_devfreq_profile = { | |
89 | .polling_ms = 10, | |
90 | .target = msm_devfreq_target, | |
91 | .get_dev_status = msm_devfreq_get_dev_status, | |
92 | .get_cur_freq = msm_devfreq_get_cur_freq, | |
93 | }; | |
94 | ||
95 | static void msm_devfreq_init(struct msm_gpu *gpu) | |
96 | { | |
97 | /* We need target support to do devfreq */ | |
de0a3d09 | 98 | if (!gpu->funcs->gpu_busy) |
f91c14ab JC |
99 | return; |
100 | ||
101 | msm_devfreq_profile.initial_freq = gpu->fast_rate; | |
102 | ||
103 | /* | |
104 | * Don't set the freq_table or max_state and let devfreq build the table | |
105 | * from OPP | |
106 | */ | |
107 | ||
108 | gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev, | |
109 | &msm_devfreq_profile, "simple_ondemand", NULL); | |
110 | ||
111 | if (IS_ERR(gpu->devfreq.devfreq)) { | |
6a41da17 | 112 | DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n"); |
f91c14ab JC |
113 | gpu->devfreq.devfreq = NULL; |
114 | } | |
d3fa91c9 SM |
115 | |
116 | devfreq_suspend_device(gpu->devfreq.devfreq); | |
f91c14ab JC |
117 | } |
118 | ||
7198e6b0 RC |
119 | static int enable_pwrrail(struct msm_gpu *gpu) |
120 | { | |
121 | struct drm_device *dev = gpu->dev; | |
122 | int ret = 0; | |
123 | ||
124 | if (gpu->gpu_reg) { | |
125 | ret = regulator_enable(gpu->gpu_reg); | |
126 | if (ret) { | |
6a41da17 | 127 | DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); |
7198e6b0 RC |
128 | return ret; |
129 | } | |
130 | } | |
131 | ||
132 | if (gpu->gpu_cx) { | |
133 | ret = regulator_enable(gpu->gpu_cx); | |
134 | if (ret) { | |
6a41da17 | 135 | DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); |
7198e6b0 RC |
136 | return ret; |
137 | } | |
138 | } | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | static int disable_pwrrail(struct msm_gpu *gpu) | |
144 | { | |
145 | if (gpu->gpu_cx) | |
146 | regulator_disable(gpu->gpu_cx); | |
147 | if (gpu->gpu_reg) | |
148 | regulator_disable(gpu->gpu_reg); | |
149 | return 0; | |
150 | } | |
151 | ||
152 | static int enable_clk(struct msm_gpu *gpu) | |
153 | { | |
98db803f JC |
154 | if (gpu->core_clk && gpu->fast_rate) |
155 | clk_set_rate(gpu->core_clk, gpu->fast_rate); | |
7198e6b0 | 156 | |
b5f103ab | 157 | /* Set the RBBM timer rate to 19.2Mhz */ |
98db803f JC |
158 | if (gpu->rbbmtimer_clk) |
159 | clk_set_rate(gpu->rbbmtimer_clk, 19200000); | |
b5f103ab | 160 | |
8e54eea5 | 161 | return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); |
7198e6b0 RC |
162 | } |
163 | ||
164 | static int disable_clk(struct msm_gpu *gpu) | |
165 | { | |
8e54eea5 | 166 | clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); |
7198e6b0 | 167 | |
bf5af4ae JC |
168 | /* |
169 | * Set the clock to a deliberately low rate. On older targets the clock | |
170 | * speed had to be non zero to avoid problems. On newer targets this | |
171 | * will be rounded down to zero anyway so it all works out. | |
172 | */ | |
98db803f JC |
173 | if (gpu->core_clk) |
174 | clk_set_rate(gpu->core_clk, 27000000); | |
89d777a5 | 175 | |
98db803f JC |
176 | if (gpu->rbbmtimer_clk) |
177 | clk_set_rate(gpu->rbbmtimer_clk, 0); | |
b5f103ab | 178 | |
7198e6b0 RC |
179 | return 0; |
180 | } | |
181 | ||
182 | static int enable_axi(struct msm_gpu *gpu) | |
183 | { | |
184 | if (gpu->ebi1_clk) | |
185 | clk_prepare_enable(gpu->ebi1_clk); | |
7198e6b0 RC |
186 | return 0; |
187 | } | |
188 | ||
189 | static int disable_axi(struct msm_gpu *gpu) | |
190 | { | |
191 | if (gpu->ebi1_clk) | |
192 | clk_disable_unprepare(gpu->ebi1_clk); | |
7198e6b0 RC |
193 | return 0; |
194 | } | |
195 | ||
de0a3d09 SM |
196 | void msm_gpu_resume_devfreq(struct msm_gpu *gpu) |
197 | { | |
198 | gpu->devfreq.busy_cycles = 0; | |
199 | gpu->devfreq.time = ktime_get(); | |
200 | ||
201 | devfreq_resume_device(gpu->devfreq.devfreq); | |
202 | } | |
203 | ||
7198e6b0 RC |
204 | int msm_gpu_pm_resume(struct msm_gpu *gpu) |
205 | { | |
206 | int ret; | |
207 | ||
eeb75474 | 208 | DBG("%s", gpu->name); |
7198e6b0 RC |
209 | |
210 | ret = enable_pwrrail(gpu); | |
211 | if (ret) | |
212 | return ret; | |
213 | ||
214 | ret = enable_clk(gpu); | |
215 | if (ret) | |
216 | return ret; | |
217 | ||
218 | ret = enable_axi(gpu); | |
219 | if (ret) | |
220 | return ret; | |
221 | ||
de0a3d09 | 222 | msm_gpu_resume_devfreq(gpu); |
f91c14ab | 223 | |
eeb75474 RC |
224 | gpu->needs_hw_init = true; |
225 | ||
7198e6b0 RC |
226 | return 0; |
227 | } | |
228 | ||
229 | int msm_gpu_pm_suspend(struct msm_gpu *gpu) | |
230 | { | |
231 | int ret; | |
232 | ||
eeb75474 | 233 | DBG("%s", gpu->name); |
7198e6b0 | 234 | |
de0a3d09 | 235 | devfreq_suspend_device(gpu->devfreq.devfreq); |
f91c14ab | 236 | |
7198e6b0 RC |
237 | ret = disable_axi(gpu); |
238 | if (ret) | |
239 | return ret; | |
240 | ||
241 | ret = disable_clk(gpu); | |
242 | if (ret) | |
243 | return ret; | |
244 | ||
245 | ret = disable_pwrrail(gpu); | |
246 | if (ret) | |
247 | return ret; | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
eeb75474 | 252 | int msm_gpu_hw_init(struct msm_gpu *gpu) |
37d77c3a | 253 | { |
eeb75474 | 254 | int ret; |
37d77c3a | 255 | |
cb1e3818 RC |
256 | WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex)); |
257 | ||
eeb75474 RC |
258 | if (!gpu->needs_hw_init) |
259 | return 0; | |
37d77c3a | 260 | |
eeb75474 RC |
261 | disable_irq(gpu->irq); |
262 | ret = gpu->funcs->hw_init(gpu); | |
263 | if (!ret) | |
264 | gpu->needs_hw_init = false; | |
265 | enable_irq(gpu->irq); | |
37d77c3a | 266 | |
eeb75474 | 267 | return ret; |
37d77c3a RC |
268 | } |
269 | ||
c0fec7f5 JC |
270 | #ifdef CONFIG_DEV_COREDUMP |
271 | static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, | |
272 | size_t count, void *data, size_t datalen) | |
273 | { | |
274 | struct msm_gpu *gpu = data; | |
275 | struct drm_print_iterator iter; | |
276 | struct drm_printer p; | |
277 | struct msm_gpu_state *state; | |
278 | ||
279 | state = msm_gpu_crashstate_get(gpu); | |
280 | if (!state) | |
281 | return 0; | |
282 | ||
283 | iter.data = buffer; | |
284 | iter.offset = 0; | |
285 | iter.start = offset; | |
286 | iter.remain = count; | |
287 | ||
288 | p = drm_coredump_printer(&iter); | |
289 | ||
290 | drm_printf(&p, "---\n"); | |
291 | drm_printf(&p, "kernel: " UTS_RELEASE "\n"); | |
292 | drm_printf(&p, "module: " KBUILD_MODNAME "\n"); | |
3530a17f AB |
293 | drm_printf(&p, "time: %lld.%09ld\n", |
294 | state->time.tv_sec, state->time.tv_nsec); | |
c0fec7f5 JC |
295 | if (state->comm) |
296 | drm_printf(&p, "comm: %s\n", state->comm); | |
297 | if (state->cmd) | |
298 | drm_printf(&p, "cmdline: %s\n", state->cmd); | |
299 | ||
300 | gpu->funcs->show(gpu, state, &p); | |
301 | ||
302 | msm_gpu_crashstate_put(gpu); | |
303 | ||
304 | return count - iter.remain; | |
305 | } | |
306 | ||
307 | static void msm_gpu_devcoredump_free(void *data) | |
308 | { | |
309 | struct msm_gpu *gpu = data; | |
310 | ||
311 | msm_gpu_crashstate_put(gpu); | |
312 | } | |
313 | ||
cdb95931 JC |
314 | static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, |
315 | struct msm_gem_object *obj, u64 iova, u32 flags) | |
316 | { | |
317 | struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; | |
318 | ||
319 | /* Don't record write only objects */ | |
cdb95931 JC |
320 | state_bo->size = obj->base.size; |
321 | state_bo->iova = iova; | |
322 | ||
896a248a JC |
323 | /* Only store data for non imported buffer objects marked for read */ |
324 | if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) { | |
cdb95931 JC |
325 | void *ptr; |
326 | ||
327 | state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); | |
328 | if (!state_bo->data) | |
896a248a | 329 | goto out; |
cdb95931 JC |
330 | |
331 | ptr = msm_gem_get_vaddr_active(&obj->base); | |
332 | if (IS_ERR(ptr)) { | |
333 | kvfree(state_bo->data); | |
896a248a JC |
334 | state_bo->data = NULL; |
335 | goto out; | |
cdb95931 JC |
336 | } |
337 | ||
338 | memcpy(state_bo->data, ptr, obj->base.size); | |
339 | msm_gem_put_vaddr(&obj->base); | |
340 | } | |
896a248a | 341 | out: |
cdb95931 JC |
342 | state->nr_bos++; |
343 | } | |
344 | ||
345 | static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, | |
346 | struct msm_gem_submit *submit, char *comm, char *cmd) | |
c0fec7f5 JC |
347 | { |
348 | struct msm_gpu_state *state; | |
349 | ||
4f3a31a8 SM |
350 | /* Check if the target supports capturing crash state */ |
351 | if (!gpu->funcs->gpu_state_get) | |
352 | return; | |
353 | ||
c0fec7f5 JC |
354 | /* Only save one crash state at a time */ |
355 | if (gpu->crashstate) | |
356 | return; | |
357 | ||
358 | state = gpu->funcs->gpu_state_get(gpu); | |
359 | if (IS_ERR_OR_NULL(state)) | |
360 | return; | |
361 | ||
362 | /* Fill in the additional crash state information */ | |
363 | state->comm = kstrdup(comm, GFP_KERNEL); | |
364 | state->cmd = kstrdup(cmd, GFP_KERNEL); | |
365 | ||
cdb95931 JC |
366 | if (submit) { |
367 | int i; | |
368 | ||
896a248a | 369 | state->bos = kcalloc(submit->nr_cmds, |
cdb95931 JC |
370 | sizeof(struct msm_gpu_state_bo), GFP_KERNEL); |
371 | ||
896a248a JC |
372 | for (i = 0; state->bos && i < submit->nr_cmds; i++) { |
373 | int idx = submit->cmd[i].idx; | |
374 | ||
375 | msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj, | |
376 | submit->bos[idx].iova, submit->bos[idx].flags); | |
377 | } | |
cdb95931 JC |
378 | } |
379 | ||
c0fec7f5 JC |
380 | /* Set the active crash state to be dumped on failure */ |
381 | gpu->crashstate = state; | |
382 | ||
383 | /* FIXME: Release the crashstate if this errors out? */ | |
384 | dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, | |
385 | msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); | |
386 | } | |
387 | #else | |
6969019f AR |
388 | static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, |
389 | struct msm_gem_submit *submit, char *comm, char *cmd) | |
c0fec7f5 JC |
390 | { |
391 | } | |
392 | #endif | |
393 | ||
bd6f82d8 RC |
394 | /* |
395 | * Hangcheck detection for locked gpu: | |
396 | */ | |
397 | ||
f97decac JC |
398 | static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, |
399 | uint32_t fence) | |
400 | { | |
401 | struct msm_gem_submit *submit; | |
402 | ||
403 | list_for_each_entry(submit, &ring->submits, node) { | |
404 | if (submit->seqno > fence) | |
405 | break; | |
406 | ||
407 | msm_update_fence(submit->ring->fctx, | |
408 | submit->fence->seqno); | |
409 | } | |
410 | } | |
411 | ||
18bb8a6c RC |
412 | static struct msm_gem_submit * |
413 | find_submit(struct msm_ringbuffer *ring, uint32_t fence) | |
414 | { | |
415 | struct msm_gem_submit *submit; | |
416 | ||
417 | WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex)); | |
418 | ||
419 | list_for_each_entry(submit, &ring->submits, node) | |
420 | if (submit->seqno == fence) | |
421 | return submit; | |
422 | ||
423 | return NULL; | |
424 | } | |
425 | ||
b6295f9a | 426 | static void retire_submits(struct msm_gpu *gpu); |
1a370be9 | 427 | |
bd6f82d8 RC |
428 | static void recover_worker(struct work_struct *work) |
429 | { | |
430 | struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); | |
431 | struct drm_device *dev = gpu->dev; | |
96169f4e | 432 | struct msm_drm_private *priv = dev->dev_private; |
4816b626 | 433 | struct msm_gem_submit *submit; |
f97decac | 434 | struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); |
65a3c274 | 435 | char *comm = NULL, *cmd = NULL; |
f97decac JC |
436 | int i; |
437 | ||
bd6f82d8 | 438 | mutex_lock(&dev->struct_mutex); |
1a370be9 | 439 | |
6a41da17 | 440 | DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); |
f97decac | 441 | |
96169f4e | 442 | submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); |
18bb8a6c RC |
443 | if (submit) { |
444 | struct task_struct *task; | |
445 | ||
482f9632 | 446 | task = get_pid_task(submit->pid, PIDTYPE_PID); |
18bb8a6c | 447 | if (task) { |
482f9632 | 448 | comm = kstrdup(task->comm, GFP_KERNEL); |
18bb8a6c RC |
449 | |
450 | /* | |
451 | * So slightly annoying, in other paths like | |
452 | * mmap'ing gem buffers, mmap_sem is acquired | |
453 | * before struct_mutex, which means we can't | |
454 | * hold struct_mutex across the call to | |
455 | * get_cmdline(). But submits are retired | |
456 | * from the same in-order workqueue, so we can | |
457 | * safely drop the lock here without worrying | |
458 | * about the submit going away. | |
459 | */ | |
460 | mutex_unlock(&dev->struct_mutex); | |
482f9632 SM |
461 | cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); |
462 | put_task_struct(task); | |
18bb8a6c | 463 | mutex_lock(&dev->struct_mutex); |
65a3c274 | 464 | } |
18bb8a6c | 465 | |
65a3c274 | 466 | if (comm && cmd) { |
6a41da17 | 467 | DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", |
65a3c274 | 468 | gpu->name, comm, cmd); |
96169f4e RC |
469 | |
470 | msm_rd_dump_submit(priv->hangrd, submit, | |
65a3c274 JC |
471 | "offending task: %s (%s)", comm, cmd); |
472 | } else | |
96169f4e | 473 | msm_rd_dump_submit(priv->hangrd, submit, NULL); |
96169f4e RC |
474 | } |
475 | ||
c0fec7f5 JC |
476 | /* Record the crash state */ |
477 | pm_runtime_get_sync(&gpu->pdev->dev); | |
cdb95931 | 478 | msm_gpu_crashstate_capture(gpu, submit, comm, cmd); |
c0fec7f5 JC |
479 | pm_runtime_put_sync(&gpu->pdev->dev); |
480 | ||
65a3c274 JC |
481 | kfree(cmd); |
482 | kfree(comm); | |
96169f4e RC |
483 | |
484 | /* | |
485 | * Update all the rings with the latest and greatest fence.. this | |
486 | * needs to happen after msm_rd_dump_submit() to ensure that the | |
487 | * bo's referenced by the offending submit are still around. | |
488 | */ | |
7ddae82e | 489 | for (i = 0; i < gpu->nr_rings; i++) { |
96169f4e RC |
490 | struct msm_ringbuffer *ring = gpu->rb[i]; |
491 | ||
492 | uint32_t fence = ring->memptrs->fence; | |
18bb8a6c | 493 | |
96169f4e RC |
494 | /* |
495 | * For the current (faulting?) ring/submit advance the fence by | |
496 | * one more to clear the faulting submit | |
497 | */ | |
498 | if (ring == cur_ring) | |
499 | fence++; | |
500 | ||
501 | update_fences(gpu, ring, fence); | |
4816b626 RC |
502 | } |
503 | ||
504 | if (msm_gpu_active(gpu)) { | |
1a370be9 | 505 | /* retire completed submits, plus the one that hung: */ |
b6295f9a | 506 | retire_submits(gpu); |
1a370be9 | 507 | |
eeb75474 | 508 | pm_runtime_get_sync(&gpu->pdev->dev); |
37d77c3a | 509 | gpu->funcs->recover(gpu); |
eeb75474 | 510 | pm_runtime_put_sync(&gpu->pdev->dev); |
1a370be9 | 511 | |
f97decac JC |
512 | /* |
513 | * Replay all remaining submits starting with highest priority | |
514 | * ring | |
515 | */ | |
b1fc2839 | 516 | for (i = 0; i < gpu->nr_rings; i++) { |
f97decac JC |
517 | struct msm_ringbuffer *ring = gpu->rb[i]; |
518 | ||
519 | list_for_each_entry(submit, &ring->submits, node) | |
520 | gpu->funcs->submit(gpu, submit, NULL); | |
1a370be9 | 521 | } |
37d77c3a | 522 | } |
4816b626 | 523 | |
bd6f82d8 RC |
524 | mutex_unlock(&dev->struct_mutex); |
525 | ||
526 | msm_gpu_retire(gpu); | |
527 | } | |
528 | ||
529 | static void hangcheck_timer_reset(struct msm_gpu *gpu) | |
530 | { | |
531 | DBG("%s", gpu->name); | |
532 | mod_timer(&gpu->hangcheck_timer, | |
533 | round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); | |
534 | } | |
535 | ||
e99e88a9 | 536 | static void hangcheck_handler(struct timer_list *t) |
bd6f82d8 | 537 | { |
e99e88a9 | 538 | struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer); |
6b8819c8 RC |
539 | struct drm_device *dev = gpu->dev; |
540 | struct msm_drm_private *priv = dev->dev_private; | |
f97decac JC |
541 | struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); |
542 | uint32_t fence = ring->memptrs->fence; | |
bd6f82d8 | 543 | |
f97decac | 544 | if (fence != ring->hangcheck_fence) { |
bd6f82d8 | 545 | /* some progress has been made.. ya! */ |
f97decac JC |
546 | ring->hangcheck_fence = fence; |
547 | } else if (fence < ring->seqno) { | |
bd6f82d8 | 548 | /* no progress and not done.. hung! */ |
f97decac | 549 | ring->hangcheck_fence = fence; |
6a41da17 | 550 | DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", |
f97decac | 551 | gpu->name, ring->id); |
6a41da17 | 552 | DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", |
26791c48 | 553 | gpu->name, fence); |
6a41da17 | 554 | DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", |
f97decac JC |
555 | gpu->name, ring->seqno); |
556 | ||
bd6f82d8 RC |
557 | queue_work(priv->wq, &gpu->recover_work); |
558 | } | |
559 | ||
560 | /* if still more pending work, reset the hangcheck timer: */ | |
f97decac | 561 | if (ring->seqno > ring->hangcheck_fence) |
bd6f82d8 | 562 | hangcheck_timer_reset(gpu); |
6b8819c8 RC |
563 | |
564 | /* workaround for missing irq: */ | |
565 | queue_work(priv->wq, &gpu->retire_work); | |
bd6f82d8 RC |
566 | } |
567 | ||
70c70f09 RC |
568 | /* |
569 | * Performance Counters: | |
570 | */ | |
571 | ||
572 | /* called under perf_lock */ | |
573 | static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) | |
574 | { | |
575 | uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; | |
576 | int i, n = min(ncntrs, gpu->num_perfcntrs); | |
577 | ||
578 | /* read current values: */ | |
579 | for (i = 0; i < gpu->num_perfcntrs; i++) | |
580 | current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); | |
581 | ||
582 | /* update cntrs: */ | |
583 | for (i = 0; i < n; i++) | |
584 | cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; | |
585 | ||
586 | /* save current values: */ | |
587 | for (i = 0; i < gpu->num_perfcntrs; i++) | |
588 | gpu->last_cntrs[i] = current_cntrs[i]; | |
589 | ||
590 | return n; | |
591 | } | |
592 | ||
593 | static void update_sw_cntrs(struct msm_gpu *gpu) | |
594 | { | |
595 | ktime_t time; | |
596 | uint32_t elapsed; | |
597 | unsigned long flags; | |
598 | ||
599 | spin_lock_irqsave(&gpu->perf_lock, flags); | |
600 | if (!gpu->perfcntr_active) | |
601 | goto out; | |
602 | ||
603 | time = ktime_get(); | |
604 | elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); | |
605 | ||
606 | gpu->totaltime += elapsed; | |
607 | if (gpu->last_sample.active) | |
608 | gpu->activetime += elapsed; | |
609 | ||
610 | gpu->last_sample.active = msm_gpu_active(gpu); | |
611 | gpu->last_sample.time = time; | |
612 | ||
613 | out: | |
614 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
615 | } | |
616 | ||
617 | void msm_gpu_perfcntr_start(struct msm_gpu *gpu) | |
618 | { | |
619 | unsigned long flags; | |
620 | ||
eeb75474 RC |
621 | pm_runtime_get_sync(&gpu->pdev->dev); |
622 | ||
70c70f09 RC |
623 | spin_lock_irqsave(&gpu->perf_lock, flags); |
624 | /* we could dynamically enable/disable perfcntr registers too.. */ | |
625 | gpu->last_sample.active = msm_gpu_active(gpu); | |
626 | gpu->last_sample.time = ktime_get(); | |
627 | gpu->activetime = gpu->totaltime = 0; | |
628 | gpu->perfcntr_active = true; | |
629 | update_hw_cntrs(gpu, 0, NULL); | |
630 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
631 | } | |
632 | ||
633 | void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) | |
634 | { | |
635 | gpu->perfcntr_active = false; | |
eeb75474 | 636 | pm_runtime_put_sync(&gpu->pdev->dev); |
70c70f09 RC |
637 | } |
638 | ||
639 | /* returns -errno or # of cntrs sampled */ | |
640 | int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, | |
641 | uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) | |
642 | { | |
643 | unsigned long flags; | |
644 | int ret; | |
645 | ||
646 | spin_lock_irqsave(&gpu->perf_lock, flags); | |
647 | ||
648 | if (!gpu->perfcntr_active) { | |
649 | ret = -EINVAL; | |
650 | goto out; | |
651 | } | |
652 | ||
653 | *activetime = gpu->activetime; | |
654 | *totaltime = gpu->totaltime; | |
655 | ||
656 | gpu->activetime = gpu->totaltime = 0; | |
657 | ||
658 | ret = update_hw_cntrs(gpu, ncntrs, cntrs); | |
659 | ||
660 | out: | |
661 | spin_unlock_irqrestore(&gpu->perf_lock, flags); | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
7198e6b0 RC |
666 | /* |
667 | * Cmdstream submission/retirement: | |
668 | */ | |
669 | ||
4241db42 JC |
670 | static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, |
671 | struct msm_gem_submit *submit) | |
7d12a279 | 672 | { |
4241db42 JC |
673 | int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; |
674 | volatile struct msm_gpu_submit_stats *stats; | |
675 | u64 elapsed, clock = 0; | |
7d12a279 RC |
676 | int i; |
677 | ||
4241db42 JC |
678 | stats = &ring->memptrs->stats[index]; |
679 | /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ | |
680 | elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; | |
681 | do_div(elapsed, 192); | |
682 | ||
683 | /* Calculate the clock frequency from the number of CP cycles */ | |
684 | if (elapsed) { | |
685 | clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000; | |
686 | do_div(clock, elapsed); | |
687 | } | |
688 | ||
689 | trace_msm_gpu_submit_retired(submit, elapsed, clock, | |
690 | stats->alwayson_start, stats->alwayson_end); | |
691 | ||
7d12a279 RC |
692 | for (i = 0; i < submit->nr_bos; i++) { |
693 | struct msm_gem_object *msm_obj = submit->bos[i].obj; | |
694 | /* move to inactive: */ | |
695 | msm_gem_move_to_inactive(&msm_obj->base); | |
7ad0e8cf | 696 | msm_gem_unpin_iova(&msm_obj->base, gpu->aspace); |
dc9a9b32 | 697 | drm_gem_object_put(&msm_obj->base); |
7d12a279 RC |
698 | } |
699 | ||
eeb75474 RC |
700 | pm_runtime_mark_last_busy(&gpu->pdev->dev); |
701 | pm_runtime_put_autosuspend(&gpu->pdev->dev); | |
40e6815b | 702 | msm_gem_submit_free(submit); |
7d12a279 RC |
703 | } |
704 | ||
b6295f9a | 705 | static void retire_submits(struct msm_gpu *gpu) |
1a370be9 RC |
706 | { |
707 | struct drm_device *dev = gpu->dev; | |
f97decac JC |
708 | struct msm_gem_submit *submit, *tmp; |
709 | int i; | |
1a370be9 RC |
710 | |
711 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
712 | ||
f97decac | 713 | /* Retire the commits starting with highest priority */ |
b1fc2839 | 714 | for (i = 0; i < gpu->nr_rings; i++) { |
f97decac | 715 | struct msm_ringbuffer *ring = gpu->rb[i]; |
1a370be9 | 716 | |
f97decac JC |
717 | list_for_each_entry_safe(submit, tmp, &ring->submits, node) { |
718 | if (dma_fence_is_signaled(submit->fence)) | |
4241db42 | 719 | retire_submit(gpu, ring, submit); |
1a370be9 RC |
720 | } |
721 | } | |
722 | } | |
723 | ||
7198e6b0 RC |
724 | static void retire_worker(struct work_struct *work) |
725 | { | |
726 | struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); | |
727 | struct drm_device *dev = gpu->dev; | |
f97decac | 728 | int i; |
7198e6b0 | 729 | |
f97decac JC |
730 | for (i = 0; i < gpu->nr_rings; i++) |
731 | update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); | |
edd4fc63 | 732 | |
7198e6b0 | 733 | mutex_lock(&dev->struct_mutex); |
b6295f9a | 734 | retire_submits(gpu); |
7198e6b0 RC |
735 | mutex_unlock(&dev->struct_mutex); |
736 | } | |
737 | ||
738 | /* call from irq handler to schedule work to retire bo's */ | |
739 | void msm_gpu_retire(struct msm_gpu *gpu) | |
740 | { | |
741 | struct msm_drm_private *priv = gpu->dev->dev_private; | |
742 | queue_work(priv->wq, &gpu->retire_work); | |
70c70f09 | 743 | update_sw_cntrs(gpu); |
7198e6b0 RC |
744 | } |
745 | ||
746 | /* add bo's to gpu's ring, and kick gpu: */ | |
f44d32c7 | 747 | void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, |
7198e6b0 RC |
748 | struct msm_file_private *ctx) |
749 | { | |
750 | struct drm_device *dev = gpu->dev; | |
751 | struct msm_drm_private *priv = dev->dev_private; | |
f97decac | 752 | struct msm_ringbuffer *ring = submit->ring; |
f44d32c7 | 753 | int i; |
7198e6b0 | 754 | |
1a370be9 RC |
755 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
756 | ||
eeb75474 RC |
757 | pm_runtime_get_sync(&gpu->pdev->dev); |
758 | ||
759 | msm_gpu_hw_init(gpu); | |
37d77c3a | 760 | |
f97decac JC |
761 | submit->seqno = ++ring->seqno; |
762 | ||
763 | list_add_tail(&submit->node, &ring->submits); | |
1a370be9 | 764 | |
998b9a58 | 765 | msm_rd_dump_submit(priv->rd, submit, NULL); |
a7d3c950 | 766 | |
70c70f09 RC |
767 | update_sw_cntrs(gpu); |
768 | ||
7198e6b0 RC |
769 | for (i = 0; i < submit->nr_bos; i++) { |
770 | struct msm_gem_object *msm_obj = submit->bos[i].obj; | |
78babc16 | 771 | uint64_t iova; |
7198e6b0 RC |
772 | |
773 | /* can't happen yet.. but when we add 2d support we'll have | |
774 | * to deal w/ cross-ring synchronization: | |
775 | */ | |
776 | WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu)); | |
777 | ||
7d12a279 | 778 | /* submit takes a reference to the bo and iova until retired: */ |
dc9a9b32 | 779 | drm_gem_object_get(&msm_obj->base); |
9fe041f6 | 780 | msm_gem_get_and_pin_iova(&msm_obj->base, |
8bdcd949 | 781 | submit->gpu->aspace, &iova); |
7198e6b0 | 782 | |
bf6811f3 RC |
783 | if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) |
784 | msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence); | |
b6295f9a RC |
785 | else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ) |
786 | msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence); | |
7198e6b0 | 787 | } |
1a370be9 | 788 | |
1193c3bc | 789 | gpu->funcs->submit(gpu, submit, ctx); |
1a370be9 RC |
790 | priv->lastctx = ctx; |
791 | ||
bd6f82d8 | 792 | hangcheck_timer_reset(gpu); |
7198e6b0 RC |
793 | } |
794 | ||
795 | /* | |
796 | * Init/Cleanup: | |
797 | */ | |
798 | ||
799 | static irqreturn_t irq_handler(int irq, void *data) | |
800 | { | |
801 | struct msm_gpu *gpu = data; | |
802 | return gpu->funcs->irq(gpu); | |
803 | } | |
804 | ||
98db803f JC |
805 | static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) |
806 | { | |
8e54eea5 | 807 | int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks); |
98db803f | 808 | |
8e54eea5 | 809 | if (ret < 1) { |
98db803f | 810 | gpu->nr_clocks = 0; |
8e54eea5 | 811 | return ret; |
9d20a0e6 | 812 | } |
98db803f | 813 | |
8e54eea5 | 814 | gpu->nr_clocks = ret; |
98db803f | 815 | |
8e54eea5 JC |
816 | gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, |
817 | gpu->nr_clocks, "core"); | |
98db803f | 818 | |
8e54eea5 JC |
819 | gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, |
820 | gpu->nr_clocks, "rbbmtimer"); | |
98db803f JC |
821 | |
822 | return 0; | |
823 | } | |
7198e6b0 | 824 | |
1267a4df JC |
825 | static struct msm_gem_address_space * |
826 | msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, | |
827 | uint64_t va_start, uint64_t va_end) | |
828 | { | |
1267a4df JC |
829 | struct msm_gem_address_space *aspace; |
830 | int ret; | |
831 | ||
832 | /* | |
833 | * Setup IOMMU.. eventually we will (I think) do this once per context | |
834 | * and have separate page tables per context. For now, to keep things | |
835 | * simple and to get something working, just use a single address space: | |
836 | */ | |
c2052a4e JM |
837 | if (!adreno_is_a2xx(to_adreno_gpu(gpu))) { |
838 | struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type); | |
839 | if (!iommu) | |
840 | return NULL; | |
841 | ||
842 | iommu->geometry.aperture_start = va_start; | |
843 | iommu->geometry.aperture_end = va_end; | |
844 | ||
845 | DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); | |
846 | ||
847 | aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); | |
848 | if (IS_ERR(aspace)) | |
849 | iommu_domain_free(iommu); | |
850 | } else { | |
851 | aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu", | |
852 | va_start, va_end); | |
853 | } | |
1267a4df | 854 | |
1267a4df | 855 | if (IS_ERR(aspace)) { |
c2052a4e | 856 | DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n", |
1267a4df | 857 | PTR_ERR(aspace)); |
1267a4df JC |
858 | return ERR_CAST(aspace); |
859 | } | |
860 | ||
861 | ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); | |
862 | if (ret) { | |
863 | msm_gem_address_space_put(aspace); | |
864 | return ERR_PTR(ret); | |
865 | } | |
866 | ||
867 | return aspace; | |
868 | } | |
869 | ||
7198e6b0 RC |
870 | int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, |
871 | struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, | |
5770fc7a | 872 | const char *name, struct msm_gpu_config *config) |
7198e6b0 | 873 | { |
f97decac JC |
874 | int i, ret, nr_rings = config->nr_rings; |
875 | void *memptrs; | |
876 | uint64_t memptrs_iova; | |
7198e6b0 | 877 | |
70c70f09 RC |
878 | if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) |
879 | gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); | |
880 | ||
7198e6b0 RC |
881 | gpu->dev = drm; |
882 | gpu->funcs = funcs; | |
883 | gpu->name = name; | |
884 | ||
885 | INIT_LIST_HEAD(&gpu->active_list); | |
886 | INIT_WORK(&gpu->retire_work, retire_worker); | |
bd6f82d8 RC |
887 | INIT_WORK(&gpu->recover_work, recover_worker); |
888 | ||
1a370be9 | 889 | |
e99e88a9 | 890 | timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); |
7198e6b0 | 891 | |
70c70f09 RC |
892 | spin_lock_init(&gpu->perf_lock); |
893 | ||
7198e6b0 RC |
894 | |
895 | /* Map registers: */ | |
5770fc7a | 896 | gpu->mmio = msm_ioremap(pdev, config->ioname, name); |
7198e6b0 RC |
897 | if (IS_ERR(gpu->mmio)) { |
898 | ret = PTR_ERR(gpu->mmio); | |
899 | goto fail; | |
900 | } | |
901 | ||
902 | /* Get Interrupt: */ | |
878411ae | 903 | gpu->irq = platform_get_irq(pdev, 0); |
7198e6b0 RC |
904 | if (gpu->irq < 0) { |
905 | ret = gpu->irq; | |
6a41da17 | 906 | DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); |
7198e6b0 RC |
907 | goto fail; |
908 | } | |
909 | ||
910 | ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, | |
911 | IRQF_TRIGGER_HIGH, gpu->name, gpu); | |
912 | if (ret) { | |
6a41da17 | 913 | DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); |
7198e6b0 RC |
914 | goto fail; |
915 | } | |
916 | ||
98db803f JC |
917 | ret = get_clocks(pdev, gpu); |
918 | if (ret) | |
919 | goto fail; | |
7198e6b0 | 920 | |
720c3bb8 | 921 | gpu->ebi1_clk = msm_clk_get(pdev, "bus"); |
7198e6b0 RC |
922 | DBG("ebi1_clk: %p", gpu->ebi1_clk); |
923 | if (IS_ERR(gpu->ebi1_clk)) | |
924 | gpu->ebi1_clk = NULL; | |
925 | ||
926 | /* Acquire regulators: */ | |
927 | gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); | |
928 | DBG("gpu_reg: %p", gpu->gpu_reg); | |
929 | if (IS_ERR(gpu->gpu_reg)) | |
930 | gpu->gpu_reg = NULL; | |
931 | ||
932 | gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); | |
933 | DBG("gpu_cx: %p", gpu->gpu_cx); | |
934 | if (IS_ERR(gpu->gpu_cx)) | |
935 | gpu->gpu_cx = NULL; | |
936 | ||
1267a4df JC |
937 | gpu->pdev = pdev; |
938 | platform_set_drvdata(pdev, gpu); | |
939 | ||
f91c14ab JC |
940 | msm_devfreq_init(gpu); |
941 | ||
1267a4df JC |
942 | gpu->aspace = msm_gpu_create_address_space(gpu, pdev, |
943 | config->va_start, config->va_end); | |
944 | ||
945 | if (gpu->aspace == NULL) | |
6a41da17 | 946 | DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); |
1267a4df JC |
947 | else if (IS_ERR(gpu->aspace)) { |
948 | ret = PTR_ERR(gpu->aspace); | |
949 | goto fail; | |
7198e6b0 | 950 | } |
a1ad3523 | 951 | |
546ec7b4 JC |
952 | memptrs = msm_gem_kernel_new(drm, |
953 | sizeof(struct msm_rbmemptrs) * nr_rings, | |
cd414f3d | 954 | MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo, |
f97decac | 955 | &memptrs_iova); |
cd414f3d | 956 | |
f97decac JC |
957 | if (IS_ERR(memptrs)) { |
958 | ret = PTR_ERR(memptrs); | |
6a41da17 | 959 | DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); |
cd414f3d JC |
960 | goto fail; |
961 | } | |
962 | ||
0815d774 JC |
963 | msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); |
964 | ||
f97decac | 965 | if (nr_rings > ARRAY_SIZE(gpu->rb)) { |
39ae0d3e | 966 | DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", |
f97decac JC |
967 | ARRAY_SIZE(gpu->rb)); |
968 | nr_rings = ARRAY_SIZE(gpu->rb); | |
7198e6b0 RC |
969 | } |
970 | ||
f97decac JC |
971 | /* Create ringbuffer(s): */ |
972 | for (i = 0; i < nr_rings; i++) { | |
973 | gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); | |
974 | ||
975 | if (IS_ERR(gpu->rb[i])) { | |
976 | ret = PTR_ERR(gpu->rb[i]); | |
6a41da17 | 977 | DRM_DEV_ERROR(drm->dev, |
f97decac JC |
978 | "could not create ringbuffer %d: %d\n", i, ret); |
979 | goto fail; | |
980 | } | |
981 | ||
982 | memptrs += sizeof(struct msm_rbmemptrs); | |
983 | memptrs_iova += sizeof(struct msm_rbmemptrs); | |
984 | } | |
985 | ||
986 | gpu->nr_rings = nr_rings; | |
987 | ||
7198e6b0 RC |
988 | return 0; |
989 | ||
990 | fail: | |
f97decac JC |
991 | for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { |
992 | msm_ringbuffer_destroy(gpu->rb[i]); | |
993 | gpu->rb[i] = NULL; | |
994 | } | |
995 | ||
1e29dff0 | 996 | msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); |
cd414f3d | 997 | |
1267a4df | 998 | platform_set_drvdata(pdev, NULL); |
7198e6b0 RC |
999 | return ret; |
1000 | } | |
1001 | ||
1002 | void msm_gpu_cleanup(struct msm_gpu *gpu) | |
1003 | { | |
f97decac JC |
1004 | int i; |
1005 | ||
7198e6b0 RC |
1006 | DBG("%s", gpu->name); |
1007 | ||
1008 | WARN_ON(!list_empty(&gpu->active_list)); | |
1009 | ||
f97decac JC |
1010 | for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { |
1011 | msm_ringbuffer_destroy(gpu->rb[i]); | |
1012 | gpu->rb[i] = NULL; | |
7198e6b0 | 1013 | } |
cd414f3d | 1014 | |
1e29dff0 | 1015 | msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false); |
cd414f3d JC |
1016 | |
1017 | if (!IS_ERR_OR_NULL(gpu->aspace)) { | |
1267a4df JC |
1018 | gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, |
1019 | NULL, 0); | |
1020 | msm_gem_address_space_put(gpu->aspace); | |
1021 | } | |
7198e6b0 | 1022 | } |