[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / nouveau / core / engine / device / base.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/object.h>
#include <core/device.h>
#include <core/client.h>
#include <core/option.h>

#include <core/class.h>

#include "priv.h"
#include "acpi.h"

static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);

struct nouveau_device *
nouveau_device_find(u64 name)
{
	struct nouveau_device *device, *match = NULL;
	mutex_lock(&nv_devices_mutex);
	list_for_each_entry(device, &nv_devices, head) {
		if (device->handle == name) {
			match = device;
			break;
		}
	}
	mutex_unlock(&nv_devices_mutex);
	return match;
}

/******************************************************************************
 * nouveau_devobj (0x0080): class implementation
 *****************************************************************************/
struct nouveau_devobj {
	struct nouveau_parent base;
	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
};

static const u64 disable_map[] = {
	[NVDEV_SUBDEV_VBIOS]	= NV_DEVICE_DISABLE_VBIOS,
	[NVDEV_SUBDEV_DEVINIT]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_GPIO]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_I2C]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_CLOCK]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_MXM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_MC]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_BUS]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_TIMER]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_FB]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_LTCG]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_IBUS]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_INSTMEM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_VM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_SUBDEV_PWR]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_ENGINE_DMAOBJ]	= NV_DEVICE_DISABLE_CORE,
	[NVDEV_ENGINE_PERFMON]  = NV_DEVICE_DISABLE_CORE,
	[NVDEV_ENGINE_FIFO]	= NV_DEVICE_DISABLE_FIFO,
	[NVDEV_ENGINE_SW]	= NV_DEVICE_DISABLE_FIFO,
	[NVDEV_ENGINE_GR]	= NV_DEVICE_DISABLE_GRAPH,
	[NVDEV_ENGINE_MPEG]	= NV_DEVICE_DISABLE_MPEG,
	[NVDEV_ENGINE_ME]	= NV_DEVICE_DISABLE_ME,
	[NVDEV_ENGINE_VP]	= NV_DEVICE_DISABLE_VP,
	[NVDEV_ENGINE_CRYPT]	= NV_DEVICE_DISABLE_CRYPT,
	[NVDEV_ENGINE_BSP]	= NV_DEVICE_DISABLE_BSP,
	[NVDEV_ENGINE_PPP]	= NV_DEVICE_DISABLE_PPP,
	[NVDEV_ENGINE_COPY0]	= NV_DEVICE_DISABLE_COPY0,
	[NVDEV_ENGINE_COPY1]	= NV_DEVICE_DISABLE_COPY1,
	[NVDEV_ENGINE_VIC]	= NV_DEVICE_DISABLE_VIC,
	[NVDEV_ENGINE_VENC]	= NV_DEVICE_DISABLE_VENC,
	[NVDEV_ENGINE_DISP]	= NV_DEVICE_DISABLE_DISP,
	[NVDEV_SUBDEV_NR]	= 0,
};

static int
nouveau_devobj_ctor(struct nouveau_object *parent,
		    struct nouveau_object *engine,
		    struct nouveau_oclass *oclass, void *data, u32 size,
		    struct nouveau_object **pobject)
{
	struct nouveau_client *client = nv_client(parent);
	struct nouveau_device *device;
	struct nouveau_devobj *devobj;
	struct nv_device_class *args = data;
	u32 boot0, strap;
	u64 disable, mmio_base, mmio_size;
	void __iomem *map;
	int ret, i, c;

	if (size < sizeof(struct nv_device_class))
		return -EINVAL;

	/* find the device subdev that matches what the client requested */
	device = nv_device(client->device);
	if (args->device != ~0) {
		device = nouveau_device_find(args->device);
		if (!device)
			return -ENODEV;
	}

	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
				    nouveau_control_oclass,
				    (1ULL << NVDEV_ENGINE_DMAOBJ) |
				    (1ULL << NVDEV_ENGINE_FIFO) |
				    (1ULL << NVDEV_ENGINE_DISP) |
				    (1ULL << NVDEV_ENGINE_PERFMON), &devobj);
	*pobject = nv_object(devobj);
	if (ret)
		return ret;

	mmio_base = nv_device_resource_start(device, 0);
	mmio_size = nv_device_resource_len(device, 0);

	/* translate api disable mask into internal mapping */
	disable = args->debug0;
	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
		if (args->disable & disable_map[i])
			disable |= (1ULL << i);
	}

	/* identify the chipset, and determine classes of subdev/engines */
	if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
	    !device->card_type) {
		map = ioremap(mmio_base, 0x102000);
		if (map == NULL)
			return -ENOMEM;

		/* switch mmio to cpu's native endianness */
#ifndef __BIG_ENDIAN
		if (ioread32_native(map + 0x000004) != 0x00000000)
#else
		if (ioread32_native(map + 0x000004) == 0x00000000)
#endif
			iowrite32_native(0x01000001, map + 0x000004);

		/* read boot0 and strapping information */
		boot0 = ioread32_native(map + 0x000000);
		strap = ioread32_native(map + 0x101000);
		iounmap(map);

		/* determine chipset and derive architecture from it */
		if ((boot0 & 0x1f000000) > 0) {
			device->chipset = (boot0 & 0x1ff00000) >> 20;
			switch (device->chipset & 0x1f0) {
			case 0x010: {
				if (0x461 & (1 << (device->chipset & 0xf)))
					device->card_type = NV_10;
				else
					device->card_type = NV_11;
				break;
			}
			case 0x020: device->card_type = NV_20; break;
			case 0x030: device->card_type = NV_30; break;
			case 0x040:
			case 0x060: device->card_type = NV_40; break;
			case 0x050:
			case 0x080:
			case 0x090:
			case 0x0a0: device->card_type = NV_50; break;
			case 0x0c0: device->card_type = NV_C0; break;
			case 0x0d0: device->card_type = NV_D0; break;
			case 0x0e0:
			case 0x0f0:
			case 0x100: device->card_type = NV_E0; break;
			case 0x110: device->card_type = GM100; break;
			default:
				break;
			}
		} else
		if ((boot0 & 0xff00fff0) == 0x20004000) {
			if (boot0 & 0x00f00000)
				device->chipset = 0x05;
			else
				device->chipset = 0x04;
			device->card_type = NV_04;
		}

		switch (device->card_type) {
		case NV_04: ret = nv04_identify(device); break;
		case NV_10:
		case NV_11: ret = nv10_identify(device); break;
		case NV_20: ret = nv20_identify(device); break;
		case NV_30: ret = nv30_identify(device); break;
		case NV_40: ret = nv40_identify(device); break;
		case NV_50: ret = nv50_identify(device); break;
		case NV_C0:
		case NV_D0: ret = nvc0_identify(device); break;
		case NV_E0: ret = nve0_identify(device); break;
		case GM100: ret = gm100_identify(device); break;
		default:
			ret = -EINVAL;
			break;
		}

		if (ret) {
			nv_error(device, "unknown chipset, 0x%08x\n", boot0);
			return ret;
		}

		nv_info(device, "BOOT0  : 0x%08x\n", boot0);
		nv_info(device, "Chipset: %s (NV%02X)\n",
			device->cname, device->chipset);
		nv_info(device, "Family : NV%02X\n", device->card_type);

		/* determine frequency of timing crystal */
		if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
		    (device->chipset >= 0x20 && device->chipset < 0x25))
			strap &= 0x00000040;
		else
			strap &= 0x00400040;

		switch (strap) {
		case 0x00000000: device->crystal = 13500; break;
		case 0x00000040: device->crystal = 14318; break;
		case 0x00400000: device->crystal = 27000; break;
		case 0x00400040: device->crystal = 25000; break;
		}

		nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
	}

	if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
	    !nv_subdev(device)->mmio) {
		nv_subdev(device)->mmio  = ioremap(mmio_base, mmio_size);
		if (!nv_subdev(device)->mmio) {
			nv_error(device, "unable to map device registers\n");
			return -ENOMEM;
		}
	}

	/* ensure requested subsystems are available for use */
	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
		if (!(oclass = device->oclass[i]) || (disable & (1ULL << i)))
			continue;

		if (device->subdev[i]) {
			nouveau_object_ref(device->subdev[i],
					  &devobj->subdev[i]);
			continue;
		}

		ret = nouveau_object_ctor(nv_object(device), NULL,
					  oclass, NULL, i,
					  &devobj->subdev[i]);
		if (ret == -ENODEV)
			continue;
		if (ret)
			return ret;

		device->subdev[i] = devobj->subdev[i];

		/* note: can't init *any* subdevs until devinit has been run
		 * due to not knowing exactly what the vbios init tables will
		 * mess with.  devinit also can't be run until all of its
		 * dependencies have been created.
		 *
		 * this code delays init of any subdev until all of devinit's
		 * dependencies have been created, and then initialises each
		 * subdev in turn as they're created.
		 */
		while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
			struct nouveau_object *subdev = devobj->subdev[c++];
			if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret)
					return ret;
				atomic_dec(&nv_object(device)->usecount);
			} else
			if (subdev) {
				nouveau_subdev_reset(subdev);
			}
		}
	}

	return 0;
}

static void
nouveau_devobj_dtor(struct nouveau_object *object)
{
	struct nouveau_devobj *devobj = (void *)object;
	int i;

	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
		nouveau_object_ref(NULL, &devobj->subdev[i]);

	nouveau_parent_destroy(&devobj->base);
}

static u8
nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
{
	return nv_rd08(object->engine, addr);
}

static u16
nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
{
	return nv_rd16(object->engine, addr);
}

static u32
nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
{
	return nv_rd32(object->engine, addr);
}

static void
nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
{
	nv_wr08(object->engine, addr, data);
}

static void
nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
{
	nv_wr16(object->engine, addr, data);
}

static void
nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
{
	nv_wr32(object->engine, addr, data);
}

static struct nouveau_ofuncs
nouveau_devobj_ofuncs = {
	.ctor = nouveau_devobj_ctor,
	.dtor = nouveau_devobj_dtor,
	.init = _nouveau_parent_init,
	.fini = _nouveau_parent_fini,
	.rd08 = nouveau_devobj_rd08,
	.rd16 = nouveau_devobj_rd16,
	.rd32 = nouveau_devobj_rd32,
	.wr08 = nouveau_devobj_wr08,
	.wr16 = nouveau_devobj_wr16,
	.wr32 = nouveau_devobj_wr32,
};

/******************************************************************************
 * nouveau_device: engine functions
 *****************************************************************************/
static struct nouveau_oclass
nouveau_device_sclass[] = {
	{ 0x0080, &nouveau_devobj_ofuncs },
	{}
};

static int
nouveau_device_fini(struct nouveau_object *object, bool suspend)
{
	struct nouveau_device *device = (void *)object;
	struct nouveau_object *subdev;
	int ret, i;

	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_dec(subdev, suspend);
				if (ret && suspend)
					goto fail;
			}
		}
	}

	ret = nvkm_acpi_fini(device, suspend);
fail:
	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret) {
					/* XXX */
				}
			}
		}
	}

	return ret;
}

static int
nouveau_device_init(struct nouveau_object *object)
{
	struct nouveau_device *device = (void *)object;
	struct nouveau_object *subdev;
	int ret, i = 0;

	ret = nvkm_acpi_init(device);
	if (ret)
		goto fail;

	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
				ret = nouveau_object_inc(subdev);
				if (ret)
					goto fail;
			} else {
				nouveau_subdev_reset(subdev);
			}
		}
	}

	ret = 0;
fail:
	for (--i; ret && i >= 0; i--) {
		if ((subdev = device->subdev[i])) {
			if (!nv_iclass(subdev, NV_ENGINE_CLASS))
				nouveau_object_dec(subdev, false);
		}
	}

	if (ret)
		nvkm_acpi_fini(device, false);
	return ret;
}

static void
nouveau_device_dtor(struct nouveau_object *object)
{
	struct nouveau_device *device = (void *)object;

	nouveau_event_destroy(&device->ntfy);

	mutex_lock(&nv_devices_mutex);
	list_del(&device->head);
	mutex_unlock(&nv_devices_mutex);

	if (nv_subdev(device)->mmio)
		iounmap(nv_subdev(device)->mmio);

	nouveau_engine_destroy(&device->base);
}

resource_size_t
nv_device_resource_start(struct nouveau_device *device, unsigned int bar)
{
	if (nv_device_is_pci(device)) {
		return pci_resource_start(device->pdev, bar);
	} else {
		struct resource *res;
		res = platform_get_resource(device->platformdev,
					    IORESOURCE_MEM, bar);
		if (!res)
			return 0;
		return res->start;
	}
}

resource_size_t
nv_device_resource_len(struct nouveau_device *device, unsigned int bar)
{
	if (nv_device_is_pci(device)) {
		return pci_resource_len(device->pdev, bar);
	} else {
		struct resource *res;
		res = platform_get_resource(device->platformdev,
					    IORESOURCE_MEM, bar);
		if (!res)
			return 0;
		return resource_size(res);
	}
}

int
nv_device_get_irq(struct nouveau_device *device, bool stall)
{
	if (nv_device_is_pci(device)) {
		return device->pdev->irq;
	} else {
		return platform_get_irq_byname(device->platformdev,
					       stall ? "stall" : "nonstall");
	}
}

static struct nouveau_oclass
nouveau_device_oclass = {
	.handle = NV_ENGINE(DEVICE, 0x00),
	.ofuncs = &(struct nouveau_ofuncs) {
		.dtor = nouveau_device_dtor,
		.init = nouveau_device_init,
		.fini = nouveau_device_fini,
	},
};

int
nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
		       const char *sname, const char *cfg, const char *dbg,
		       int length, void **pobject)
{
	struct nouveau_device *device;
	int ret = -EEXIST;

	mutex_lock(&nv_devices_mutex);
	list_for_each_entry(device, &nv_devices, head) {
		if (device->handle == name)
			goto done;
	}

	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
				     "DEVICE", "device", length, pobject);
	device = *pobject;
	if (ret)
		goto done;

	switch (type) {
	case NOUVEAU_BUS_PCI:
		device->pdev = dev;
		break;
	case NOUVEAU_BUS_PLATFORM:
		device->platformdev = dev;
		break;
	}
	device->handle = name;
	device->cfgopt = cfg;
	device->dbgopt = dbg;
	device->name = sname;

	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
	nv_engine(device)->sclass = nouveau_device_sclass;
	list_add(&device->head, &nv_devices);

	ret = nouveau_event_create(1, NVKM_DEVICE_NTFY, &device->ntfy);
done:
	mutex_unlock(&nv_devices_mutex);
	return ret;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <core/object.h>
	26	#include <core/device.h>
	27	#include <core/client.h>
9274f4a9 BS	28	#include <core/option.h>
	29
	30	#include <core/class.h>
	31
9838366c	32	#include "priv.h"
ed76a870	33	#include "acpi.h"
9274f4a9 BS	34
	35	static DEFINE_MUTEX(nv_devices_mutex);
	36	static LIST_HEAD(nv_devices);
	37
	38	struct nouveau_device *
	39	nouveau_device_find(u64 name)
	40	{
	41	struct nouveau_device device, match = NULL;
	42	mutex_lock(&nv_devices_mutex);
	43	list_for_each_entry(device, &nv_devices, head) {
	44	if (device->handle == name) {
	45	match = device;
	46	break;
	47	}
	48	}
	49	mutex_unlock(&nv_devices_mutex);
	50	return match;
	51	}
	52
	53	/******************************************************************************
	54	* nouveau_devobj (0x0080): class implementation
	55	*****************************************************************************/
	56	struct nouveau_devobj {
	57	struct nouveau_parent base;
	58	struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
9274f4a9 BS	59	};
	60
	61	static const u64 disable_map[] = {
	62	[NVDEV_SUBDEV_VBIOS] = NV_DEVICE_DISABLE_VBIOS,
206c38a9	63	[NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	64	[NVDEV_SUBDEV_GPIO] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	65	[NVDEV_SUBDEV_I2C] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	66	[NVDEV_SUBDEV_CLOCK] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	67	[NVDEV_SUBDEV_MXM] = NV_DEVICE_DISABLE_CORE,
9274f4a9	68	[NVDEV_SUBDEV_MC] = NV_DEVICE_DISABLE_CORE,
a10220bb	69	[NVDEV_SUBDEV_BUS] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	70	[NVDEV_SUBDEV_TIMER] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	71	[NVDEV_SUBDEV_FB] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	72	[NVDEV_SUBDEV_LTCG] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	73	[NVDEV_SUBDEV_IBUS] = NV_DEVICE_DISABLE_CORE,
9274f4a9	74	[NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_DISABLE_CORE,
206c38a9	75	[NVDEV_SUBDEV_VM] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	76	[NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE,
9274f4a9 BS	77	[NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE,
9274f4a9	78	[NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
ff4b42c7	79	[NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE,
9274f4a9	80	[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
aa4d7a4d	81	[NVDEV_ENGINE_PERFMON] = NV_DEVICE_DISABLE_CORE,
206c38a9 BS	82	[NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
206c38a9 BS	83	[NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
9274f4a9 BS	84	[NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH,
	85	[NVDEV_ENGINE_MPEG] = NV_DEVICE_DISABLE_MPEG,
	86	[NVDEV_ENGINE_ME] = NV_DEVICE_DISABLE_ME,
	87	[NVDEV_ENGINE_VP] = NV_DEVICE_DISABLE_VP,
	88	[NVDEV_ENGINE_CRYPT] = NV_DEVICE_DISABLE_CRYPT,
	89	[NVDEV_ENGINE_BSP] = NV_DEVICE_DISABLE_BSP,
	90	[NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP,
	91	[NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0,
	92	[NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1,
c42a7aec	93	[NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC,
206c38a9	94	[NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC,
9274f4a9 BS	95	[NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP,
	96	[NVDEV_SUBDEV_NR] = 0,
	97	};
	98
	99	static int
	100	nouveau_devobj_ctor(struct nouveau_object *parent,
	101	struct nouveau_object *engine,
	102	struct nouveau_oclass oclass, void data, u32 size,
	103	struct nouveau_object **pobject)
	104	{
	105	struct nouveau_client *client = nv_client(parent);
9274f4a9 BS	106	struct nouveau_device *device;
	107	struct nouveau_devobj *devobj;
	108	struct nv_device_class *args = data;
950fbfab MS	109	u32 boot0, strap;
950fbfab MS	110	u64 disable, mmio_base, mmio_size;
9274f4a9	111	void __iomem *map;
7234d023	112	int ret, i, c;
9274f4a9 BS	113
	114	if (size < sizeof(struct nv_device_class))
	115	return -EINVAL;
	116
	117	/* find the device subdev that matches what the client requested */
	118	device = nv_device(client->device);
	119	if (args->device != ~0) {
	120	device = nouveau_device_find(args->device);
	121	if (!device)
	122	return -ENODEV;
	123	}
	124
9838366c BS	125	ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
9838366c BS	126	nouveau_control_oclass,
9274f4a9 BS	127	(1ULL << NVDEV_ENGINE_DMAOBJ) \|
9274f4a9 BS	128	(1ULL << NVDEV_ENGINE_FIFO) \|
aa4d7a4d BS	129	(1ULL << NVDEV_ENGINE_DISP) \|
aa4d7a4d BS	130	(1ULL << NVDEV_ENGINE_PERFMON), &devobj);
9274f4a9 BS	131	*pobject = nv_object(devobj);
	132	if (ret)
	133	return ret;
	134
420b9469 AC	135	mmio_base = nv_device_resource_start(device, 0);
420b9469 AC	136	mmio_size = nv_device_resource_len(device, 0);
9274f4a9 BS	137
	138	/* translate api disable mask into internal mapping */
	139	disable = args->debug0;
	140	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
	141	if (args->disable & disable_map[i])
	142	disable \|= (1ULL << i);
	143	}
	144
	145	/* identify the chipset, and determine classes of subdev/engines */
	146	if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
	147	!device->card_type) {
	148	map = ioremap(mmio_base, 0x102000);
43b1e9c9 BS	149	if (map == NULL)
43b1e9c9 BS	150	return -ENOMEM;
9274f4a9 BS	151
	152	/* switch mmio to cpu's native endianness */
	153	#ifndef __BIG_ENDIAN
	154	if (ioread32_native(map + 0x000004) != 0x00000000)
	155	#else
	156	if (ioread32_native(map + 0x000004) == 0x00000000)
	157	#endif
	158	iowrite32_native(0x01000001, map + 0x000004);
	159
	160	/* read boot0 and strapping information */
	161	boot0 = ioread32_native(map + 0x000000);
	162	strap = ioread32_native(map + 0x101000);
	163	iounmap(map);
	164
	165	/* determine chipset and derive architecture from it */
dd5b84ac BS	166	if ((boot0 & 0x1f000000) > 0) {
	167	device->chipset = (boot0 & 0x1ff00000) >> 20;
	168	switch (device->chipset & 0x1f0) {
aabf19c2	169	case 0x010: {
4a0ff754 IM	170	if (0x461 & (1 << (device->chipset & 0xf)))
	171	device->card_type = NV_10;
	172	else
	173	device->card_type = NV_11;
	174	break;
	175	}
aabf19c2 BS	176	case 0x020: device->card_type = NV_20; break;
	177	case 0x030: device->card_type = NV_30; break;
	178	case 0x040:
	179	case 0x060: device->card_type = NV_40; break;
	180	case 0x050:
	181	case 0x080:
	182	case 0x090:
	183	case 0x0a0: device->card_type = NV_50; break;
	184	case 0x0c0: device->card_type = NV_C0; break;
	185	case 0x0d0: device->card_type = NV_D0; break;
	186	case 0x0e0:
	187	case 0x0f0:
	188	case 0x100: device->card_type = NV_E0; break;
3f204647	189	case 0x110: device->card_type = GM100; break;
9274f4a9 BS	190	default:
	191	break;
	192	}
	193	} else
	194	if ((boot0 & 0xff00fff0) == 0x20004000) {
	195	if (boot0 & 0x00f00000)
	196	device->chipset = 0x05;
	197	else
	198	device->chipset = 0x04;
	199	device->card_type = NV_04;
	200	}
	201
	202	switch (device->card_type) {
	203	case NV_04: ret = nv04_identify(device); break;
4a0ff754 IM	204	case NV_10:
4a0ff754 IM	205	case NV_11: ret = nv10_identify(device); break;
9274f4a9 BS	206	case NV_20: ret = nv20_identify(device); break;
	207	case NV_30: ret = nv30_identify(device); break;
	208	case NV_40: ret = nv40_identify(device); break;
	209	case NV_50: ret = nv50_identify(device); break;
	210	case NV_C0:
	211	case NV_D0: ret = nvc0_identify(device); break;
	212	case NV_E0: ret = nve0_identify(device); break;
3f204647	213	case GM100: ret = gm100_identify(device); break;
9274f4a9 BS	214	default:
	215	ret = -EINVAL;
	216	break;
	217	}
	218
	219	if (ret) {
	220	nv_error(device, "unknown chipset, 0x%08x\n", boot0);
	221	return ret;
	222	}
	223
	224	nv_info(device, "BOOT0 : 0x%08x\n", boot0);
2094dd82 BS	225	nv_info(device, "Chipset: %s (NV%02X)\n",
2094dd82 BS	226	device->cname, device->chipset);
9274f4a9 BS	227	nv_info(device, "Family : NV%02X\n", device->card_type);
	228
	229	/* determine frequency of timing crystal */
8aa816b0	230	if ( device->card_type <= NV_10 \|\| device->chipset < 0x17 \|\|
1f2285d4	231	(device->chipset >= 0x20 && device->chipset < 0x25))
9274f4a9 BS	232	strap &= 0x00000040;
	233	else
	234	strap &= 0x00400040;
	235
	236	switch (strap) {
	237	case 0x00000000: device->crystal = 13500; break;
	238	case 0x00000040: device->crystal = 14318; break;
	239	case 0x00400000: device->crystal = 27000; break;
	240	case 0x00400040: device->crystal = 25000; break;
	241	}
	242
	243	nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
	244	}
	245
	246	if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
	247	!nv_subdev(device)->mmio) {
	248	nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size);
	249	if (!nv_subdev(device)->mmio) {
	250	nv_error(device, "unable to map device registers\n");
43b1e9c9	251	return -ENOMEM;
9274f4a9 BS	252	}
	253	}
	254
	255	/* ensure requested subsystems are available for use */
10caad33	256	for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
9274f4a9 BS	257	if (!(oclass = device->oclass[i]) \|\| (disable & (1ULL << i)))
	258	continue;
	259
10caad33	260	if (device->subdev[i]) {
7234d023 BS	261	nouveau_object_ref(device->subdev[i],
7234d023 BS	262	&devobj->subdev[i]);
10caad33	263	continue;
9274f4a9 BS	264	}
9274f4a9 BS	265
10caad33 BS	266	ret = nouveau_object_ctor(nv_object(device), NULL,
	267	oclass, NULL, i,
	268	&devobj->subdev[i]);
	269	if (ret == -ENODEV)
	270	continue;
	271	if (ret)
	272	return ret;
	273
61b365a5 BS	274	device->subdev[i] = devobj->subdev[i];
61b365a5 BS	275
7234d023 BS	276	/* note: can't init any subdevs until devinit has been run
	277	* due to not knowing exactly what the vbios init tables will
	278	* mess with. devinit also can't be run until all of its
	279	* dependencies have been created.
	280	*
	281	* this code delays init of any subdev until all of devinit's
	282	* dependencies have been created, and then initialises each
	283	* subdev in turn as they're created.
	284	*/
	285	while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
	286	struct nouveau_object *subdev = devobj->subdev[c++];
	287	if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
	288	ret = nouveau_object_inc(subdev);
	289	if (ret)
	290	return ret;
10caad33 BS	291	atomic_dec(&nv_object(device)->usecount);
	292	} else
	293	if (subdev) {
	294	nouveau_subdev_reset(subdev);
9274f4a9 BS	295	}
9274f4a9 BS	296	}
9274f4a9 BS	297	}
	298
	299	return 0;
	300	}
	301
	302	static void
	303	nouveau_devobj_dtor(struct nouveau_object *object)
	304	{
	305	struct nouveau_devobj devobj = (void )object;
	306	int i;
	307
	308	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
	309	nouveau_object_ref(NULL, &devobj->subdev[i]);
	310
	311	nouveau_parent_destroy(&devobj->base);
	312	}
	313
9274f4a9	314	static u8
0a32241d	315	nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
9274f4a9 BS	316	{
	317	return nv_rd08(object->engine, addr);
	318	}
	319
	320	static u16
0a32241d	321	nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
9274f4a9 BS	322	{
	323	return nv_rd16(object->engine, addr);
	324	}
	325
	326	static u32
0a32241d	327	nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
9274f4a9 BS	328	{
	329	return nv_rd32(object->engine, addr);
	330	}
	331
	332	static void
0a32241d	333	nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
9274f4a9 BS	334	{
	335	nv_wr08(object->engine, addr, data);
	336	}
	337
	338	static void
0a32241d	339	nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
9274f4a9 BS	340	{
	341	nv_wr16(object->engine, addr, data);
	342	}
	343
	344	static void
0a32241d	345	nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
9274f4a9 BS	346	{
	347	nv_wr32(object->engine, addr, data);
	348	}
	349
	350	static struct nouveau_ofuncs
	351	nouveau_devobj_ofuncs = {
	352	.ctor = nouveau_devobj_ctor,
	353	.dtor = nouveau_devobj_dtor,
10caad33 BS	354	.init = _nouveau_parent_init,
10caad33 BS	355	.fini = _nouveau_parent_fini,
9274f4a9 BS	356	.rd08 = nouveau_devobj_rd08,
	357	.rd16 = nouveau_devobj_rd16,
	358	.rd32 = nouveau_devobj_rd32,
	359	.wr08 = nouveau_devobj_wr08,
	360	.wr16 = nouveau_devobj_wr16,
	361	.wr32 = nouveau_devobj_wr32,
	362	};
	363
	364	/******************************************************************************
	365	* nouveau_device: engine functions
	366	*****************************************************************************/
9aecbada	367	static struct nouveau_oclass
9274f4a9 BS	368	nouveau_device_sclass[] = {
	369	{ 0x0080, &nouveau_devobj_ofuncs },
	370	{}
	371	};
	372
066a5d09 BS	373	static int
	374	nouveau_device_fini(struct nouveau_object *object, bool suspend)
	375	{
	376	struct nouveau_device device = (void )object;
10caad33 BS	377	struct nouveau_object *subdev;
	378	int ret, i;
	379
	380	for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
	381	if ((subdev = device->subdev[i])) {
	382	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	383	ret = nouveau_object_dec(subdev, suspend);
	384	if (ret && suspend)
	385	goto fail;
	386	}
	387	}
	388	}
	389
ed76a870	390	ret = nvkm_acpi_fini(device, suspend);
10caad33 BS	391	fail:
	392	for (; ret && i < NVDEV_SUBDEV_NR; i++) {
	393	if ((subdev = device->subdev[i])) {
	394	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	395	ret = nouveau_object_inc(subdev);
	396	if (ret) {
	397	/* XXX */
	398	}
	399	}
	400	}
	401	}
	402
	403	return ret;
066a5d09 BS	404	}
	405
	406	static int
	407	nouveau_device_init(struct nouveau_object *object)
	408	{
	409	struct nouveau_device device = (void )object;
10caad33	410	struct nouveau_object *subdev;
ed76a870 BS	411	int ret, i = 0;
	412
	413	ret = nvkm_acpi_init(device);
	414	if (ret)
	415	goto fail;
10caad33 BS	416
	417	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
	418	if ((subdev = device->subdev[i])) {
	419	if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
	420	ret = nouveau_object_inc(subdev);
	421	if (ret)
	422	goto fail;
	423	} else {
	424	nouveau_subdev_reset(subdev);
	425	}
	426	}
	427	}
	428
	429	ret = 0;
	430	fail:
	431	for (--i; ret && i >= 0; i--) {
	432	if ((subdev = device->subdev[i])) {
	433	if (!nv_iclass(subdev, NV_ENGINE_CLASS))
	434	nouveau_object_dec(subdev, false);
	435	}
	436	}
	437
ed76a870 BS	438	if (ret)
ed76a870 BS	439	nvkm_acpi_fini(device, false);
10caad33	440	return ret;
066a5d09 BS	441	}
066a5d09 BS	442
ebb945a9 BS	443	static void
	444	nouveau_device_dtor(struct nouveau_object *object)
	445	{
	446	struct nouveau_device device = (void )object;
	447
ed76a870 BS	448	nouveau_event_destroy(&device->ntfy);
ed76a870 BS	449
ebb945a9 BS	450	mutex_lock(&nv_devices_mutex);
	451	list_del(&device->head);
	452	mutex_unlock(&nv_devices_mutex);
	453
dded35de BS	454	if (nv_subdev(device)->mmio)
dded35de BS	455	iounmap(nv_subdev(device)->mmio);
ebb945a9	456
dded35de	457	nouveau_engine_destroy(&device->base);
ebb945a9 BS	458	}
ebb945a9 BS	459
420b9469 AC	460	resource_size_t
	461	nv_device_resource_start(struct nouveau_device *device, unsigned int bar)
	462	{
	463	if (nv_device_is_pci(device)) {
	464	return pci_resource_start(device->pdev, bar);
	465	} else {
	466	struct resource *res;
	467	res = platform_get_resource(device->platformdev,
	468	IORESOURCE_MEM, bar);
	469	if (!res)
	470	return 0;
	471	return res->start;
	472	}
	473	}
	474
	475	resource_size_t
	476	nv_device_resource_len(struct nouveau_device *device, unsigned int bar)
	477	{
	478	if (nv_device_is_pci(device)) {
	479	return pci_resource_len(device->pdev, bar);
	480	} else {
	481	struct resource *res;
	482	res = platform_get_resource(device->platformdev,
	483	IORESOURCE_MEM, bar);
	484	if (!res)
	485	return 0;
	486	return resource_size(res);
	487	}
	488	}
	489
420b9469 AC	490	int
	491	nv_device_get_irq(struct nouveau_device *device, bool stall)
	492	{
	493	if (nv_device_is_pci(device)) {
	494	return device->pdev->irq;
	495	} else {
	496	return platform_get_irq_byname(device->platformdev,
	497	stall ? "stall" : "nonstall");
	498	}
	499	}
	500
9274f4a9 BS	501	static struct nouveau_oclass
9274f4a9 BS	502	nouveau_device_oclass = {
dded35de	503	.handle = NV_ENGINE(DEVICE, 0x00),
9274f4a9	504	.ofuncs = &(struct nouveau_ofuncs) {
ebb945a9	505	.dtor = nouveau_device_dtor,
066a5d09 BS	506	.init = nouveau_device_init,
066a5d09 BS	507	.fini = nouveau_device_fini,
9274f4a9 BS	508	},
	509	};
	510
	511	int
420b9469 AC	512	nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name,
420b9469 AC	513	const char sname, const char cfg, const char *dbg,
9274f4a9 BS	514	int length, void **pobject)
	515	{
	516	struct nouveau_device *device;
	517	int ret = -EEXIST;
	518
	519	mutex_lock(&nv_devices_mutex);
	520	list_for_each_entry(device, &nv_devices, head) {
	521	if (device->handle == name)
	522	goto done;
	523	}
	524
dded35de	525	ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
9274f4a9 BS	526	"DEVICE", "device", length, pobject);
	527	device = *pobject;
	528	if (ret)
	529	goto done;
	530
420b9469 AC	531	switch (type) {
	532	case NOUVEAU_BUS_PCI:
	533	device->pdev = dev;
	534	break;
	535	case NOUVEAU_BUS_PLATFORM:
	536	device->platformdev = dev;
	537	break;
	538	}
9274f4a9 BS	539	device->handle = name;
	540	device->cfgopt = cfg;
	541	device->dbgopt = dbg;
	542	device->name = sname;
	543
	544	nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
9aecbada	545	nv_engine(device)->sclass = nouveau_device_sclass;
9274f4a9	546	list_add(&device->head, &nv_devices);
ed76a870 BS	547
ed76a870 BS	548	ret = nouveau_event_create(1, NVKM_DEVICE_NTFY, &device->ntfy);
9274f4a9 BS	549	done:
	550	mutex_unlock(&nv_devices_mutex);
	551	return ret;
	552	}