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Merge tag 'pm+acpi-3.15-rc1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafae...
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / nouveau / core / engine / device / nv40.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
70c0f263 25#include <subdev/bios.h>
a10220bb
MP		 26#include <subdev/bus.h>
27#include <subdev/vm.h>
e0996aea 28#include <subdev/gpio.h>
4196faa8 29#include <subdev/i2c.h>
8aceb7de 30#include <subdev/clock.h>
aa1b9b48 31#include <subdev/therm.h>
cb75d97e 32#include <subdev/devinit.h>
7d9115de 33#include <subdev/mc.h>
5a5c7432 34#include <subdev/timer.h>
861d2107 35#include <subdev/fb.h>
3863c9bc
BS		 36#include <subdev/instmem.h>
37#include <subdev/vm.h>
c9c0ccae 38#include <subdev/volt.h>
9274f4a9 39
dded35de 40#include <engine/device.h>
ebb945a9
BS		 41#include <engine/dmaobj.h>
42#include <engine/fifo.h>
43#include <engine/software.h>
44#include <engine/graph.h>
45#include <engine/mpeg.h>
46#include <engine/disp.h>
aa4d7a4d 47#include <engine/perfmon.h>
ebb945a9 48
9274f4a9
BS		 49int
50nv40_identify(struct nouveau_device *device)
51{
52 switch (device->chipset) {
53 case 0x40:
2094dd82 54 device->cname = "NV40";
70c0f263 55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 56 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 57 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 58 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 59 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 60 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 61 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 62 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 63 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 64 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
24a4ae86 65 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
3863c9bc 66 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
c9c0ccae 67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 69 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 70 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9
BS		 71 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
72 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489 73 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 74 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 75 break;
76 case 0x41:
2094dd82 77 device->cname = "NV41";
70c0f263 78 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 79 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 80 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 81 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 82 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 83 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 84 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 85 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 87 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
24a4ae86 88 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 89 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 90 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 91 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 92 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 93 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9
BS		 94 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
95 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489 96 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 97 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 98 break;
99 case 0x42:
2094dd82 100 device->cname = "NV42";
70c0f263 101 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 102 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 103 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 104 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 105 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 106 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 107 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 108 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 109 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 110 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
24a4ae86 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 112 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 113 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 114 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 115 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 116 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9
BS		 117 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
118 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489 119 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 120 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 121 break;
122 case 0x43:
2094dd82 123 device->cname = "NV43";
70c0f263 124 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 125 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 126 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 127 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 128 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 129 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 130 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 131 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 132 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 133 device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
24a4ae86 134 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 135 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 136 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 137 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 138 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 139 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9
BS		 140 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
141 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
a8f8b489 142 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 143 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 144 break;
145 case 0x45:
2094dd82 146 device->cname = "NV45";
70c0f263 147 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 148 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 149 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 150 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 151 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 152 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 153 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 154 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 156 device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
24a4ae86 157 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
3863c9bc 158 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
c9c0ccae 159 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 160 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 161 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 162 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 163 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 164 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 165 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 166 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 167 break;
168 case 0x47:
2094dd82 169 device->cname = "G70";
70c0f263 170 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 171 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 172 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 173 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 174 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 175 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 176 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 177 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 179 device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
24a4ae86 180 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 181 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 182 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 183 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 184 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 185 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 186 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 187 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 188 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 189 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 190 break;
191 case 0x49:
2094dd82 192 device->cname = "G71";
70c0f263 193 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 194 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 195 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 196 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 197 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 198 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 199 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 200 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 201 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 202 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
24a4ae86 203 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 204 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 205 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 206 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 207 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 208 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 209 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 210 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 211 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 212 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 213 break;
214 case 0x4b:
2094dd82 215 device->cname = "G73";
70c0f263 216 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 217 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 218 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 219 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 220 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 221 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
1b4fea0f 222 device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
48ae0b35 223 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 224 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 225 device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
24a4ae86 226 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
002d0c73 227 device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
c9c0ccae 228 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 229 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 230 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 231 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 232 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 233 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 234 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 235 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 236 break;
237 case 0x44:
2094dd82 238 device->cname = "NV44";
70c0f263 239 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 240 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 241 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 242 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 243 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 244 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
08f6fbdb 245 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
48ae0b35 246 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 248 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
24a4ae86 249 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 250 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 251 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 253 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 254 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 255 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 257 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 258 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 259 break;
260 case 0x46:
2094dd82 261 device->cname = "G72";
70c0f263 262 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 263 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 264 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 265 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 266 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 267 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
08f6fbdb 268 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
48ae0b35 269 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 270 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 271 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
24a4ae86 272 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 273 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 275 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 276 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 277 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 278 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 279 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 280 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 281 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 282 break;
283 case 0x4a:
2094dd82 284 device->cname = "NV44A";
70c0f263 285 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 286 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 287 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 288 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 289 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
08f6fbdb 291 device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
48ae0b35 292 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 294 device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
24a4ae86 295 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 296 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 297 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 298 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 299 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 300 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 301 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 302 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 303 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 304 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 305 break;
306 case 0x4c:
2094dd82 307 device->cname = "C61";
70c0f263 308 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 309 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 310 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 311 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 312 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 313 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
fa8c9ac7 314 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
48ae0b35 315 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 316 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 317 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
24a4ae86 318 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 319 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 320 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 321 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 322 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 323 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 324 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 325 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 326 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 327 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 328 break;
329 case 0x4e:
2094dd82 330 device->cname = "C51";
70c0f263 331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 332 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 333 device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass;
8aceb7de 334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 336 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
fa8c9ac7 337 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
48ae0b35 338 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 339 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 340 device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
24a4ae86 341 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 342 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 343 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 344 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 345 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 346 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 347 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 348 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 349 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 350 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 351 break;
352 case 0x63:
2094dd82 353 device->cname = "C73";
70c0f263 354 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 355 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 356 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 357 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 358 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 359 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
fa8c9ac7 360 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
48ae0b35 361 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 362 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 363 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
24a4ae86 364 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 365 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 366 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 367 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 368 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 369 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 370 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 371 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 372 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 373 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 374 break;
375 case 0x67:
2094dd82 376 device->cname = "C67";
70c0f263 377 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 378 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 379 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 380 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 381 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 382 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
fa8c9ac7 383 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
48ae0b35 384 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 385 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 386 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
24a4ae86 387 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 388 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 389 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 390 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 391 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 392 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 393 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 394 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 395 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 396 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 397 break;
398 case 0x68:
2094dd82 399 device->cname = "C68";
70c0f263 400 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 401 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
7dcd060c 402 device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
8aceb7de 403 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
aa1b9b48 404 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
cf336014 405 device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
fa8c9ac7 406 device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
48ae0b35 407 device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
5a5c7432 408 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 409 device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
24a4ae86 410 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
e5f186c4 411 device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
c9c0ccae 412 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
ebb945a9 413 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
16c4f227 414 device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
c46c3ddf 415 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
ebb945a9 416 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
5fa75430 417 device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
a8f8b489 418 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
aa4d7a4d 419 device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
9274f4a9
BS		 420 break;
421 default:
422 nv_fatal(device, "unknown Curie chipset\n");
423 return -EINVAL;
424 }
425
426 return 0;
427}
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