[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / core / engine / device / nvc0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>

#include <engine/device.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>

int
nvc0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0xc0:
		device->cname = "GF100";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xc4:
		device->cname = "GF104";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xc3:
		device->cname = "GF106";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xce:
		device->cname = "GF114";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xcf:
		device->cname = "GF116";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xc1:
		device->cname = "GF108";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xc8:
		device->cname = "GF110";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nv94_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
		break;
	case 0xd9:
		device->cname = "GF119";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
		break;
	case 0xd7:
		device->cname = "GF117";
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Fermi chipset\n");
		return -EINVAL;
	}

	return 0;
	}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
70c0f263	25	#include <subdev/bios.h>
a10220bb	26	#include <subdev/bus.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
aa1b9b48	30	#include <subdev/therm.h>
d38ac521	31	#include <subdev/mxm.h>
cb75d97e	32	#include <subdev/devinit.h>
7d9115de	33	#include <subdev/mc.h>
5a5c7432	34	#include <subdev/timer.h>
861d2107 BS	35	#include <subdev/fb.h>
861d2107 BS	36	#include <subdev/ltcg.h>
c0abf5c9	37	#include <subdev/ibus.h>
3863c9bc BS	38	#include <subdev/instmem.h>
	39	#include <subdev/vm.h>
	40	#include <subdev/bar.h>
9274f4a9	41
dded35de	42	#include <engine/device.h>
ebb945a9 BS	43	#include <engine/dmaobj.h>
	44	#include <engine/fifo.h>
	45	#include <engine/software.h>
	46	#include <engine/graph.h>
	47	#include <engine/vp.h>
	48	#include <engine/bsp.h>
	49	#include <engine/ppp.h>
	50	#include <engine/copy.h>
	51	#include <engine/disp.h>
	52
9274f4a9 BS	53	int
	54	nvc0_identify(struct nouveau_device *device)
	55	{
	56	switch (device->chipset) {
	57	case 0xc0:
2094dd82	58	device->cname = "GF100";
70c0f263	59	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	60	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	61	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	62	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	63	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	64	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	65	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	66	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	67	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	68	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	69	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	70	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	71	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	72	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	73	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	74	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	75	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	76	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	77	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	78	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	79	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	80	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	81	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	82	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	83	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
70cabe4a	84	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	85	break;
9274f4a9 BS	86	case 0xc4:
2094dd82	87	device->cname = "GF104";
70c0f263	88	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	89	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	90	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	91	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	92	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	93	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	94	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	95	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	96	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	97	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	98	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	99	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	100	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	101	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	102	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	103	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	104	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	105	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	106	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	107	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	108	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	109	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	110	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	111	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	112	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
70cabe4a	113	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	114	break;
9274f4a9 BS	115	case 0xc3:
2094dd82	116	device->cname = "GF106";
70c0f263	117	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	118	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	119	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	120	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	121	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	122	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	123	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	124	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	125	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	126	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	127	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	128	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	129	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	130	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	131	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	132	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	133	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	134	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	135	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	136	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	137	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	138	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	139	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9	140	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
70cabe4a	141	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	142	break;
9274f4a9 BS	143	case 0xce:
2094dd82	144	device->cname = "GF114";
70c0f263	145	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	146	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	147	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	148	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	149	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	150	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	151	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	152	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	153	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	154	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	155	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	156	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	157	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	158	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	159	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	160	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	161	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	162	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	163	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	164	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	165	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	166	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	167	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	168	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	169	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
70cabe4a	170	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	171	break;
9274f4a9 BS	172	case 0xcf:
2094dd82	173	device->cname = "GF116";
70c0f263	174	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	175	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	176	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	177	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	178	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	179	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	180	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	181	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	182	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	183	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	184	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	185	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	186	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	187	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	188	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	189	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	190	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	191	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	192	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	193	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	194	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	195	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	196	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	197	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	198	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
70cabe4a	199	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	200	break;
9274f4a9 BS	201	case 0xc1:
2094dd82	202	device->cname = "GF108";
70c0f263	203	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	204	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	205	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	206	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	207	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	208	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	209	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	210	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	211	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	212	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	213	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	214	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	215	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	216	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	217	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	218	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	219	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	220	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	221	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	222	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	223	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	224	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	225	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9	226	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
70cabe4a	227	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	228	break;
9274f4a9 BS	229	case 0xc8:
2094dd82	230	device->cname = "GF110";
70c0f263	231	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	232	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
7dcd060c	233	device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
8aceb7de	234	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
7b49bd68	235	device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521	236	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	237	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	238	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	239	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	240	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	241	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	242	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	243	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	244	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	245	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	246	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	247	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	248	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	249	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	250	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	251	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	252	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	253	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	254	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	255	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
70cabe4a	256	device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
9274f4a9 BS	257	break;
9274f4a9 BS	258	case 0xd9:
2094dd82	259	device->cname = "GF119";
70c0f263	260	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	261	device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
7dcd060c	262	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
8aceb7de	263	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
bc79202f	264	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
d38ac521	265	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
cb75d97e	266	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	267	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
a10220bb	268	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
5a5c7432	269	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
3f196a04 BS	270	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
	271	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
	272	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
	273	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	274	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	275	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
	276	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
	277	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	278	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	279	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	280	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
	281	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
	282	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
	283	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	284	device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
	285	break;
	286	case 0xd7:
	287	device->cname = "GF117";
	288	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
	289	device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
	290	device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
	291	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
	292	device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
	293	device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
	294	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
	295	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
	296	device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
	297	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	298	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	299	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
c0abf5c9	300	device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
3863c9bc BS	301	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	302	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	303	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
344e107d	304	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
ebb945a9 BS	305	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	306	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	307	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
7d8bd91b	308	device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
23c14ed2	309	device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
4a795014	310	device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
ebb945a9 BS	311	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
ebb945a9 BS	312	device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
9274f4a9 BS	313	break;
	314	default:
	315	nv_fatal(device, "unknown Fermi chipset\n");
	316	return -EINVAL;
	317	}
	318
	319	return 0;
7b49bd68	320	}