[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / core / engine / disp / nva0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <engine/software.h>
#include <engine/disp.h>

#include <core/class.h>

#include "nv50.h"

static struct nouveau_oclass
nva0_disp_sclass[] = {
	{ NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
	{ NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
	{ NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
	{ NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
	{ NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
	{}
};

static struct nouveau_oclass
nva0_disp_base_oclass[] = {
	{ NVA0_DISP_CLASS, &nv50_disp_base_ofuncs, nv84_disp_base_omthds },
	{}
};

static int
nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv50_disp_priv *priv;
	int ret;

	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
				  "display", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_engine(priv)->sclass = nva0_disp_base_oclass;
	nv_engine(priv)->cclass = &nv50_disp_cclass;
	nv_subdev(priv)->intr = nv50_disp_intr;
	priv->sclass = nva0_disp_sclass;
	priv->head.nr = 2;
	priv->dac.nr = 3;
	priv->sor.nr = 2;
	priv->dac.power = nv50_dac_power;
	priv->dac.sense = nv50_dac_sense;
	priv->sor.power = nv50_sor_power;
	priv->sor.hdmi = nv84_hdmi_ctrl;
	return 0;
}

struct nouveau_oclass
nva0_disp_oclass = {
	.handle = NV_ENGINE(DISP, 0x83),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nva0_disp_ctor,
		.dtor = _nouveau_disp_dtor,
		.init = _nouveau_disp_init,
		.fini = _nouveau_disp_fini,
	},
};
Commit	Line	Data
70cabe4a BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <engine/software.h>
	26	#include <engine/disp.h>
	27
370c00f9 BS	28	#include <core/class.h>
370c00f9 BS	29
70cabe4a BS	30	#include "nv50.h"
	31
	32	static struct nouveau_oclass
	33	nva0_disp_sclass[] = {
370c00f9 BS	34	{ NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
	35	{ NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
	36	{ NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
	37	{ NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
	38	{ NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
70cabe4a BS	39	{}
	40	};
	41
	42	static struct nouveau_oclass
	43	nva0_disp_base_oclass[] = {
ef22c8bb	44	{ NVA0_DISP_CLASS, &nv50_disp_base_ofuncs, nv84_disp_base_omthds },
370c00f9	45	{}
70cabe4a BS	46	};
	47
	48	static int
	49	nva0_disp_ctor(struct nouveau_object parent, struct nouveau_object engine,
	50	struct nouveau_oclass oclass, void data, u32 size,
	51	struct nouveau_object **pobject)
	52	{
	53	struct nv50_disp_priv *priv;
	54	int ret;
	55
1d7c71a3	56	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
70cabe4a BS	57	"display", &priv);
	58	*pobject = nv_object(priv);
	59	if (ret)
	60	return ret;
	61
	62	nv_engine(priv)->sclass = nva0_disp_base_oclass;
	63	nv_engine(priv)->cclass = &nv50_disp_cclass;
	64	nv_subdev(priv)->intr = nv50_disp_intr;
	65	priv->sclass = nva0_disp_sclass;
	66	priv->head.nr = 2;
	67	priv->dac.nr = 3;
	68	priv->sor.nr = 2;
ef22c8bb	69	priv->dac.power = nv50_dac_power;
7ebb38b5	70	priv->dac.sense = nv50_dac_sense;
ef22c8bb	71	priv->sor.power = nv50_sor_power;
8e9e3d2d	72	priv->sor.hdmi = nv84_hdmi_ctrl;
70cabe4a BS	73	return 0;
	74	}
	75
	76	struct nouveau_oclass
	77	nva0_disp_oclass = {
	78	.handle = NV_ENGINE(DISP, 0x83),
	79	.ofuncs = &(struct nouveau_ofuncs) {
	80	.ctor = nva0_disp_ctor,
	81	.dtor = _nouveau_disp_dtor,
	82	.init = _nouveau_disp_init,
	83	.fini = _nouveau_disp_fini,
	84	},
	85	};