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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include <core/os.h> | |
6c5a0424 BS |
26 | |
27 | #include <subdev/bios.h> | |
28 | #include <subdev/bios/dcb.h> | |
29 | #include <subdev/bios/dp.h> | |
30 | #include <subdev/bios/init.h> | |
1ecee1cd | 31 | #include <subdev/timer.h> |
6c5a0424 BS |
32 | |
33 | #include "nv50.h" | |
34 | ||
0a0afd28 | 35 | static inline u32 |
3b52a1f9 | 36 | nvd0_sor_soff(struct nvkm_output_dp *outp) |
0a0afd28 | 37 | { |
3b52a1f9 | 38 | return (ffs(outp->base.info.or) - 1) * 0x800; |
0a0afd28 BS |
39 | } |
40 | ||
41 | static inline u32 | |
3b52a1f9 | 42 | nvd0_sor_loff(struct nvkm_output_dp *outp) |
0a0afd28 | 43 | { |
3b52a1f9 | 44 | return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; |
0a0afd28 BS |
45 | } |
46 | ||
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47 | static inline u32 |
48 | nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) | |
49 | { | |
50 | static const u8 nvd0[] = { 16, 8, 0, 24 }; | |
51 | return nvd0[lane]; | |
52 | } | |
53 | ||
0a0afd28 | 54 | static int |
3b52a1f9 | 55 | nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) |
6c5a0424 | 56 | { |
3b52a1f9 | 57 | struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); |
0a0afd28 BS |
58 | const u32 loff = nvd0_sor_loff(outp); |
59 | nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); | |
6c5a0424 BS |
60 | return 0; |
61 | } | |
62 | ||
0a0afd28 | 63 | static int |
3b52a1f9 | 64 | nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) |
6c5a0424 | 65 | { |
3b52a1f9 | 66 | struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); |
0a0afd28 BS |
67 | const u32 soff = nvd0_sor_soff(outp); |
68 | const u32 loff = nvd0_sor_loff(outp); | |
6c5a0424 BS |
69 | u32 dpctrl = 0x00000000; |
70 | u32 clksor = 0x00000000; | |
6c5a0424 | 71 | |
3b52a1f9 BS |
72 | clksor |= bw << 18; |
73 | dpctrl |= ((1 << nr) - 1) << 16; | |
74 | if (ef) | |
6c5a0424 BS |
75 | dpctrl |= 0x00004000; |
76 | ||
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77 | nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor); |
78 | nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); | |
6c5a0424 BS |
79 | return 0; |
80 | } | |
81 | ||
0a0afd28 | 82 | static int |
3b52a1f9 | 83 | nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) |
6c5a0424 | 84 | { |
3b52a1f9 BS |
85 | struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); |
86 | struct nouveau_bios *bios = nouveau_bios(priv); | |
87 | const u32 shift = nvd0_sor_dp_lane_map(priv, ln); | |
0a0afd28 | 88 | const u32 loff = nvd0_sor_loff(outp); |
7a14bc78 | 89 | u32 addr, data[4]; |
6c5a0424 | 90 | u8 ver, hdr, cnt, len; |
0a0afd28 | 91 | struct nvbios_dpout info; |
6c5a0424 BS |
92 | struct nvbios_dpcfg ocfg; |
93 | ||
3b52a1f9 BS |
94 | addr = nvbios_dpout_match(bios, outp->base.info.hasht, |
95 | outp->base.info.hashm, | |
0a0afd28 | 96 | &ver, &hdr, &cnt, &len, &info); |
6c5a0424 BS |
97 | if (!addr) |
98 | return -ENODEV; | |
99 | ||
7a14bc78 | 100 | addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, |
0a0afd28 | 101 | &ver, &hdr, &cnt, &len, &ocfg); |
6c5a0424 BS |
102 | if (!addr) |
103 | return -EINVAL; | |
104 | ||
6d8d1631 BS |
105 | data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); |
106 | data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); | |
3e1eb5cf BS |
107 | data[2] = nv_rd32(priv, 0x61c130 + loff); |
108 | if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) | |
109 | data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); | |
7a14bc78 BS |
110 | nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); |
111 | nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); | |
112 | nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); | |
113 | data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); | |
114 | nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); | |
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115 | return 0; |
116 | } | |
0a0afd28 | 117 | |
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118 | struct nvkm_output_dp_impl |
119 | nvd0_sor_dp_impl = { | |
120 | .base.base.handle = DCB_OUTPUT_DP, | |
121 | .base.base.ofuncs = &(struct nouveau_ofuncs) { | |
122 | .ctor = _nvkm_output_dp_ctor, | |
123 | .dtor = _nvkm_output_dp_dtor, | |
124 | .init = _nvkm_output_dp_init, | |
125 | .fini = _nvkm_output_dp_fini, | |
126 | }, | |
3b52a1f9 | 127 | .pattern = nvd0_sor_dp_pattern, |
1ecee1cd | 128 | .lnk_pwr = nv94_sor_dp_lnk_pwr, |
3b52a1f9 BS |
129 | .lnk_ctl = nvd0_sor_dp_lnk_ctl, |
130 | .drv_ctl = nvd0_sor_dp_drv_ctl, | |
b8407c9e | 131 | }; |