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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
4acfd707 | 25 | #include <core/client.h> |
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26 | #include <core/device.h> |
27 | #include <core/gpuobj.h> | |
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28 | #include <nvif/unpack.h> |
29 | #include <nvif/class.h> | |
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30 | |
31 | #include <subdev/fb.h> | |
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32 | |
33 | #include "priv.h" | |
344e107d | 34 | |
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35 | struct nvd0_dmaobj_priv { |
36 | struct nouveau_dmaobj base; | |
37 | u32 flags0; | |
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38 | }; |
39 | ||
40 | static int | |
b2c81703 | 41 | nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, |
344e107d | 42 | struct nouveau_object *parent, |
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43 | struct nouveau_gpuobj **pgpuobj) |
44 | { | |
b2c81703 | 45 | struct nvd0_dmaobj_priv *priv = (void *)dmaobj; |
47a1e0fe | 46 | int ret; |
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47 | |
48 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { | |
49 | switch (nv_mclass(parent->parent)) { | |
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50 | case GF110_DISP_CORE_CHANNEL_DMA: |
51 | case GK104_DISP_CORE_CHANNEL_DMA: | |
52 | case GK110_DISP_CORE_CHANNEL_DMA: | |
53 | case GM107_DISP_CORE_CHANNEL_DMA: | |
54 | case GF110_DISP_BASE_CHANNEL_DMA: | |
55 | case GK104_DISP_BASE_CHANNEL_DMA: | |
56 | case GK110_DISP_BASE_CHANNEL_DMA: | |
57 | case GF110_DISP_OVERLAY_CONTROL_DMA: | |
58 | case GK104_DISP_OVERLAY_CONTROL_DMA: | |
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59 | break; |
60 | default: | |
61 | return -EINVAL; | |
62 | } | |
63 | } else | |
64 | return 0; | |
65 | ||
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66 | ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); |
67 | if (ret == 0) { | |
68 | nv_wo32(*pgpuobj, 0x00, priv->flags0); | |
69 | nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8); | |
70 | nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8); | |
71 | nv_wo32(*pgpuobj, 0x0c, 0x00000000); | |
72 | nv_wo32(*pgpuobj, 0x10, 0x00000000); | |
73 | nv_wo32(*pgpuobj, 0x14, 0x00000000); | |
74 | } | |
75 | ||
76 | return ret; | |
77 | } | |
78 | ||
79 | static int | |
80 | nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
81 | struct nouveau_oclass *oclass, void *data, u32 size, | |
82 | struct nouveau_object **pobject) | |
83 | { | |
84 | struct nouveau_dmaeng *dmaeng = (void *)engine; | |
b2c81703 | 85 | union { |
4acfd707 | 86 | struct gf110_dma_v0 v0; |
b2c81703 | 87 | } *args; |
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88 | struct nvd0_dmaobj_priv *priv; |
89 | u32 kind, page; | |
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90 | int ret; |
91 | ||
92 | ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); | |
93 | *pobject = nv_object(priv); | |
94 | if (ret) | |
95 | return ret; | |
96 | args = data; | |
97 | ||
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98 | nv_ioctl(parent, "create gf110 dma size %d\n", size); |
99 | if (nvif_unpack(args->v0, 0, 0, false)) { | |
100 | nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n", | |
101 | args->v0.version, args->v0.page, args->v0.kind); | |
102 | kind = args->v0.kind; | |
103 | page = args->v0.page; | |
104 | } else | |
105 | if (size == 0) { | |
106 | if (priv->base.target != NV_MEM_TARGET_VM) { | |
107 | kind = GF110_DMA_V0_KIND_PITCH; | |
108 | page = GF110_DMA_V0_PAGE_SP; | |
47a1e0fe | 109 | } else { |
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110 | kind = GF110_DMA_V0_KIND_VM; |
111 | page = GF110_DMA_V0_PAGE_LP; | |
47a1e0fe | 112 | } |
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113 | } else |
114 | return ret; | |
47a1e0fe | 115 | |
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116 | if (page > 1) |
117 | return -EINVAL; | |
118 | priv->flags0 = (kind << 20) | (page << 6); | |
47a1e0fe | 119 | |
b2c81703 | 120 | switch (priv->base.target) { |
47a1e0fe | 121 | case NV_MEM_TARGET_VRAM: |
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122 | priv->flags0 |= 0x00000009; |
123 | break; | |
124 | case NV_MEM_TARGET_VM: | |
125 | case NV_MEM_TARGET_PCI: | |
126 | case NV_MEM_TARGET_PCI_NOSNOOP: | |
127 | /* XXX: don't currently know how to construct a real one | |
128 | * of these. we only use them to represent pushbufs | |
129 | * on these chipsets, and the classes that use them | |
130 | * deal with the target themselves. | |
131 | */ | |
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132 | break; |
133 | default: | |
134 | return -EINVAL; | |
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135 | } |
136 | ||
b2c81703 | 137 | return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); |
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138 | } |
139 | ||
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140 | static struct nouveau_ofuncs |
141 | nvd0_dmaobj_ofuncs = { | |
142 | .ctor = nvd0_dmaobj_ctor, | |
143 | .dtor = _nvkm_dmaobj_dtor, | |
144 | .init = _nvkm_dmaobj_init, | |
145 | .fini = _nvkm_dmaobj_fini, | |
146 | }; | |
147 | ||
148 | static struct nouveau_oclass | |
149 | nvd0_dmaeng_sclass[] = { | |
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150 | { NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs }, |
151 | { NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs }, | |
152 | { NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs }, | |
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153 | {} |
154 | }; | |
155 | ||
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156 | struct nouveau_oclass * |
157 | nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { | |
158 | .base.handle = NV_ENGINE(DMAOBJ, 0xd0), | |
159 | .base.ofuncs = &(struct nouveau_ofuncs) { | |
160 | .ctor = _nvkm_dmaeng_ctor, | |
161 | .dtor = _nvkm_dmaeng_dtor, | |
162 | .init = _nvkm_dmaeng_init, | |
163 | .fini = _nvkm_dmaeng_fini, | |
344e107d | 164 | }, |
b2c81703 | 165 | .sclass = nvd0_dmaeng_sclass, |
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166 | .bind = nvd0_dmaobj_bind, |
167 | }.base; |