[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / nouveau / core / engine / fifo / nv84.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/os.h>
#include <core/client.h>
#include <core/engctx.h>
#include <core/ramht.h>
#include <core/event.h>
#include <core/class.h>

#include <subdev/timer.h>
#include <subdev/bar.h>

#include <engine/dmaobj.h>
#include <engine/fifo.h>

#include "nv04.h"
#include "nv50.h"

/*******************************************************************************
 * FIFO channel objects
 ******************************************************************************/

static int
nv84_fifo_context_attach(struct nouveau_object *parent,
			 struct nouveau_object *object)
{
	struct nouveau_bar *bar = nouveau_bar(parent);
	struct nv50_fifo_base *base = (void *)parent->parent;
	struct nouveau_gpuobj *ectx = (void *)object;
	u64 limit = ectx->addr + ectx->size - 1;
	u64 start = ectx->addr;
	u32 addr;

	switch (nv_engidx(object->engine)) {
	case NVDEV_ENGINE_SW   : return 0;
	case NVDEV_ENGINE_GR   : addr = 0x0020; break;
	case NVDEV_ENGINE_VP   : addr = 0x0040; break;
	case NVDEV_ENGINE_PPP  :
	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
	case NVDEV_ENGINE_BSP  : addr = 0x0080; break;
	case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
	case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
	default:
		return -EINVAL;
	}

	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
	nv_wo32(base->eng, addr + 0x00, 0x00190000);
	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
					upper_32_bits(start));
	nv_wo32(base->eng, addr + 0x10, 0x00000000);
	nv_wo32(base->eng, addr + 0x14, 0x00000000);
	bar->flush(bar);
	return 0;
}

static int
nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
			 struct nouveau_object *object)
{
	struct nouveau_bar *bar = nouveau_bar(parent);
	struct nv50_fifo_priv *priv = (void *)parent->engine;
	struct nv50_fifo_base *base = (void *)parent->parent;
	struct nv50_fifo_chan *chan = (void *)parent;
	u32 addr, save, engn;
	bool done;

	switch (nv_engidx(object->engine)) {
	case NVDEV_ENGINE_SW   : return 0;
	case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
	case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;
	case NVDEV_ENGINE_PPP  :
	case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
	case NVDEV_ENGINE_BSP  : engn = 5; addr = 0x0080; break;
	case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
	case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
	default:
		return -EINVAL;
	}

	save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
	done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
	nv_wr32(priv, 0x002520, save);
	if (!done) {
		nv_error(priv, "channel %d [%s] unload timeout\n",
			 chan->base.chid, nouveau_client_name(chan));
		if (suspend)
			return -EBUSY;
	}

	nv_wo32(base->eng, addr + 0x00, 0x00000000);
	nv_wo32(base->eng, addr + 0x04, 0x00000000);
	nv_wo32(base->eng, addr + 0x08, 0x00000000);
	nv_wo32(base->eng, addr + 0x0c, 0x00000000);
	nv_wo32(base->eng, addr + 0x10, 0x00000000);
	nv_wo32(base->eng, addr + 0x14, 0x00000000);
	bar->flush(bar);
	return 0;
}

static int
nv84_fifo_object_attach(struct nouveau_object *parent,
			struct nouveau_object *object, u32 handle)
{
	struct nv50_fifo_chan *chan = (void *)parent;
	u32 context;

	if (nv_iclass(object, NV_GPUOBJ_CLASS))
		context = nv_gpuobj(object)->node->offset >> 4;
	else
		context = 0x00000004; /* just non-zero */

	switch (nv_engidx(object->engine)) {
	case NVDEV_ENGINE_DMAOBJ:
	case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
	case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
	case NVDEV_ENGINE_MPEG  :
	case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
	case NVDEV_ENGINE_ME    :
	case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
	case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
	case NVDEV_ENGINE_CRYPT :
	case NVDEV_ENGINE_VIC   : context |= 0x00500000; break;
	case NVDEV_ENGINE_BSP   : context |= 0x00600000; break;
	default:
		return -EINVAL;
	}

	return nouveau_ramht_insert(chan->ramht, 0, handle, context);
}

static int
nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nouveau_bar *bar = nouveau_bar(parent);
	struct nv50_fifo_base *base = (void *)parent;
	struct nv50_fifo_chan *chan;
	struct nv03_channel_dma_class *args = data;
	int ret;

	if (size < sizeof(*args))
		return -EINVAL;

	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
					  0x2000, args->pushbuf,
					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
					  (1ULL << NVDEV_ENGINE_SW) |
					  (1ULL << NVDEV_ENGINE_GR) |
					  (1ULL << NVDEV_ENGINE_MPEG) |
					  (1ULL << NVDEV_ENGINE_ME) |
					  (1ULL << NVDEV_ENGINE_VP) |
					  (1ULL << NVDEV_ENGINE_CRYPT) |
					  (1ULL << NVDEV_ENGINE_BSP) |
					  (1ULL << NVDEV_ENGINE_PPP) |
					  (1ULL << NVDEV_ENGINE_COPY0) |
					  (1ULL << NVDEV_ENGINE_VIC), &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
			       &chan->ramht);
	if (ret)
		return ret;

	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
	nv_parent(chan)->object_detach = nv50_fifo_object_detach;

	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
	nv_wo32(base->ramfc, 0x3c, 0x003f6078);
	nv_wo32(base->ramfc, 0x44, 0x01003fff);
	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
	nv_wo32(base->ramfc, 0x4c, 0xffffffff);
	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
	nv_wo32(base->ramfc, 0x78, 0x00000000);
	nv_wo32(base->ramfc, 0x7c, 0x30000001);
	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
				   (4 << 24) /* SEARCH_FULL */ |
				   (chan->ramht->base.node->offset >> 4));
	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
	bar->flush(bar);
	return 0;
}

static int
nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nouveau_bar *bar = nouveau_bar(parent);
	struct nv50_fifo_base *base = (void *)parent;
	struct nv50_fifo_chan *chan;
	struct nv50_channel_ind_class *args = data;
	u64 ioffset, ilength;
	int ret;

	if (size < sizeof(*args))
		return -EINVAL;

	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
					  0x2000, args->pushbuf,
					  (1ULL << NVDEV_ENGINE_DMAOBJ) |
					  (1ULL << NVDEV_ENGINE_SW) |
					  (1ULL << NVDEV_ENGINE_GR) |
					  (1ULL << NVDEV_ENGINE_MPEG) |
					  (1ULL << NVDEV_ENGINE_ME) |
					  (1ULL << NVDEV_ENGINE_VP) |
					  (1ULL << NVDEV_ENGINE_CRYPT) |
					  (1ULL << NVDEV_ENGINE_BSP) |
					  (1ULL << NVDEV_ENGINE_PPP) |
					  (1ULL << NVDEV_ENGINE_COPY0) |
					  (1ULL << NVDEV_ENGINE_VIC), &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
			       &chan->ramht);
	if (ret)
		return ret;

	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
	nv_parent(chan)->object_detach = nv50_fifo_object_detach;

	ioffset = args->ioffset;
	ilength = order_base_2(args->ilength / 8);

	nv_wo32(base->ramfc, 0x3c, 0x403f6078);
	nv_wo32(base->ramfc, 0x44, 0x01003fff);
	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
	nv_wo32(base->ramfc, 0x78, 0x00000000);
	nv_wo32(base->ramfc, 0x7c, 0x30000001);
	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
				   (4 << 24) /* SEARCH_FULL */ |
				   (chan->ramht->base.node->offset >> 4));
	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
	bar->flush(bar);
	return 0;
}

static int
nv84_fifo_chan_init(struct nouveau_object *object)
{
	struct nv50_fifo_priv *priv = (void *)object->engine;
	struct nv50_fifo_base *base = (void *)object->parent;
	struct nv50_fifo_chan *chan = (void *)object;
	struct nouveau_gpuobj *ramfc = base->ramfc;
	u32 chid = chan->base.chid;
	int ret;

	ret = nouveau_fifo_channel_init(&chan->base);
	if (ret)
		return ret;

	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
	nv50_fifo_playlist_update(priv);
	return 0;
}

static struct nouveau_ofuncs
nv84_fifo_ofuncs_dma = {
	.ctor = nv84_fifo_chan_ctor_dma,
	.dtor = nv50_fifo_chan_dtor,
	.init = nv84_fifo_chan_init,
	.fini = nv50_fifo_chan_fini,
	.rd32 = _nouveau_fifo_channel_rd32,
	.wr32 = _nouveau_fifo_channel_wr32,
};

static struct nouveau_ofuncs
nv84_fifo_ofuncs_ind = {
	.ctor = nv84_fifo_chan_ctor_ind,
	.dtor = nv50_fifo_chan_dtor,
	.init = nv84_fifo_chan_init,
	.fini = nv50_fifo_chan_fini,
	.rd32 = _nouveau_fifo_channel_rd32,
	.wr32 = _nouveau_fifo_channel_wr32,
};

static struct nouveau_oclass
nv84_fifo_sclass[] = {
	{ NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
	{ NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
	{}
};

/*******************************************************************************
 * FIFO context - basically just the instmem reserved for the channel
 ******************************************************************************/

static int
nv84_fifo_context_ctor(struct nouveau_object *parent,
		       struct nouveau_object *engine,
		       struct nouveau_oclass *oclass, void *data, u32 size,
		       struct nouveau_object **pobject)
{
	struct nv50_fifo_base *base;
	int ret;

	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
				          0x1000, NVOBJ_FLAG_HEAP, &base);
	*pobject = nv_object(base);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
				 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
				 0, &base->pgd);
	if (ret)
		return ret;

	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
				 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
				 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
	if (ret)
		return ret;

	return 0;
}

static struct nouveau_oclass
nv84_fifo_cclass = {
	.handle = NV_ENGCTX(FIFO, 0x84),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv84_fifo_context_ctor,
		.dtor = nv50_fifo_context_dtor,
		.init = _nouveau_fifo_context_init,
		.fini = _nouveau_fifo_context_fini,
		.rd32 = _nouveau_fifo_context_rd32,
		.wr32 = _nouveau_fifo_context_wr32,
	},
};

/*******************************************************************************
 * PFIFO engine
 ******************************************************************************/

static void
nv84_fifo_uevent_enable(struct nouveau_event *event, int index)
{
	struct nv84_fifo_priv *priv = event->priv;
	nv_mask(priv, 0x002140, 0x40000000, 0x40000000);
}

static void
nv84_fifo_uevent_disable(struct nouveau_event *event, int index)
{
	struct nv84_fifo_priv *priv = event->priv;
	nv_mask(priv, 0x002140, 0x40000000, 0x00000000);
}

static int
nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv50_fifo_priv *priv;
	int ret;

	ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
				&priv->playlist[0]);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
				&priv->playlist[1]);
	if (ret)
		return ret;

	priv->base.uevent->enable = nv84_fifo_uevent_enable;
	priv->base.uevent->disable = nv84_fifo_uevent_disable;
	priv->base.uevent->priv = priv;

	nv_subdev(priv)->unit = 0x00000100;
	nv_subdev(priv)->intr = nv04_fifo_intr;
	nv_engine(priv)->cclass = &nv84_fifo_cclass;
	nv_engine(priv)->sclass = nv84_fifo_sclass;
	priv->base.pause = nv04_fifo_pause;
	priv->base.start = nv04_fifo_start;
	return 0;
}

struct nouveau_oclass *
nv84_fifo_oclass = &(struct nouveau_oclass) {
	.handle = NV_ENGINE(FIFO, 0x84),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv84_fifo_ctor,
		.dtor = nv50_fifo_dtor,
		.init = nv50_fifo_init,
		.fini = _nouveau_fifo_fini,
	},
};
Commit	Line	Data
c420b2dc	1	/*
ebb945a9	2	* Copyright 2012 Red Hat Inc.
c420b2dc	3	*
ebb945a9 BS	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
c420b2dc	10	*
ebb945a9 BS	11	* The above copyright notice and this permission notice shall be included in
ebb945a9 BS	12	* all copies or substantial portions of the Software.
c420b2dc	13	*
ebb945a9 BS	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
c420b2dc	21	*
ebb945a9	22	* Authors: Ben Skeggs
c420b2dc BS	23	*/
c420b2dc BS	24
ebb945a9 BS	25	#include <core/os.h>
	26	#include <core/client.h>
	27	#include <core/engctx.h>
02a841d4	28	#include <core/ramht.h>
750087f1	29	#include <core/event.h>
ebb945a9	30	#include <core/class.h>
c420b2dc	31
ebb945a9 BS	32	#include <subdev/timer.h>
ebb945a9 BS	33	#include <subdev/bar.h>
c420b2dc	34
ebb945a9 BS	35	#include <engine/dmaobj.h>
	36	#include <engine/fifo.h>
	37
b1cd4976	38	#include "nv04.h"
ebb945a9 BS	39	#include "nv50.h"
	40
	41	/*******************************************************************************
	42	* FIFO channel objects
	43	******************************************************************************/
c420b2dc BS	44
c420b2dc BS	45	static int
ebb945a9 BS	46	nv84_fifo_context_attach(struct nouveau_object *parent,
ebb945a9 BS	47	struct nouveau_object *object)
c420b2dc	48	{
ebb945a9 BS	49	struct nouveau_bar *bar = nouveau_bar(parent);
	50	struct nv50_fifo_base base = (void )parent->parent;
	51	struct nouveau_gpuobj ectx = (void )object;
	52	u64 limit = ectx->addr + ectx->size - 1;
	53	u64 start = ectx->addr;
	54	u32 addr;
	55
	56	switch (nv_engidx(object->engine)) {
	57	case NVDEV_ENGINE_SW : return 0;
	58	case NVDEV_ENGINE_GR : addr = 0x0020; break;
a0376b14	59	case NVDEV_ENGINE_VP : addr = 0x0040; break;
ef7d64e5	60	case NVDEV_ENGINE_PPP :
ebb945a9	61	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
05f9a5bc	62	case NVDEV_ENGINE_BSP : addr = 0x0080; break;
ebb945a9 BS	63	case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
	64	case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
	65	default:
	66	return -EINVAL;
	67	}
c420b2dc	68
4c2d4222	69	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
ebb945a9 BS	70	nv_wo32(base->eng, addr + 0x00, 0x00190000);
	71	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
	72	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
	73	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 \|
	74	upper_32_bits(start));
	75	nv_wo32(base->eng, addr + 0x10, 0x00000000);
	76	nv_wo32(base->eng, addr + 0x14, 0x00000000);
	77	bar->flush(bar);
	78	return 0;
	79	}
c420b2dc	80
ebb945a9 BS	81	static int
	82	nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
	83	struct nouveau_object *object)
	84	{
	85	struct nouveau_bar *bar = nouveau_bar(parent);
	86	struct nv50_fifo_priv priv = (void )parent->engine;
	87	struct nv50_fifo_base base = (void )parent->parent;
	88	struct nv50_fifo_chan chan = (void )parent;
6fa8e629 BS	89	u32 addr, save, engn;
6fa8e629 BS	90	bool done;
ebb945a9 BS	91
	92	switch (nv_engidx(object->engine)) {
	93	case NVDEV_ENGINE_SW : return 0;
6fa8e629	94	case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
a0376b14	95	case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
ef7d64e5	96	case NVDEV_ENGINE_PPP :
6fa8e629	97	case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
05f9a5bc	98	case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
6fa8e629 BS	99	case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
6fa8e629 BS	100	case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
ebb945a9 BS	101	default:
ebb945a9 BS	102	return -EINVAL;
c420b2dc BS	103	}
c420b2dc BS	104
6fa8e629	105	save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
ebb945a9	106	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
6fa8e629 BS	107	done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
	108	nv_wr32(priv, 0x002520, save);
	109	if (!done) {
93260d3c MS	110	nv_error(priv, "channel %d [%s] unload timeout\n",
93260d3c MS	111	chan->base.chid, nouveau_client_name(chan));
ebb945a9 BS	112	if (suspend)
	113	return -EBUSY;
	114	}
edc260d0 BS	115
	116	nv_wo32(base->eng, addr + 0x00, 0x00000000);
	117	nv_wo32(base->eng, addr + 0x04, 0x00000000);
	118	nv_wo32(base->eng, addr + 0x08, 0x00000000);
	119	nv_wo32(base->eng, addr + 0x0c, 0x00000000);
	120	nv_wo32(base->eng, addr + 0x10, 0x00000000);
	121	nv_wo32(base->eng, addr + 0x14, 0x00000000);
	122	bar->flush(bar);
ebb945a9 BS	123	return 0;
ebb945a9 BS	124	}
c420b2dc	125
ebb945a9 BS	126	static int
	127	nv84_fifo_object_attach(struct nouveau_object *parent,
	128	struct nouveau_object *object, u32 handle)
	129	{
	130	struct nv50_fifo_chan chan = (void )parent;
	131	u32 context;
	132
	133	if (nv_iclass(object, NV_GPUOBJ_CLASS))
	134	context = nv_gpuobj(object)->node->offset >> 4;
	135	else
	136	context = 0x00000004; /* just non-zero */
	137
	138	switch (nv_engidx(object->engine)) {
	139	case NVDEV_ENGINE_DMAOBJ:
	140	case NVDEV_ENGINE_SW : context \|= 0x00000000; break;
	141	case NVDEV_ENGINE_GR : context \|= 0x00100000; break;
	142	case NVDEV_ENGINE_MPEG :
	143	case NVDEV_ENGINE_PPP : context \|= 0x00200000; break;
	144	case NVDEV_ENGINE_ME :
	145	case NVDEV_ENGINE_COPY0 : context \|= 0x00300000; break;
	146	case NVDEV_ENGINE_VP : context \|= 0x00400000; break;
	147	case NVDEV_ENGINE_CRYPT :
c42a7aec	148	case NVDEV_ENGINE_VIC : context \|= 0x00500000; break;
ebb945a9 BS	149	case NVDEV_ENGINE_BSP : context \|= 0x00600000; break;
	150	default:
	151	return -EINVAL;
	152	}
c420b2dc	153
ebb945a9 BS	154	return nouveau_ramht_insert(chan->ramht, 0, handle, context);
ebb945a9 BS	155	}
c420b2dc	156
ebb945a9	157	static int
ab285892 BS	158	nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
	159	struct nouveau_object *engine,
	160	struct nouveau_oclass oclass, void data, u32 size,
	161	struct nouveau_object **pobject)
	162	{
	163	struct nouveau_bar *bar = nouveau_bar(parent);
	164	struct nv50_fifo_base base = (void )parent;
	165	struct nv50_fifo_chan *chan;
	166	struct nv03_channel_dma_class *args = data;
	167	int ret;
	168
	169	if (size < sizeof(*args))
	170	return -EINVAL;
	171
	172	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
	173	0x2000, args->pushbuf,
507ceb15 MP	174	(1ULL << NVDEV_ENGINE_DMAOBJ) \|
	175	(1ULL << NVDEV_ENGINE_SW) \|
	176	(1ULL << NVDEV_ENGINE_GR) \|
	177	(1ULL << NVDEV_ENGINE_MPEG) \|
	178	(1ULL << NVDEV_ENGINE_ME) \|
	179	(1ULL << NVDEV_ENGINE_VP) \|
	180	(1ULL << NVDEV_ENGINE_CRYPT) \|
	181	(1ULL << NVDEV_ENGINE_BSP) \|
	182	(1ULL << NVDEV_ENGINE_PPP) \|
	183	(1ULL << NVDEV_ENGINE_COPY0) \|
c42a7aec	184	(1ULL << NVDEV_ENGINE_VIC), &chan);
ab285892 BS	185	*pobject = nv_object(chan);
	186	if (ret)
	187	return ret;
	188
f50c8054 BS	189	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
f50c8054 BS	190	&chan->ramht);
ab285892 BS	191	if (ret)
	192	return ret;
	193
	194	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
	195	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
	196	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
	197	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
	198
	199	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
	200	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
	201	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
	202	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
	203	nv_wo32(base->ramfc, 0x3c, 0x003f6078);
	204	nv_wo32(base->ramfc, 0x44, 0x01003fff);
	205	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
	206	nv_wo32(base->ramfc, 0x4c, 0xffffffff);
	207	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
	208	nv_wo32(base->ramfc, 0x78, 0x00000000);
	209	nv_wo32(base->ramfc, 0x7c, 0x30000001);
	210	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) \|
	211	(4 << 24) /* SEARCH_FULL */ \|
	212	(chan->ramht->base.node->offset >> 4));
	213	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
	214	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
	215	bar->flush(bar);
	216	return 0;
	217	}
	218
	219	static int
	220	nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
	221	struct nouveau_object *engine,
	222	struct nouveau_oclass oclass, void data, u32 size,
	223	struct nouveau_object **pobject)
ebb945a9 BS	224	{
	225	struct nouveau_bar *bar = nouveau_bar(parent);
	226	struct nv50_fifo_base base = (void )parent;
	227	struct nv50_fifo_chan *chan;
dbff2dee	228	struct nv50_channel_ind_class *args = data;
ebb945a9 BS	229	u64 ioffset, ilength;
ebb945a9 BS	230	int ret;
c420b2dc	231
ebb945a9 BS	232	if (size < sizeof(*args))
	233	return -EINVAL;
	234
	235	ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
	236	0x2000, args->pushbuf,
507ceb15 MP	237	(1ULL << NVDEV_ENGINE_DMAOBJ) \|
	238	(1ULL << NVDEV_ENGINE_SW) \|
	239	(1ULL << NVDEV_ENGINE_GR) \|
	240	(1ULL << NVDEV_ENGINE_MPEG) \|
	241	(1ULL << NVDEV_ENGINE_ME) \|
	242	(1ULL << NVDEV_ENGINE_VP) \|
	243	(1ULL << NVDEV_ENGINE_CRYPT) \|
	244	(1ULL << NVDEV_ENGINE_BSP) \|
	245	(1ULL << NVDEV_ENGINE_PPP) \|
	246	(1ULL << NVDEV_ENGINE_COPY0) \|
c42a7aec	247	(1ULL << NVDEV_ENGINE_VIC), &chan);
ebb945a9 BS	248	*pobject = nv_object(chan);
	249	if (ret)
	250	return ret;
c420b2dc	251
f50c8054 BS	252	ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
f50c8054 BS	253	&chan->ramht);
c420b2dc	254	if (ret)
ebb945a9 BS	255	return ret;
	256
	257	nv_parent(chan)->context_attach = nv84_fifo_context_attach;
	258	nv_parent(chan)->context_detach = nv84_fifo_context_detach;
	259	nv_parent(chan)->object_attach = nv84_fifo_object_attach;
	260	nv_parent(chan)->object_detach = nv50_fifo_object_detach;
	261
	262	ioffset = args->ioffset;
57be046e	263	ilength = order_base_2(args->ilength / 8);
ebb945a9 BS	264
	265	nv_wo32(base->ramfc, 0x3c, 0x403f6078);
	266	nv_wo32(base->ramfc, 0x44, 0x01003fff);
	267	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
	268	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
	269	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) \| (ilength << 16));
	270	nv_wo32(base->ramfc, 0x60, 0x7fffffff);
	271	nv_wo32(base->ramfc, 0x78, 0x00000000);
	272	nv_wo32(base->ramfc, 0x7c, 0x30000001);
	273	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) \|
	274	(4 << 24) /* SEARCH_FULL */ \|
	275	(chan->ramht->base.node->offset >> 4));
	276	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
	277	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
	278	bar->flush(bar);
	279	return 0;
c420b2dc BS	280	}
c420b2dc BS	281
ebb945a9 BS	282	static int
ebb945a9 BS	283	nv84_fifo_chan_init(struct nouveau_object *object)
c420b2dc	284	{
ebb945a9 BS	285	struct nv50_fifo_priv priv = (void )object->engine;
	286	struct nv50_fifo_base base = (void )object->parent;
	287	struct nv50_fifo_chan chan = (void )object;
	288	struct nouveau_gpuobj *ramfc = base->ramfc;
	289	u32 chid = chan->base.chid;
	290	int ret;
	291
	292	ret = nouveau_fifo_channel_init(&chan->base);
	293	if (ret)
	294	return ret;
c420b2dc	295
ebb945a9 BS	296	nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 \| ramfc->addr >> 8);
	297	nv50_fifo_playlist_update(priv);
	298	return 0;
	299	}
c420b2dc	300
ebb945a9	301	static struct nouveau_ofuncs
ab285892 BS	302	nv84_fifo_ofuncs_dma = {
	303	.ctor = nv84_fifo_chan_ctor_dma,
	304	.dtor = nv50_fifo_chan_dtor,
	305	.init = nv84_fifo_chan_init,
	306	.fini = nv50_fifo_chan_fini,
	307	.rd32 = _nouveau_fifo_channel_rd32,
	308	.wr32 = _nouveau_fifo_channel_wr32,
	309	};
	310
	311	static struct nouveau_ofuncs
	312	nv84_fifo_ofuncs_ind = {
	313	.ctor = nv84_fifo_chan_ctor_ind,
ebb945a9 BS	314	.dtor = nv50_fifo_chan_dtor,
	315	.init = nv84_fifo_chan_init,
	316	.fini = nv50_fifo_chan_fini,
	317	.rd32 = _nouveau_fifo_channel_rd32,
	318	.wr32 = _nouveau_fifo_channel_wr32,
	319	};
2064db72	320
ebb945a9 BS	321	static struct nouveau_oclass
ebb945a9 BS	322	nv84_fifo_sclass[] = {
c97f8c92 BS	323	{ NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
c97f8c92 BS	324	{ NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
ebb945a9 BS	325	{}
ebb945a9 BS	326	};
c420b2dc	327
ebb945a9 BS	328	/*******************************************************************************
	329	* FIFO context - basically just the instmem reserved for the channel
	330	******************************************************************************/
2064db72	331
5b8a43ae	332	static int
ebb945a9 BS	333	nv84_fifo_context_ctor(struct nouveau_object *parent,
	334	struct nouveau_object *engine,
	335	struct nouveau_oclass oclass, void data, u32 size,
	336	struct nouveau_object **pobject)
	337	{
	338	struct nv50_fifo_base *base;
	339	int ret;
c420b2dc	340
ebb945a9 BS	341	ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
	342	0x1000, NVOBJ_FLAG_HEAP, &base);
	343	*pobject = nv_object(base);
	344	if (ret)
	345	return ret;
c420b2dc	346
f50c8054	347	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
ebb945a9 BS	348	NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
	349	if (ret)
	350	return ret;
c420b2dc	351
f50c8054	352	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
ebb945a9 BS	353	0, &base->pgd);
	354	if (ret)
	355	return ret;
c420b2dc	356
ebb945a9 BS	357	ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
	358	if (ret)
	359	return ret;
c420b2dc	360
f50c8054 BS	361	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
f50c8054 BS	362	0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
ebb945a9 BS	363	if (ret)
	364	return ret;
	365
f50c8054 BS	366	ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
f50c8054 BS	367	0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
ebb945a9 BS	368	if (ret)
ebb945a9 BS	369	return ret;
c420b2dc	370
c420b2dc BS	371	return 0;
	372	}
	373
ebb945a9 BS	374	static struct nouveau_oclass
	375	nv84_fifo_cclass = {
	376	.handle = NV_ENGCTX(FIFO, 0x84),
	377	.ofuncs = &(struct nouveau_ofuncs) {
	378	.ctor = nv84_fifo_context_ctor,
	379	.dtor = nv50_fifo_context_dtor,
	380	.init = _nouveau_fifo_context_init,
	381	.fini = _nouveau_fifo_context_fini,
	382	.rd32 = _nouveau_fifo_context_rd32,
	383	.wr32 = _nouveau_fifo_context_wr32,
	384	},
	385	};
c420b2dc	386
ebb945a9 BS	387	/*******************************************************************************
	388	* PFIFO engine
	389	******************************************************************************/
c420b2dc	390
750087f1 BS	391	static void
	392	nv84_fifo_uevent_enable(struct nouveau_event *event, int index)
	393	{
	394	struct nv84_fifo_priv *priv = event->priv;
	395	nv_mask(priv, 0x002140, 0x40000000, 0x40000000);
	396	}
	397
	398	static void
	399	nv84_fifo_uevent_disable(struct nouveau_event *event, int index)
	400	{
	401	struct nv84_fifo_priv *priv = event->priv;
	402	nv_mask(priv, 0x002140, 0x40000000, 0x00000000);
	403	}
	404
ebb945a9 BS	405	static int
	406	nv84_fifo_ctor(struct nouveau_object parent, struct nouveau_object engine,
	407	struct nouveau_oclass oclass, void data, u32 size,
	408	struct nouveau_object **pobject)
c420b2dc	409	{
ebb945a9	410	struct nv50_fifo_priv *priv;
c420b2dc BS	411	int ret;
c420b2dc BS	412
ebb945a9 BS	413	ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
ebb945a9 BS	414	*pobject = nv_object(priv);
c420b2dc	415	if (ret)
ebb945a9	416	return ret;
c420b2dc	417
f50c8054	418	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
ebb945a9	419	&priv->playlist[0]);
c420b2dc	420	if (ret)
ebb945a9	421	return ret;
c420b2dc	422
f50c8054	423	ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
ebb945a9	424	&priv->playlist[1]);
c420b2dc	425	if (ret)
ebb945a9 BS	426	return ret;
ebb945a9 BS	427
750087f1 BS	428	priv->base.uevent->enable = nv84_fifo_uevent_enable;
	429	priv->base.uevent->disable = nv84_fifo_uevent_disable;
	430	priv->base.uevent->priv = priv;
	431
ebb945a9 BS	432	nv_subdev(priv)->unit = 0x00000100;
	433	nv_subdev(priv)->intr = nv04_fifo_intr;
	434	nv_engine(priv)->cclass = &nv84_fifo_cclass;
	435	nv_engine(priv)->sclass = nv84_fifo_sclass;
b1cd4976 RS	436	priv->base.pause = nv04_fifo_pause;
b1cd4976 RS	437	priv->base.start = nv04_fifo_start;
ebb945a9	438	return 0;
c420b2dc	439	}
ebb945a9	440
16c4f227 BS	441	struct nouveau_oclass *
16c4f227 BS	442	nv84_fifo_oclass = &(struct nouveau_oclass) {
ebb945a9 BS	443	.handle = NV_ENGINE(FIFO, 0x84),
	444	.ofuncs = &(struct nouveau_ofuncs) {
	445	.ctor = nv84_fifo_ctor,
	446	.dtor = nv50_fifo_dtor,
	447	.init = nv50_fifo_init,
	448	.fini = _nouveau_fifo_fini,
	449	},
	450	};