[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / core / engine / graph / fuc / gpc.fuc

/* fuc microcode for nvc0 PGRAPH/GPC
 *
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

/* TODO
 * - bracket certain functions with scratch writes, useful for debugging
 * - watchdog timer around ctx operations
 */

#ifdef INCLUDE_DATA
gpc_mmio_list_head:	.b32 #mmio_list_base
gpc_mmio_list_tail:
tpc_mmio_list_head:	.b32 #mmio_list_base
tpc_mmio_list_tail:
unk_mmio_list_head:	.b32 #mmio_list_base
unk_mmio_list_tail:	.b32 #mmio_list_base

gpc_id:			.b32 0

tpc_count:		.b32 0
tpc_mask:		.b32 0

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
unk_count:		.b32 0
unk_mask:		.b32 0
#endif

cmd_queue:		queue_init

mmio_list_base:
#endif

#ifdef INCLUDE_CODE
// reports an exception to the host
//
// In: $r15 error code (see nvc0.fuc)
//
error:
	push $r14
	mov $r14 -0x67ec 	// 0x9814
	sethi $r14 0x400000
	call #nv_wr32		// HUB_CTXCTL_CC_SCRATCH[5] = error code
	add b32 $r14 0x41c
	mov $r15 1
	call #nv_wr32		// HUB_CTXCTL_INTR_UP_SET
	pop $r14
	ret

// GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion.
//
// Input:
//   CC_SCRATCH[1]: context base
//
// Output:
//   CC_SCRATCH[0]:
//	     31:31: set to signal completion
//   CC_SCRATCH[1]:
//	      31:0: GPC context size
//
init:
	clear b32 $r0
	mov $sp $r0

	// enable fifo access
	mov $r1 0x1200
	mov $r2 2
	iowr I[$r1 + 0x000] $r2		// FIFO_ENABLE

	// setup i0 handler, and route all interrupts to it
	mov $r1 #ih
	mov $iv0 $r1
	mov $r1 0x400
	iowr I[$r1 + 0x300] $r0		// INTR_DISPATCH

	// enable fifo interrupt
	mov $r2 4
	iowr I[$r1 + 0x000] $r2		// INTR_EN_SET

	// enable interrupts
	bset $flags ie0

	// figure out which GPC we are, and how many TPCs we have
	mov $r1 0x608
	shl b32 $r1 6
	iord $r2 I[$r1 + 0x000]		// UNITS
	mov $r3 1
	and $r2 0x1f
	shl b32 $r3 $r2
	sub b32 $r3 1
	st b32 D[$r0 + #tpc_count] $r2
	st b32 D[$r0 + #tpc_mask] $r3
	add b32 $r1 0x400
	iord $r2 I[$r1 + 0x000]		// MYINDEX
	st b32 D[$r0 + #gpc_id] $r2

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// figure out which, and how many, UNKs are actually present
	mov $r14 0x0c30
	sethi $r14 0x500000
	clear b32 $r2
	clear b32 $r3
	clear b32 $r4
	init_unk_loop:
		call #nv_rd32
		cmp b32 $r15 0
		bra z #init_unk_next
			mov $r15 1
			shl b32 $r15 $r2
			or $r4 $r15
			add b32 $r3 1
		init_unk_next:
		add b32 $r2 1
		add b32 $r14 4
		cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
		bra ne #init_unk_loop
	init_unk_done:
	st b32 D[$r0 + #unk_count] $r3
	st b32 D[$r0 + #unk_mask] $r4
#endif

	// initialise context base, and size tracking
	mov $r2 0x800
	shl b32 $r2 6
	iord $r2 I[$r2 + 0x100]	// CC_SCRATCH[1], initial base
	clear b32 $r3		// track GPC context size here

	// set mmctx base addresses now so we don't have to do it later,
	// they don't currently ever change
	mov $r4 0x700
	shl b32 $r4 6
	shr b32 $r5 $r2 8
	iowr I[$r4 + 0x000] $r5		// MMCTX_SAVE_SWBASE
	iowr I[$r4 + 0x100] $r5		// MMCTX_LOAD_SWBASE

	// calculate GPC mmio context size
	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
	call #mmctx_size
	add b32 $r2 $r15
	add b32 $r3 $r15

	// calculate per-TPC mmio context size
	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
	call #mmctx_size
	ld b32 $r14 D[$r0 + #tpc_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// calculate per-UNK mmio context size
	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	call #mmctx_size
	ld b32 $r14 D[$r0 + #unk_count]
	mulu $r14 $r15
	add b32 $r2 $r14
	add b32 $r3 $r14
#endif

	// round up base/size to 256 byte boundary (for strand SWBASE)
	add b32 $r4 0x1300
	shr b32 $r3 2
	iowr I[$r4 + 0x000] $r3		// MMCTX_LOAD_COUNT, wtf for?!?
	shr b32 $r2 8
	shr b32 $r3 6
	add b32 $r2 1
	add b32 $r3 1
	shl b32 $r2 8
	shl b32 $r3 8

	// calculate size of strand context data
	mov b32 $r15 $r2
	call #strand_ctx_init
	add b32 $r3 $r15

	// save context size, and tell HUB we're done
	mov $r1 0x800
	shl b32 $r1 6
	iowr I[$r1 + 0x100] $r3		// CC_SCRATCH[1]  = context size
	add b32 $r1 0x800
	clear b32 $r2
	bset $r2 31
	iowr I[$r1 + 0x000] $r2		// CC_SCRATCH[0] |= 0x80000000

// Main program loop, very simple, sleeps until woken up by the interrupt
// handler, pulls a command from the queue and executes its handler
//
main:
	bset $flags $p0
	sleep $p0
	mov $r13 #cmd_queue
	call #queue_get
	bra $p1 #main

	// 0x0000-0x0003 are all context transfers
	cmpu b32 $r14 0x04
	bra nc #main_not_ctx_xfer
		// fetch $flags and mask off $p1/$p2
		mov $r1 $flags
		mov $r2 0x0006
		not b32 $r2
		and $r1 $r2
		// set $p1/$p2 according to transfer type
		shl b32 $r14 1
		or $r1 $r14
		mov $flags $r1
		// transfer context data
		call #ctx_xfer
		bra #main

	main_not_ctx_xfer:
	shl b32 $r15 $r14 16
	or $r15 E_BAD_COMMAND
	call #error
	bra #main

// interrupt handler
ih:
	push $r8
	mov $r8 $flags
	push $r8
	push $r9
	push $r10
	push $r11
	push $r13
	push $r14
	push $r15

	// incoming fifo command?
	iord $r10 I[$r0 + 0x200]	// INTR
	and $r11 $r10 0x00000004
	bra e #ih_no_fifo
		// queue incoming fifo command for later processing
		mov $r11 0x1900
		mov $r13 #cmd_queue
		iord $r14 I[$r11 + 0x100]	// FIFO_CMD
		iord $r15 I[$r11 + 0x000]	// FIFO_DATA
		call #queue_put
		add b32 $r11 0x400
		mov $r14 1
		iowr I[$r11 + 0x000] $r14	// FIFO_ACK

	// ack, and wake up main()
	ih_no_fifo:
	iowr I[$r0 + 0x100] $r10	// INTR_ACK

	pop $r15
	pop $r14
	pop $r13
	pop $r11
	pop $r10
	pop $r9
	pop $r8
	mov $flags $r8
	pop $r8
	bclr $flags $p0
	iret

// Set this GPC's bit in HUB_BAR, used to signal completion of various
// activities to the HUB fuc
//
hub_barrier_done:
	mov $r15 1
	ld b32 $r14 D[$r0 + #gpc_id]
	shl b32 $r15 $r14
	mov $r14 -0x6be8 	// 0x409418 - HUB_BAR_SET
	sethi $r14 0x400000
	call #nv_wr32
	ret

// Disables various things, waits a bit, and re-enables them..
//
// Not sure how exactly this helps, perhaps "ENABLE" is not such a
// good description for the bits we turn off?  Anyways, without this,
// funny things happen.
//
ctx_redswitch:
	mov $r14 0x614
	shl b32 $r14 6
	mov $r15 0x020
	iowr I[$r14] $r15	// GPC_RED_SWITCH = POWER
	mov $r15 8
	ctx_redswitch_delay:
		sub b32 $r15 1
		bra ne #ctx_redswitch_delay
	mov $r15 0xa20
	iowr I[$r14] $r15	// GPC_RED_SWITCH = UNK11, ENABLE, POWER
	ret

// Transfer GPC context data between GPU and storage area
//
// In: $r15 context base address
//     $p1 clear on save, set on load
//     $p2 set if opposite direction done/will be done, so:
//		on save it means: "a load will follow this save"
//		on load it means: "a save preceeded this load"
//
ctx_xfer:
	// set context base address
	mov $r1 0xa04
	shl b32 $r1 6
	iowr I[$r1 + 0x000] $r15// MEM_BASE
	bra not $p1 #ctx_xfer_not_load
		call #ctx_redswitch
	ctx_xfer_not_load:

	// strands
	mov $r1 0x4afc
	sethi $r1 0x20000
	mov $r2 0xc
	iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0c
	call #strand_wait
	mov $r2 0x47fc
	sethi $r2 0x20000
	iowr I[$r2] $r0		// STRAND_FIRST_GENE(0x3f) = 0x00
	xbit $r2 $flags $p1
	add b32 $r2 3
	iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)

	// mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 2		// first
	mov $r11 0x0000
	sethi $r11 0x500000
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn
	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
	mov $r14 0		// not multi
	call #mmctx_xfer

	// per-TPC mmio context
	xbit $r10 $flags $p1	// direction
	mov $r11 0x4000
	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_TPC0
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0
	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	ld b32 $r15 D[$r0 + #tpc_mask]
	mov $r14 0x800		// stride = 0x800
	call #mmctx_xfer

#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	// per-UNK mmio context
	xbit $r10 $flags $p1	// direction
	or $r10 4		// last
	mov $r11 0x3000
	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_UNK0
	ld b32 $r12 D[$r0 + #gpc_id]
	shl b32 $r12 15
	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	ld b32 $r15 D[$r0 + #unk_mask]
	mov $r14 0x200		// stride = 0x200
	call #mmctx_xfer
#endif

	// wait for strands to finish
	call #strand_wait

	// if load, or a save without a load following, do some
	// unknown stuff that's done after finishing a block of
	// strand commands
	bra $p1 #ctx_xfer_post
	bra not $p2 #ctx_xfer_done
	ctx_xfer_post:
		mov $r1 0x4afc
		sethi $r1 0x20000
		mov $r2 0xd
		iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0d
		call #strand_wait

	// mark completion in HUB's barrier
	ctx_xfer_done:
	call #hub_barrier_done
	ret
#endif
Commit	Line	Data
e99716f1 BS	1	/* fuc microcode for nvc0 PGRAPH/GPC
	2	*
	3	* Copyright 2011 Red Hat Inc.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	21	* OTHER DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors: Ben Skeggs
	24	*/
	25
	26	/* TODO
	27	* - bracket certain functions with scratch writes, useful for debugging
	28	* - watchdog timer around ctx operations
	29	*/
	30
	31	#ifdef INCLUDE_DATA
a32b2ffb BS	32	gpc_mmio_list_head: .b32 #mmio_list_base
	33	gpc_mmio_list_tail:
	34	tpc_mmio_list_head: .b32 #mmio_list_base
	35	tpc_mmio_list_tail:
	36	unk_mmio_list_head: .b32 #mmio_list_base
	37	unk_mmio_list_tail: .b32 #mmio_list_base
	38
e99716f1	39	gpc_id: .b32 0
e99716f1 BS	40
	41	tpc_count: .b32 0
	42	tpc_mask: .b32 0
e99716f1	43
26410c67	44	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
f8adeb82 BS	45	unk_count: .b32 0
f8adeb82 BS	46	unk_mask: .b32 0
5ee86c41 BS	47	#endif
5ee86c41 BS	48
e99716f1	49	cmd_queue: queue_init
a32b2ffb BS	50
a32b2ffb BS	51	mmio_list_base:
e99716f1 BS	52	#endif
	53
	54	#ifdef INCLUDE_CODE
	55	// reports an exception to the host
	56	//
	57	// In: $r15 error code (see nvc0.fuc)
	58	//
	59	error:
	60	push $r14
	61	mov $r14 -0x67ec // 0x9814
	62	sethi $r14 0x400000
	63	call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
	64	add b32 $r14 0x41c
	65	mov $r15 1
	66	call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
	67	pop $r14
	68	ret
	69
	70	// GPC fuc initialisation, executed by triggering ucode start, will
	71	// fall through to main loop after completion.
	72	//
	73	// Input:
e99716f1 BS	74	// CC_SCRATCH[1]: context base
	75	//
	76	// Output:
	77	// CC_SCRATCH[0]:
	78	// 31:31: set to signal completion
	79	// CC_SCRATCH[1]:
	80	// 31:0: GPC context size
	81	//
	82	init:
	83	clear b32 $r0
	84	mov $sp $r0
	85
	86	// enable fifo access
	87	mov $r1 0x1200
	88	mov $r2 2
	89	iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
	90
	91	// setup i0 handler, and route all interrupts to it
	92	mov $r1 #ih
	93	mov $iv0 $r1
	94	mov $r1 0x400
	95	iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
	96
	97	// enable fifo interrupt
	98	mov $r2 4
	99	iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
	100
	101	// enable interrupts
	102	bset $flags ie0
	103
	104	// figure out which GPC we are, and how many TPCs we have
	105	mov $r1 0x608
	106	shl b32 $r1 6
	107	iord $r2 I[$r1 + 0x000] // UNITS
	108	mov $r3 1
	109	and $r2 0x1f
	110	shl b32 $r3 $r2
	111	sub b32 $r3 1
	112	st b32 D[$r0 + #tpc_count] $r2
	113	st b32 D[$r0 + #tpc_mask] $r3
	114	add b32 $r1 0x400
	115	iord $r2 I[$r1 + 0x000] // MYINDEX
	116	st b32 D[$r0 + #gpc_id] $r2
	117
f8adeb82 BS	118	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
	119	// figure out which, and how many, UNKs are actually present
	120	mov $r14 0x0c30
	121	sethi $r14 0x500000
	122	clear b32 $r2
	123	clear b32 $r3
	124	clear b32 $r4
	125	init_unk_loop:
	126	call #nv_rd32
	127	cmp b32 $r15 0
	128	bra z #init_unk_next
	129	mov $r15 1
	130	shl b32 $r15 $r2
	131	or $r4 $r15
	132	add b32 $r3 1
	133	init_unk_next:
	134	add b32 $r2 1
	135	add b32 $r14 4
	136	cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
	137	bra ne #init_unk_loop
	138	init_unk_done:
	139	st b32 D[$r0 + #unk_count] $r3
	140	st b32 D[$r0 + #unk_mask] $r4
	141	#endif
	142
e99716f1	143	// initialise context base, and size tracking
e99716f1 BS	144	mov $r2 0x800
	145	shl b32 $r2 6
	146	iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
	147	clear b32 $r3 // track GPC context size here
	148
	149	// set mmctx base addresses now so we don't have to do it later,
	150	// they don't currently ever change
	151	mov $r4 0x700
	152	shl b32 $r4 6
	153	shr b32 $r5 $r2 8
	154	iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
	155	iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
	156
a32b2ffb BS	157	// calculate GPC mmio context size
	158	ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
	159	ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
e99716f1 BS	160	call #mmctx_size
	161	add b32 $r2 $r15
	162	add b32 $r3 $r15
	163
a32b2ffb BS	164	// calculate per-TPC mmio context size
	165	ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
	166	ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
e99716f1 BS	167	call #mmctx_size
	168	ld b32 $r14 D[$r0 + #tpc_count]
	169	mulu $r14 $r15
	170	add b32 $r2 $r14
	171	add b32 $r3 $r14
	172
26410c67	173	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
5ee86c41 BS	174	// calculate per-UNK mmio context size
	175	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
	176	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
	177	call #mmctx_size
	178	ld b32 $r14 D[$r0 + #unk_count]
	179	mulu $r14 $r15
	180	add b32 $r2 $r14
	181	add b32 $r3 $r14
	182	#endif
	183
e99716f1 BS	184	// round up base/size to 256 byte boundary (for strand SWBASE)
	185	add b32 $r4 0x1300
	186	shr b32 $r3 2
	187	iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
	188	shr b32 $r2 8
	189	shr b32 $r3 6
	190	add b32 $r2 1
	191	add b32 $r3 1
	192	shl b32 $r2 8
	193	shl b32 $r3 8
	194
	195	// calculate size of strand context data
	196	mov b32 $r15 $r2
	197	call #strand_ctx_init
	198	add b32 $r3 $r15
	199
	200	// save context size, and tell HUB we're done
	201	mov $r1 0x800
	202	shl b32 $r1 6
	203	iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
	204	add b32 $r1 0x800
	205	clear b32 $r2
	206	bset $r2 31
	207	iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] \|= 0x80000000
	208
	209	// Main program loop, very simple, sleeps until woken up by the interrupt
	210	// handler, pulls a command from the queue and executes its handler
	211	//
	212	main:
	213	bset $flags $p0
	214	sleep $p0
	215	mov $r13 #cmd_queue
	216	call #queue_get
	217	bra $p1 #main
	218
	219	// 0x0000-0x0003 are all context transfers
	220	cmpu b32 $r14 0x04
	221	bra nc #main_not_ctx_xfer
	222	// fetch $flags and mask off $p1/$p2
	223	mov $r1 $flags
	224	mov $r2 0x0006
	225	not b32 $r2
	226	and $r1 $r2
	227	// set $p1/$p2 according to transfer type
	228	shl b32 $r14 1
	229	or $r1 $r14
	230	mov $flags $r1
	231	// transfer context data
	232	call #ctx_xfer
	233	bra #main
	234
	235	main_not_ctx_xfer:
	236	shl b32 $r15 $r14 16
	237	or $r15 E_BAD_COMMAND
	238	call #error
	239	bra #main
	240
	241	// interrupt handler
	242	ih:
	243	push $r8
	244	mov $r8 $flags
	245	push $r8
	246	push $r9
	247	push $r10
248	push $r11
249	push $r13
250	push $r14
251	push $r15
252
253	// incoming fifo command?
254	iord $r10 I[$r0 + 0x200] // INTR
255	and $r11 $r10 0x00000004
256	bra e #ih_no_fifo
257	// queue incoming fifo command for later processing
258	mov $r11 0x1900
259	mov $r13 #cmd_queue
260	iord $r14 I[$r11 + 0x100] // FIFO_CMD
261	iord $r15 I[$r11 + 0x000] // FIFO_DATA
262	call #queue_put
263	add b32 $r11 0x400
264	mov $r14 1
265	iowr I[$r11 + 0x000] $r14 // FIFO_ACK
266
267	// ack, and wake up main()
268	ih_no_fifo:
269	iowr I[$r0 + 0x100] $r10 // INTR_ACK
270
271	pop $r15
272	pop $r14
273	pop $r13
274	pop $r11
275	pop $r10
276	pop $r9
277	pop $r8
278	mov $flags $r8
279	pop $r8
280	bclr $flags $p0
281	iret
282
283	// Set this GPC's bit in HUB_BAR, used to signal completion of various
284	// activities to the HUB fuc
285	//
286	hub_barrier_done:
287	mov $r15 1
288	ld b32 $r14 D[$r0 + #gpc_id]
289	shl b32 $r15 $r14
290	mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
291	sethi $r14 0x400000
292	call #nv_wr32
293	ret
294
295	// Disables various things, waits a bit, and re-enables them..
296	//
297	// Not sure how exactly this helps, perhaps "ENABLE" is not such a
298	// good description for the bits we turn off? Anyways, without this,
299	// funny things happen.
300	//
301	ctx_redswitch:
302	mov $r14 0x614
303	shl b32 $r14 6
304	mov $r15 0x020
305	iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
306	mov $r15 8
307	ctx_redswitch_delay:
308	sub b32 $r15 1
309	bra ne #ctx_redswitch_delay
310	mov $r15 0xa20
311	iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
312	ret
313
314	// Transfer GPC context data between GPU and storage area
315	//
316	// In: $r15 context base address
317	// $p1 clear on save, set on load
318	// $p2 set if opposite direction done/will be done, so:
319	// on save it means: "a load will follow this save"
320	// on load it means: "a save preceeded this load"
321	//
322	ctx_xfer:
323	// set context base address
324	mov $r1 0xa04
325	shl b32 $r1 6
326	iowr I[$r1 + 0x000] $r15// MEM_BASE
327	bra not $p1 #ctx_xfer_not_load
328	call #ctx_redswitch
329	ctx_xfer_not_load:
330
331	// strands
332	mov $r1 0x4afc
333	sethi $r1 0x20000
334	mov $r2 0xc
335	iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
336	call #strand_wait
337	mov $r2 0x47fc
338	sethi $r2 0x20000
339	iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
340	xbit $r2 $flags $p1
341	add b32 $r2 3
342	iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
343
344	// mmio context
345	xbit $r10 $flags $p1 // direction
346	or $r10 2 // first
347	mov $r11 0x0000
348	sethi $r11 0x500000
349	ld b32 $r12 D[$r0 + #gpc_id]
350	shl b32 $r12 15
351	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
352	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
353	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
354	mov $r14 0 // not multi
355	call #mmctx_xfer
356
357	// per-TPC mmio context
358	xbit $r10 $flags $p1 // direction
e99716f1 BS	359	mov $r11 0x4000
	360	sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
	361	ld b32 $r12 D[$r0 + #gpc_id]
	362	shl b32 $r12 15
	363	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
	364	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
	365	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
	366	ld b32 $r15 D[$r0 + #tpc_mask]
	367	mov $r14 0x800 // stride = 0x800
	368	call #mmctx_xfer
	369
26410c67	370	#if NV_PGRAPH_GPCX_UNK__SIZE > 0
5ee86c41 BS	371	// per-UNK mmio context
	372	xbit $r10 $flags $p1 // direction
	373	or $r10 4 // last
	374	mov $r11 0x3000
	375	sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0
	376	ld b32 $r12 D[$r0 + #gpc_id]
	377	shl b32 $r12 15
	378	add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0
	379	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
	380	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
	381	ld b32 $r15 D[$r0 + #unk_mask]
	382	mov $r14 0x200 // stride = 0x200
	383	call #mmctx_xfer
	384	#endif
	385
e99716f1 BS	386	// wait for strands to finish
	387	call #strand_wait
	388
	389	// if load, or a save without a load following, do some
	390	// unknown stuff that's done after finishing a block of
	391	// strand commands
	392	bra $p1 #ctx_xfer_post
	393	bra not $p2 #ctx_xfer_done
	394	ctx_xfer_post:
	395	mov $r1 0x4afc
	396	sethi $r1 0x20000
	397	mov $r2 0xd
	398	iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
	399	call #strand_wait
	400
	401	// mark completion in HUB's barrier
	402	ctx_xfer_done:
	403	call #hub_barrier_done
	404	ret
	405	#endif