[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / core / engine / graph / nv40.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/os.h>
#include <core/class.h>
#include <core/handle.h>
#include <core/engctx.h>

#include <subdev/fb.h>
#include <subdev/timer.h>

#include <engine/graph.h>
#include <engine/fifo.h>

#include "nv40.h"
#include "regs.h"

struct nv40_graph_priv {
	struct nouveau_graph base;
	u32 size;
};

struct nv40_graph_chan {
	struct nouveau_graph_chan base;
};

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static int
nv40_graph_object_ctor(struct nouveau_object *parent,
		       struct nouveau_object *engine,
		       struct nouveau_oclass *oclass, void *data, u32 size,
		       struct nouveau_object **pobject)
{
	struct nouveau_gpuobj *obj;
	int ret;

	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
				    20, 16, 0, &obj);
	*pobject = nv_object(obj);
	if (ret)
		return ret;

	nv_wo32(obj, 0x00, nv_mclass(obj));
	nv_wo32(obj, 0x04, 0x00000000);
	nv_wo32(obj, 0x08, 0x00000000);
#ifdef __BIG_ENDIAN
	nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
#endif
	nv_wo32(obj, 0x0c, 0x00000000);
	nv_wo32(obj, 0x10, 0x00000000);
	return 0;
}

static struct nouveau_ofuncs
nv40_graph_ofuncs = {
	.ctor = nv40_graph_object_ctor,
	.dtor = _nouveau_gpuobj_dtor,
	.init = _nouveau_gpuobj_init,
	.fini = _nouveau_gpuobj_fini,
	.rd32 = _nouveau_gpuobj_rd32,
	.wr32 = _nouveau_gpuobj_wr32,
};

static struct nouveau_oclass
nv40_graph_sclass[] = {
	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
	{ 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
	{},
};

static struct nouveau_oclass
nv44_graph_sclass[] = {
	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
	{ 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv40_graph_context_ctor(struct nouveau_object *parent,
			struct nouveau_object *engine,
			struct nouveau_oclass *oclass, void *data, u32 size,
			struct nouveau_object **pobject)
{
	struct nv40_graph_priv *priv = (void *)engine;
	struct nv40_graph_chan *chan;
	int ret;

	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
					   priv->size, 16,
					   NVOBJ_FLAG_ZERO_ALLOC, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
	nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
	return 0;
}

static int
nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
{
	struct nv40_graph_priv *priv = (void *)object->engine;
	struct nv40_graph_chan *chan = (void *)object;
	u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
	int ret = 0;

	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);

	if (nv_rd32(priv, 0x40032c) == inst) {
		if (suspend) {
			nv_wr32(priv, 0x400720, 0x00000000);
			nv_wr32(priv, 0x400784, inst);
			nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
			nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
			if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
				u32 insn = nv_rd32(priv, 0x400308);
				nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
				ret = -EBUSY;
			}
		}

		nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
	}

	if (nv_rd32(priv, 0x400330) == inst)
		nv_mask(priv, 0x400330, 0x01000000, 0x00000000);

	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
	return ret;
}

static struct nouveau_oclass
nv40_graph_cclass = {
	.handle = NV_ENGCTX(GR, 0x40),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv40_graph_context_ctor,
		.dtor = _nouveau_graph_context_dtor,
		.init = _nouveau_graph_context_init,
		.fini = nv40_graph_context_fini,
		.rd32 = _nouveau_graph_context_rd32,
		.wr32 = _nouveau_graph_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

static void
nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
{
	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	struct nv40_graph_priv *priv = (void *)engine;
	unsigned long flags;

	pfifo->pause(pfifo, &flags);
	nv04_graph_idle(priv);

	switch (nv_device(priv)->chipset) {
	case 0x40:
	case 0x41: /* guess */
	case 0x42:
	case 0x43:
	case 0x45: /* guess */
	case 0x4e:
		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	case 0x44:
	case 0x4a:
		nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
		break;
	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
	case 0x4c:
	case 0x67:
	default:
		nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
		nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	}

	pfifo->start(pfifo, &flags);
}

static void
nv40_graph_intr(struct nouveau_subdev *subdev)
{
	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
	struct nouveau_engine *engine = nv_engine(subdev);
	struct nouveau_object *engctx;
	struct nouveau_handle *handle = NULL;
	struct nv40_graph_priv *priv = (void *)subdev;
	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
	u32 show = stat;
	int chid;

	engctx = nouveau_engctx_get(engine, inst);
	chid   = pfifo->chid(pfifo, engctx);

	if (stat & NV_PGRAPH_INTR_ERROR) {
		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
			handle = nouveau_handle_get_class(engctx, class);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~NV_PGRAPH_INTR_ERROR;
			nouveau_handle_put(handle);
		}

		if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
			nv_mask(priv, 0x402000, 0, 0);
		}
	}

	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nv_info(priv, "");
		nouveau_bitfield_print(nv10_graph_intr_name, show);
		printk(" nsource:");
		nouveau_bitfield_print(nv04_graph_nsource, nsource);
		printk(" nstatus:");
		nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
		printk("\n");
		nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x "
			       "mthd 0x%04x data 0x%08x\n",
			 chid, inst << 4, subc, class, mthd, data);
	}

	nouveau_engctx_put(engctx);
}

static int
nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	       struct nouveau_oclass *oclass, void *data, u32 size,
	       struct nouveau_object **pobject)
{
	struct nv40_graph_priv *priv;
	int ret;

	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv40_graph_intr;
	nv_engine(priv)->cclass = &nv40_graph_cclass;
	if (nv44_graph_class(priv))
		nv_engine(priv)->sclass = nv44_graph_sclass;
	else
		nv_engine(priv)->sclass = nv40_graph_sclass;
	nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
	return 0;
}

static int
nv40_graph_init(struct nouveau_object *object)
{
	struct nouveau_engine *engine = nv_engine(object);
	struct nouveau_fb *pfb = nouveau_fb(object);
	struct nv40_graph_priv *priv = (void *)engine;
	int ret, i, j;
	u32 vramsz;

	ret = nouveau_graph_init(&priv->base);
	if (ret)
		return ret;

	/* generate and upload context program */
	ret = nv40_grctx_init(nv_device(priv), &priv->size);
	if (ret)
		return ret;

	/* No context present currently */
	nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(priv, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(priv, 0x405000, i);
	}

	if (nv_device(priv)->chipset == 0x40) {
		nv_wr32(priv, 0x4009b0, 0x83280fff);
		nv_wr32(priv, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(priv, 0x400820, 0x83280eff);
		nv_wr32(priv, 0x400824, 0x000000a0);
	}

	switch (nv_device(priv)->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(priv, 0x4009b8, 0x0078e366);
		nv_wr32(priv, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(priv, 0x400828, 0x007596ff);
		nv_wr32(priv, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(priv, 0x400828, 0x0072cb77);
		nv_wr32(priv, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(priv, 0x400860, 0);
		nv_wr32(priv, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(priv, 0x400828, 0x07830610);
		nv_wr32(priv, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(priv, 0x400b38, 0x2ffff800);
	nv_wr32(priv, 0x400b3c, 0x00006000);

	/* Tiling related stuff. */
	switch (nv_device(priv)->chipset) {
	case 0x44:
	case 0x4a:
		nv_wr32(priv, 0x400bc4, 0x1003d888);
		nv_wr32(priv, 0x400bbc, 0xb7a7b500);
		break;
	case 0x46:
		nv_wr32(priv, 0x400bc4, 0x0000e024);
		nv_wr32(priv, 0x400bbc, 0xb7a7b520);
		break;
	case 0x4c:
	case 0x4e:
	case 0x67:
		nv_wr32(priv, 0x400bc4, 0x1003d888);
		nv_wr32(priv, 0x400bbc, 0xb7a7b540);
		break;
	default:
		break;
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->tile.regions; i++)
		engine->tile_prog(engine, i);

	/* begin RAM config */
	vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
	switch (nv_device(priv)->chipset) {
	case 0x40:
		nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
		nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
		nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
		nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
		nv_wr32(priv, 0x400820, 0);
		nv_wr32(priv, 0x400824, 0);
		nv_wr32(priv, 0x400864, vramsz);
		nv_wr32(priv, 0x400868, vramsz);
		break;
	default:
		switch (nv_device(priv)->chipset) {
		case 0x41:
		case 0x42:
		case 0x43:
		case 0x45:
		case 0x4e:
		case 0x44:
		case 0x4a:
			nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
			nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
			break;
		default:
			nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
			nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
			break;
		}
		nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
		nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
		nv_wr32(priv, 0x400840, 0);
		nv_wr32(priv, 0x400844, 0);
		nv_wr32(priv, 0x4008A0, vramsz);
		nv_wr32(priv, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

struct nouveau_oclass
nv40_graph_oclass = {
	.handle = NV_ENGINE(GR, 0x40),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv40_graph_ctor,
		.dtor = _nouveau_graph_dtor,
		.init = nv40_graph_init,
		.fini = _nouveau_graph_fini,
	},
};
Commit	Line	Data
6ee73861	1	/*
ebb945a9	2	* Copyright 2012 Red Hat Inc.
6ee73861	3	*
ebb945a9 BS	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
6ee73861	10	*
ebb945a9 BS	11	* The above copyright notice and this permission notice shall be included in
ebb945a9 BS	12	* all copies or substantial portions of the Software.
6ee73861	13	*
ebb945a9 BS	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
6ee73861	21	*
ebb945a9	22	* Authors: Ben Skeggs
6ee73861 BS	23	*/
6ee73861 BS	24
ebb945a9 BS	25	#include <core/os.h>
	26	#include <core/class.h>
	27	#include <core/handle.h>
	28	#include <core/engctx.h>
	29
	30	#include <subdev/fb.h>
	31	#include <subdev/timer.h>
	32
	33	#include <engine/graph.h>
02a841d4	34	#include <engine/fifo.h>
6ee73861	35
ebb945a9 BS	36	#include "nv40.h"
	37	#include "regs.h"
	38
	39	struct nv40_graph_priv {
	40	struct nouveau_graph base;
	41	u32 size;
39c8d368	42	};
b8c157d3	43
ebb945a9 BS	44	struct nv40_graph_chan {
	45	struct nouveau_graph_chan base;
	46	};
	47
	48	/*******************************************************************************
	49	* Graphics object classes
	50	******************************************************************************/
	51
39c8d368	52	static int
ebb945a9 BS	53	nv40_graph_object_ctor(struct nouveau_object *parent,
	54	struct nouveau_object *engine,
	55	struct nouveau_oclass oclass, void data, u32 size,
	56	struct nouveau_object **pobject)
39c8d368	57	{
ebb945a9	58	struct nouveau_gpuobj *obj;
39c8d368 BS	59	int ret;
39c8d368 BS	60
ebb945a9 BS	61	ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
	62	20, 16, 0, &obj);
	63	*pobject = nv_object(obj);
6ee73861 BS	64	if (ret)
	65	return ret;
	66
ebb945a9 BS	67	nv_wo32(obj, 0x00, nv_mclass(obj));
	68	nv_wo32(obj, 0x04, 0x00000000);
	69	nv_wo32(obj, 0x08, 0x00000000);
	70	#ifdef __BIG_ENDIAN
	71	nv_mo32(obj, 0x08, 0x01000000, 0x01000000);
	72	#endif
	73	nv_wo32(obj, 0x0c, 0x00000000);
	74	nv_wo32(obj, 0x10, 0x00000000);
6ee73861 BS	75	return 0;
	76	}
	77
5b8a43ae	78	static struct nouveau_ofuncs
ebb945a9 BS	79	nv40_graph_ofuncs = {
	80	.ctor = nv40_graph_object_ctor,
	81	.dtor = _nouveau_gpuobj_dtor,
	82	.init = _nouveau_gpuobj_init,
	83	.fini = _nouveau_gpuobj_fini,
	84	.rd32 = _nouveau_gpuobj_rd32,
	85	.wr32 = _nouveau_gpuobj_wr32,
	86	};
6ee73861	87
ebb945a9 BS	88	static struct nouveau_oclass
	89	nv40_graph_sclass[] = {
	90	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
	91	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
	92	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
	93	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
	94	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
	95	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
	96	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
	97	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
	98	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
	99	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
	100	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
	101	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
	102	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
	103	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
	104	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
	105	{ 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */
	106	{},
	107	};
	108
	109	static struct nouveau_oclass
	110	nv44_graph_sclass[] = {
	111	{ 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */
	112	{ 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */
	113	{ 0x0030, &nv40_graph_ofuncs, NULL }, /* null */
	114	{ 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */
	115	{ 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */
	116	{ 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */
	117	{ 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */
	118	{ 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */
	119	{ 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */
	120	{ 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */
	121	{ 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */
	122	{ 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */
	123	{ 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */
	124	{ 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */
	125	{ 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */
	126	{ 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */
	127	{},
	128	};
	129
	130	/*******************************************************************************
	131	* PGRAPH context
	132	******************************************************************************/
6ee73861	133
ebb945a9 BS	134	static int
	135	nv40_graph_context_ctor(struct nouveau_object *parent,
	136	struct nouveau_object *engine,
	137	struct nouveau_oclass oclass, void data, u32 size,
	138	struct nouveau_object **pobject)
4ea52f89	139	{
ebb945a9 BS	140	struct nv40_graph_priv priv = (void )engine;
ebb945a9 BS	141	struct nv40_graph_chan *chan;
4ea52f89 BS	142	int ret;
4ea52f89 BS	143
ebb945a9 BS	144	ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
	145	priv->size, 16,
	146	NVOBJ_FLAG_ZERO_ALLOC, &chan);
	147	*pobject = nv_object(chan);
4ea52f89 BS	148	if (ret)
4ea52f89 BS	149	return ret;
4ea52f89	150
ebb945a9 BS	151	nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan));
	152	nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4);
	153	return 0;
	154	}
	155
	156	static int
	157	nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
	158	{
a4dd4ec2 MS	159	struct nv40_graph_priv priv = (void )object->engine;
a4dd4ec2 MS	160	struct nv40_graph_chan chan = (void )object;
ebb945a9 BS	161	u32 inst = 0x01000000 \| nv_gpuobj(chan)->addr >> 4;
	162	int ret = 0;
	163
	164	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	165
	166	if (nv_rd32(priv, 0x40032c) == inst) {
	167	if (suspend) {
	168	nv_wr32(priv, 0x400720, 0x00000000);
	169	nv_wr32(priv, 0x400784, inst);
	170	nv_mask(priv, 0x400310, 0x00000020, 0x00000020);
	171	nv_mask(priv, 0x400304, 0x00000001, 0x00000001);
	172	if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) {
	173	u32 insn = nv_rd32(priv, 0x400308);
	174	nv_warn(priv, "ctxprog timeout 0x%08x\n", insn);
	175	ret = -EBUSY;
	176	}
	177	}
4ea52f89	178
ebb945a9 BS	179	nv_mask(priv, 0x40032c, 0x01000000, 0x00000000);
	180	}
	181
	182	if (nv_rd32(priv, 0x400330) == inst)
	183	nv_mask(priv, 0x400330, 0x01000000, 0x00000000);
	184
	185	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
4ea52f89 BS	186	return ret;
	187	}
	188
ebb945a9 BS	189	static struct nouveau_oclass
	190	nv40_graph_cclass = {
	191	.handle = NV_ENGCTX(GR, 0x40),
	192	.ofuncs = &(struct nouveau_ofuncs) {
	193	.ctor = nv40_graph_context_ctor,
	194	.dtor = _nouveau_graph_context_dtor,
	195	.init = _nouveau_graph_context_init,
	196	.fini = nv40_graph_context_fini,
	197	.rd32 = _nouveau_graph_context_rd32,
	198	.wr32 = _nouveau_graph_context_wr32,
	199	},
	200	};
	201
	202	/*******************************************************************************
	203	* PGRAPH engine/subdev functions
	204	******************************************************************************/
	205
96c50082	206	static void
ebb945a9	207	nv40_graph_tile_prog(struct nouveau_engine *engine, int i)
0d87c100	208	{
ebb945a9 BS	209	struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
	210	struct nouveau_fifo *pfifo = nouveau_fifo(engine);
	211	struct nv40_graph_priv priv = (void )engine;
	212	unsigned long flags;
	213
	214	pfifo->pause(pfifo, &flags);
	215	nv04_graph_idle(priv);
0d87c100	216
ebb945a9	217	switch (nv_device(priv)->chipset) {
1dc32671 BS	218	case 0x40:
	219	case 0x41: /* guess */
	220	case 0x42:
	221	case 0x43:
	222	case 0x45: /* guess */
	223	case 0x4e:
ebb945a9 BS	224	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	225	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	226	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
	227	nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	228	nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	229	nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
1dc32671	230	break;
0d87c100 FJ	231	case 0x44:
0d87c100 FJ	232	case 0x4a:
ebb945a9 BS	233	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	234	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	235	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
0d87c100	236	break;
0d87c100 FJ	237	case 0x46:
	238	case 0x47:
	239	case 0x49:
	240	case 0x4b:
1dc32671 BS	241	case 0x4c:
	242	case 0x67:
	243	default:
ebb945a9 BS	244	nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch);
	245	nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit);
	246	nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr);
	247	nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	248	nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	249	nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr);
0d87c100	250	break;
0d87c100	251	}
ebb945a9 BS	252
ebb945a9 BS	253	pfifo->start(pfifo, &flags);
0d87c100 FJ	254	}
0d87c100 FJ	255
ebb945a9 BS	256	static void
	257	nv40_graph_intr(struct nouveau_subdev *subdev)
	258	{
72a14827	259	struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
ebb945a9	260	struct nouveau_engine *engine = nv_engine(subdev);
72a14827	261	struct nouveau_object *engctx;
ebb945a9	262	struct nouveau_handle *handle = NULL;
72a14827	263	struct nv40_graph_priv priv = (void )subdev;
ebb945a9 BS	264	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	265	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	266	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
72a14827	267	u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff;
ebb945a9 BS	268	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	269	u32 subc = (addr & 0x00070000) >> 16;
	270	u32 mthd = (addr & 0x00001ffc);
	271	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	272	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff;
	273	u32 show = stat;
72a14827 BS	274	int chid;
	275
	276	engctx = nouveau_engctx_get(engine, inst);
	277	chid = pfifo->chid(pfifo, engctx);
ebb945a9 BS	278
	279	if (stat & NV_PGRAPH_INTR_ERROR) {
	280	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
72a14827	281	handle = nouveau_handle_get_class(engctx, class);
ebb945a9 BS	282	if (handle && !nv_call(handle->object, mthd, data))
ebb945a9 BS	283	show &= ~NV_PGRAPH_INTR_ERROR;
72a14827	284	nouveau_handle_put(handle);
ebb945a9 BS	285	}
	286
	287	if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
	288	nv_mask(priv, 0x402000, 0, 0);
	289	}
	290	}
	291
	292	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	293	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
	294
	295	if (show) {
	296	nv_info(priv, "");
	297	nouveau_bitfield_print(nv10_graph_intr_name, show);
	298	printk(" nsource:");
	299	nouveau_bitfield_print(nv04_graph_nsource, nsource);
	300	printk(" nstatus:");
	301	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
	302	printk("\n");
72a14827	303	nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x "
ebb945a9	304	"mthd 0x%04x data 0x%08x\n",
72a14827	305	chid, inst << 4, subc, class, mthd, data);
ebb945a9	306	}
72a14827 BS	307
72a14827 BS	308	nouveau_engctx_put(engctx);
ebb945a9 BS	309	}
	310
	311	static int
	312	nv40_graph_ctor(struct nouveau_object parent, struct nouveau_object engine,
	313	struct nouveau_oclass oclass, void data, u32 size,
	314	struct nouveau_object **pobject)
6ee73861	315	{
ebb945a9 BS	316	struct nv40_graph_priv *priv;
	317	int ret;
	318
	319	ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
	320	*pobject = nv_object(priv);
	321	if (ret)
	322	return ret;
6ee73861	323
ebb945a9 BS	324	nv_subdev(priv)->unit = 0x00001000;
	325	nv_subdev(priv)->intr = nv40_graph_intr;
	326	nv_engine(priv)->cclass = &nv40_graph_cclass;
	327	if (nv44_graph_class(priv))
	328	nv_engine(priv)->sclass = nv44_graph_sclass;
	329	else
	330	nv_engine(priv)->sclass = nv40_graph_sclass;
	331	nv_engine(priv)->tile_prog = nv40_graph_tile_prog;
	332	return 0;
	333	}
	334
	335	static int
	336	nv40_graph_init(struct nouveau_object *object)
	337	{
	338	struct nouveau_engine *engine = nv_engine(object);
	339	struct nouveau_fb *pfb = nouveau_fb(object);
	340	struct nv40_graph_priv priv = (void )engine;
	341	int ret, i, j;
	342	u32 vramsz;
	343
	344	ret = nouveau_graph_init(&priv->base);
	345	if (ret)
	346	return ret;
6ee73861	347
d58086de	348	/* generate and upload context program */
1f150b3e MS	349	ret = nv40_grctx_init(nv_device(priv), &priv->size);
	350	if (ret)
	351	return ret;
6ee73861 BS	352
6ee73861 BS	353	/* No context present currently */
ebb945a9	354	nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
6ee73861	355
ebb945a9 BS	356	nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
ebb945a9 BS	357	nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	358
ebb945a9 BS	359	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	360	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	361	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	362	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	363	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000);
	364	nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
6ee73861	365
ebb945a9 BS	366	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
ebb945a9 BS	367	nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
6ee73861	368
ebb945a9	369	j = nv_rd32(priv, 0x1540) & 0xff;
6ee73861 BS	370	if (j) {
	371	for (i = 0; !(j & 1); j >>= 1, i++)
	372	;
ebb945a9	373	nv_wr32(priv, 0x405000, i);
6ee73861 BS	374	}
6ee73861 BS	375
ebb945a9 BS	376	if (nv_device(priv)->chipset == 0x40) {
	377	nv_wr32(priv, 0x4009b0, 0x83280fff);
	378	nv_wr32(priv, 0x4009b4, 0x000000a0);
6ee73861	379	} else {
ebb945a9 BS	380	nv_wr32(priv, 0x400820, 0x83280eff);
ebb945a9 BS	381	nv_wr32(priv, 0x400824, 0x000000a0);
6ee73861 BS	382	}
6ee73861 BS	383
ebb945a9	384	switch (nv_device(priv)->chipset) {
6ee73861 BS	385	case 0x40:
6ee73861 BS	386	case 0x45:
ebb945a9 BS	387	nv_wr32(priv, 0x4009b8, 0x0078e366);
ebb945a9 BS	388	nv_wr32(priv, 0x4009bc, 0x0000014c);
6ee73861 BS	389	break;
	390	case 0x41:
	391	case 0x42: /* pciid also 0x00Cx */
	392	/* case 0x0120: XXX (pciid) */
ebb945a9 BS	393	nv_wr32(priv, 0x400828, 0x007596ff);
ebb945a9 BS	394	nv_wr32(priv, 0x40082c, 0x00000108);
6ee73861 BS	395	break;
6ee73861 BS	396	case 0x43:
ebb945a9 BS	397	nv_wr32(priv, 0x400828, 0x0072cb77);
ebb945a9 BS	398	nv_wr32(priv, 0x40082c, 0x00000108);
6ee73861 BS	399	break;
	400	case 0x44:
	401	case 0x46: /* G72 */
	402	case 0x4a:
	403	case 0x4c: /* G7x-based C51 */
	404	case 0x4e:
ebb945a9 BS	405	nv_wr32(priv, 0x400860, 0);
ebb945a9 BS	406	nv_wr32(priv, 0x400864, 0);
6ee73861 BS	407	break;
	408	case 0x47: /* G70 */
	409	case 0x49: /* G71 */
	410	case 0x4b: /* G73 */
ebb945a9 BS	411	nv_wr32(priv, 0x400828, 0x07830610);
ebb945a9 BS	412	nv_wr32(priv, 0x40082c, 0x0000016A);
6ee73861 BS	413	break;
	414	default:
	415	break;
	416	}
	417
ebb945a9 BS	418	nv_wr32(priv, 0x400b38, 0x2ffff800);
ebb945a9 BS	419	nv_wr32(priv, 0x400b3c, 0x00006000);
6ee73861	420
2295e17a	421	/* Tiling related stuff. */
ebb945a9	422	switch (nv_device(priv)->chipset) {
2295e17a FJ	423	case 0x44:
2295e17a FJ	424	case 0x4a:
ebb945a9 BS	425	nv_wr32(priv, 0x400bc4, 0x1003d888);
ebb945a9 BS	426	nv_wr32(priv, 0x400bbc, 0xb7a7b500);
2295e17a FJ	427	break;
2295e17a FJ	428	case 0x46:
ebb945a9 BS	429	nv_wr32(priv, 0x400bc4, 0x0000e024);
ebb945a9 BS	430	nv_wr32(priv, 0x400bbc, 0xb7a7b520);
2295e17a FJ	431	break;
	432	case 0x4c:
	433	case 0x4e:
	434	case 0x67:
ebb945a9 BS	435	nv_wr32(priv, 0x400bc4, 0x1003d888);
ebb945a9 BS	436	nv_wr32(priv, 0x400bbc, 0xb7a7b540);
2295e17a FJ	437	break;
	438	default:
	439	break;
	440	}
	441
0d87c100	442	/* Turn all the tiling regions off. */
ebb945a9 BS	443	for (i = 0; i < pfb->tile.regions; i++)
ebb945a9 BS	444	engine->tile_prog(engine, i);
6ee73861 BS	445
6ee73861 BS	446	/* begin RAM config */
ebb945a9 BS	447	vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
ebb945a9 BS	448	switch (nv_device(priv)->chipset) {
6ee73861	449	case 0x40:
ebb945a9 BS	450	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	451	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	452	nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200));
	453	nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204));
	454	nv_wr32(priv, 0x400820, 0);
	455	nv_wr32(priv, 0x400824, 0);
	456	nv_wr32(priv, 0x400864, vramsz);
	457	nv_wr32(priv, 0x400868, vramsz);
6ee73861 BS	458	break;
6ee73861 BS	459	default:
ebb945a9	460	switch (nv_device(priv)->chipset) {
1dc32671 BS	461	case 0x41:
	462	case 0x42:
	463	case 0x43:
	464	case 0x45:
	465	case 0x4e:
	466	case 0x44:
	467	case 0x4a:
ebb945a9 BS	468	nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200));
ebb945a9 BS	469	nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204));
6ee73861	470	break;
1dc32671	471	default:
ebb945a9 BS	472	nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200));
ebb945a9 BS	473	nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204));
1dc32671	474	break;
6ee73861	475	}
ebb945a9 BS	476	nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200));
	477	nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204));
	478	nv_wr32(priv, 0x400840, 0);
	479	nv_wr32(priv, 0x400844, 0);
	480	nv_wr32(priv, 0x4008A0, vramsz);
	481	nv_wr32(priv, 0x4008A4, vramsz);
6ee73861 BS	482	break;
	483	}
	484
	485	return 0;
	486	}
	487
ebb945a9 BS	488	struct nouveau_oclass
	489	nv40_graph_oclass = {
	490	.handle = NV_ENGINE(GR, 0x40),
	491	.ofuncs = &(struct nouveau_ofuncs) {
	492	.ctor = nv40_graph_ctor,
	493	.dtor = _nouveau_graph_dtor,
	494	.init = nv40_graph_init,
	495	.fini = _nouveau_graph_fini,
	496	},
	497	};