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drm/nouveau/bios: have strap reads show on devinit spam debug level
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / core / subdev / bios / init.c
CommitLineData
cb75d97e
BS		 1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
cb75d97e
BS		 5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
1ed73166 7#include <subdev/bios/conn.h>
cb75d97e
BS		 8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
1ed73166 10#include <subdev/bios/gpio.h>
cb75d97e 11#include <subdev/bios/init.h>
0a0dc8f5 12#include <subdev/bios/ramcfg.h>
cb75d97e 13#include <subdev/devinit.h>
cb75d97e
BS		 14#include <subdev/i2c.h>
15#include <subdev/vga.h>
16#include <subdev/gpio.h>
17
18#define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21} while(0)
22#define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
25} while(0)
26#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29
30/******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
33
34static inline bool
35init_exec(struct nvbios_init *init)
36{
37 return (init->execute == 1) || ((init->execute & 5) == 5);
38}
39
40static inline void
41init_exec_set(struct nvbios_init *init, bool exec)
42{
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
45}
46
47static inline void
48init_exec_inv(struct nvbios_init *init)
49{
50 init->execute ^= 0x02;
51}
52
53static inline void
54init_exec_force(struct nvbios_init *init, bool exec)
55{
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
58}
59
60/******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
63
64static inline int
65init_or(struct nvbios_init *init)
66{
28ec70f7
BS		 67 if (init_exec(init)) {
68 if (init->outp)
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
71 }
cb75d97e
BS		 72 return 0;
73}
74
75static inline int
76init_link(struct nvbios_init *init)
77{
28ec70f7
BS		 78 if (init_exec(init)) {
79 if (init->outp)
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
82 }
cb75d97e
BS		 83 return 0;
84}
85
86static inline int
87init_crtc(struct nvbios_init *init)
88{
28ec70f7
BS		 89 if (init_exec(init)) {
90 if (init->crtc >= 0)
91 return init->crtc;
92 error("script needs crtc\n");
93 }
cb75d97e
BS		 94 return 0;
95}
96
97static u8
98init_conn(struct nvbios_init *init)
99{
100 struct nouveau_bios *bios = init->bios;
28ec70f7
BS		 101 u8 ver, len;
102 u16 conn;
cb75d97e 103
28ec70f7
BS		 104 if (init_exec(init)) {
105 if (init->outp) {
106 conn = init->outp->connector;
107 conn = dcb_conn(bios, conn, &ver, &len);
108 if (conn)
109 return nv_ro08(bios, conn);
110 }
111
112 error("script needs connector type\n");
cb75d97e
BS		 113 }
114
28ec70f7 115 return 0xff;
cb75d97e
BS		 116}
117
118static inline u32
119init_nvreg(struct nvbios_init *init, u32 reg)
120{
121 /* C51 (at least) sometimes has the lower bits set which the VBIOS
122 * interprets to mean that access needs to go through certain IO
123 * ports instead. The NVIDIA binary driver has been seen to access
124 * these through the NV register address, so lets assume we can
125 * do the same
126 */
127 reg &= ~0x00000003;
128
129 /* GF8+ display scripts need register addresses mangled a bit to
130 * select a specific CRTC/OR
131 */
132 if (nv_device(init->bios)->card_type >= NV_50) {
133 if (reg & 0x80000000) {
134 reg += init_crtc(init) * 0x800;
135 reg &= ~0x80000000;
136 }
137
138 if (reg & 0x40000000) {
139 reg += init_or(init) * 0x800;
140 reg &= ~0x40000000;
141 if (reg & 0x20000000) {
142 reg += init_link(init) * 0x80;
143 reg &= ~0x20000000;
144 }
145 }
146 }
147
148 if (reg & ~0x00fffffc)
149 warn("unknown bits in register 0x%08x\n", reg);
150 return reg;
151}
152
153static u32
154init_rd32(struct nvbios_init *init, u32 reg)
155{
156 reg = init_nvreg(init, reg);
157 if (init_exec(init))
158 return nv_rd32(init->subdev, reg);
159 return 0x00000000;
160}
161
162static void
163init_wr32(struct nvbios_init *init, u32 reg, u32 val)
164{
165 reg = init_nvreg(init, reg);
166 if (init_exec(init))
167 nv_wr32(init->subdev, reg, val);
168}
169
170static u32
171init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
172{
173 reg = init_nvreg(init, reg);
174 if (init_exec(init)) {
175 u32 tmp = nv_rd32(init->subdev, reg);
176 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
177 return tmp;
178 }
179 return 0x00000000;
180}
181
182static u8
183init_rdport(struct nvbios_init *init, u16 port)
184{
185 if (init_exec(init))
186 return nv_rdport(init->subdev, init->crtc, port);
187 return 0x00;
188}
189
190static void
191init_wrport(struct nvbios_init *init, u16 port, u8 value)
192{
193 if (init_exec(init))
194 nv_wrport(init->subdev, init->crtc, port, value);
195}
196
197static u8
198init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
199{
200 struct nouveau_subdev *subdev = init->subdev;
201 if (init_exec(init)) {
202 int head = init->crtc < 0 ? 0 : init->crtc;
203 return nv_rdvgai(subdev, head, port, index);
204 }
205 return 0x00;
206}
207
208static void
209init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
210{
211 /* force head 0 for updates to cr44, it only exists on first head */
212 if (nv_device(init->subdev)->card_type < NV_50) {
213 if (port == 0x03d4 && index == 0x44)
214 init->crtc = 0;
215 }
216
217 if (init_exec(init)) {
218 int head = init->crtc < 0 ? 0 : init->crtc;
219 nv_wrvgai(init->subdev, head, port, index, value);
220 }
221
222 /* select head 1 if cr44 write selected it */
223 if (nv_device(init->subdev)->card_type < NV_50) {
224 if (port == 0x03d4 && index == 0x44 && value == 3)
225 init->crtc = 1;
226 }
227}
228
229static struct nouveau_i2c_port *
230init_i2c(struct nvbios_init *init, int index)
231{
232 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
233
234 if (index == 0xff) {
235 index = NV_I2C_DEFAULT(0);
236 if (init->outp && init->outp->i2c_upper_default)
237 index = NV_I2C_DEFAULT(1);
238 } else
239 if (index < 0) {
240 if (!init->outp) {
28ec70f7
BS		 241 if (init_exec(init))
242 error("script needs output for i2c\n");
cb75d97e
BS		 243 return NULL;
244 }
245
476e84e1
BS		 246 if (index == -2 && init->outp->location) {
247 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
248 return i2c->find_type(i2c, index);
249 }
250
cb75d97e
BS		 251 index = init->outp->i2c_index;
252 }
253
254 return i2c->find(i2c, index);
255}
256
257static int
258init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
259{
260 struct nouveau_i2c_port *port = init_i2c(init, index);
261 if (port && init_exec(init))
262 return nv_rdi2cr(port, addr, reg);
263 return -ENODEV;
264}
265
266static int
267init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
268{
269 struct nouveau_i2c_port *port = init_i2c(init, index);
270 if (port && init_exec(init))
271 return nv_wri2cr(port, addr, reg, val);
272 return -ENODEV;
273}
274
275static int
276init_rdauxr(struct nvbios_init *init, u32 addr)
277{
476e84e1 278 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 279 u8 data;
280
281 if (port && init_exec(init)) {
282 int ret = nv_rdaux(port, addr, &data, 1);
283 if (ret)
284 return ret;
285 return data;
286 }
287
288 return -ENODEV;
289}
290
291static int
292init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
293{
476e84e1 294 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 295 if (port && init_exec(init))
296 return nv_wraux(port, addr, &data, 1);
297 return -ENODEV;
298}
299
300static void
301init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
302{
88524bc0
BS		 303 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
304 if (devinit->pll_set && init_exec(init)) {
305 int ret = devinit->pll_set(devinit, id, freq);
cb75d97e
BS		 306 if (ret)
307 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
308 }
309}
310
311/******************************************************************************
312 * parsing of bios structures that are required to execute init tables
313 *****************************************************************************/
314
315static u16
316init_table(struct nouveau_bios *bios, u16 *len)
317{
318 struct bit_entry bit_I;
319
320 if (!bit_entry(bios, 'I', &bit_I)) {
321 *len = bit_I.length;
322 return bit_I.offset;
323 }
324
325 if (bmp_version(bios) >= 0x0510) {
326 *len = 14;
327 return bios->bmp_offset + 75;
328 }
329
330 return 0x0000;
331}
332
333static u16
334init_table_(struct nvbios_init *init, u16 offset, const char *name)
335{
336 struct nouveau_bios *bios = init->bios;
337 u16 len, data = init_table(bios, &len);
338 if (data) {
339 if (len >= offset + 2) {
340 data = nv_ro16(bios, data + offset);
341 if (data)
342 return data;
343
344 warn("%s pointer invalid\n", name);
345 return 0x0000;
346 }
347
348 warn("init data too short for %s pointer", name);
349 return 0x0000;
350 }
351
352 warn("init data not found\n");
353 return 0x0000;
354}
355
356#define init_script_table(b) init_table_((b), 0x00, "script table")
357#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
358#define init_macro_table(b) init_table_((b), 0x04, "macro table")
359#define init_condition_table(b) init_table_((b), 0x06, "condition table")
360#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
361#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
362#define init_function_table(b) init_table_((b), 0x0c, "function table")
363#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
364
365static u16
366init_script(struct nouveau_bios *bios, int index)
367{
368 struct nvbios_init init = { .bios = bios };
5d2f4767 369 u16 bmp_ver = bmp_version(bios), data;
cb75d97e 370
5d2f4767
IM		 371 if (bmp_ver && bmp_ver < 0x0510) {
372 if (index > 1 || bmp_ver < 0x0100)
cb75d97e
BS		 373 return 0x0000;
374
5d2f4767 375 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
cb75d97e
BS		 376 return nv_ro16(bios, data + (index * 2));
377 }
378
379 data = init_script_table(&init);
380 if (data)
381 return nv_ro16(bios, data + (index * 2));
382
383 return 0x0000;
384}
385
386static u16
387init_unknown_script(struct nouveau_bios *bios)
388{
389 u16 len, data = init_table(bios, &len);
390 if (data && len >= 16)
391 return nv_ro16(bios, data + 14);
392 return 0x0000;
393}
394
cb75d97e
BS		 395static u8
396init_ram_restrict_group_count(struct nvbios_init *init)
397{
0a0dc8f5 398 return nvbios_ramcfg_count(init->bios);
cb75d97e
BS		 399}
400
5ddf4d4a 401static u8
0a0dc8f5 402init_ram_restrict(struct nvbios_init *init)
5ddf4d4a
BS		 403{
404 /* This appears to be the behaviour of the VBIOS parser, and *is*
405 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
406 * avoid fucking up the memory controller (somehow) by reading it
407 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
408 *
409 * Preserving the non-caching behaviour on earlier chipsets just
410 * in case *not* re-reading the strap causes similar breakage.
411 */
412 if (!init->ramcfg || init->bios->version.major < 0x70)
0a8649f1 413 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
0a0dc8f5 414 return (init->ramcfg & 0x7fffffff);
cb75d97e
BS		 415}
416
417static u8
418init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
419{
420 struct nouveau_bios *bios = init->bios;
421 u16 table = init_xlat_table(init);
422 if (table) {
423 u16 data = nv_ro16(bios, table + (index * 2));
424 if (data)
425 return nv_ro08(bios, data + offset);
426 warn("xlat table pointer %d invalid\n", index);
427 }
428 return 0x00;
429}
430
431/******************************************************************************
432 * utility functions used by various init opcode handlers
433 *****************************************************************************/
434
435static bool
436init_condition_met(struct nvbios_init *init, u8 cond)
437{
438 struct nouveau_bios *bios = init->bios;
439 u16 table = init_condition_table(init);
440 if (table) {
441 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
442 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
443 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
444 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
445 cond, reg, msk, val);
446 return (init_rd32(init, reg) & msk) == val;
447 }
448 return false;
449}
450
451static bool
452init_io_condition_met(struct nvbios_init *init, u8 cond)
453{
454 struct nouveau_bios *bios = init->bios;
455 u16 table = init_io_condition_table(init);
456 if (table) {
457 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
458 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
459 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
460 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
461 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
462 cond, port, index, mask, value);
463 return (init_rdvgai(init, port, index) & mask) == value;
464 }
465 return false;
466}
467
468static bool
469init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
470{
471 struct nouveau_bios *bios = init->bios;
472 u16 table = init_io_flag_condition_table(init);
473 if (table) {
474 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
475 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
476 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
477 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
478 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
479 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
480 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
481 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
482 return (nv_ro08(bios, data + ioval) & dmask) == value;
483 }
484 return false;
485}
486
487static inline u32
488init_shift(u32 data, u8 shift)
489{
490 if (shift < 0x80)
491 return data >> shift;
492 return data << (0x100 - shift);
493}
494
495static u32
496init_tmds_reg(struct nvbios_init *init, u8 tmds)
497{
498 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
499 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
500 * CR58 for CR57 = 0 to index a table of offsets to the basic
501 * 0x6808b0 address.
502 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
503 * CR58 for CR57 = 0 to index a table of offsets to the basic
504 * 0x6808b0 address, and then flip the offset by 8.
505 */
506
507 const int pramdac_offset[13] = {
508 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
509 const u32 pramdac_table[4] = {
510 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
511
512 if (tmds >= 0x80) {
513 if (init->outp) {
514 u32 dacoffset = pramdac_offset[init->outp->or];
515 if (tmds == 0x81)
516 dacoffset ^= 8;
517 return 0x6808b0 + dacoffset;
518 }
519
28ec70f7
BS		 520 if (init_exec(init))
521 error("tmds opcodes need dcb\n");
cb75d97e
BS		 522 } else {
523 if (tmds < ARRAY_SIZE(pramdac_table))
524 return pramdac_table[tmds];
525
526 error("tmds selector 0x%02x unknown\n", tmds);
527 }
528
529 return 0;
530}
531
532/******************************************************************************
533 * init opcode handlers
534 *****************************************************************************/
535
536/**
537 * init_reserved - stub for various unknown/unused single-byte opcodes
538 *
539 */
540static void
541init_reserved(struct nvbios_init *init)
542{
543 u8 opcode = nv_ro08(init->bios, init->offset);
5495e39f
BS		 544 u8 length, i;
545
546 switch (opcode) {
547 case 0xaa:
548 length = 4;
549 break;
550 default:
551 length = 1;
552 break;
553 }
554
555 trace("RESERVED 0x%02x\t", opcode);
556 for (i = 1; i < length; i++)
557 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
558 cont("\n");
559 init->offset += length;
cb75d97e
BS		 560}
561
562/**
563 * INIT_DONE - opcode 0x71
564 *
565 */
566static void
567init_done(struct nvbios_init *init)
568{
569 trace("DONE\n");
570 init->offset = 0x0000;
571}
572
573/**
574 * INIT_IO_RESTRICT_PROG - opcode 0x32
575 *
576 */
577static void
578init_io_restrict_prog(struct nvbios_init *init)
579{
580 struct nouveau_bios *bios = init->bios;
581 u16 port = nv_ro16(bios, init->offset + 1);
582 u8 index = nv_ro08(bios, init->offset + 3);
583 u8 mask = nv_ro08(bios, init->offset + 4);
584 u8 shift = nv_ro08(bios, init->offset + 5);
585 u8 count = nv_ro08(bios, init->offset + 6);
586 u32 reg = nv_ro32(bios, init->offset + 7);
587 u8 conf, i;
588
589 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
590 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
591 reg, port, index, mask, shift);
592 init->offset += 11;
593
594 conf = (init_rdvgai(init, port, index) & mask) >> shift;
595 for (i = 0; i < count; i++) {
596 u32 data = nv_ro32(bios, init->offset);
597
598 if (i == conf) {
599 trace("\t0x%08x *\n", data);
600 init_wr32(init, reg, data);
601 } else {
602 trace("\t0x%08x\n", data);
603 }
604
605 init->offset += 4;
606 }
607 trace("}]\n");
608}
609
610/**
611 * INIT_REPEAT - opcode 0x33
612 *
613 */
614static void
615init_repeat(struct nvbios_init *init)
616{
617 struct nouveau_bios *bios = init->bios;
618 u8 count = nv_ro08(bios, init->offset + 1);
619 u16 repeat = init->repeat;
620
621 trace("REPEAT\t0x%02x\n", count);
622 init->offset += 2;
623
624 init->repeat = init->offset;
625 init->repend = init->offset;
626 while (count--) {
627 init->offset = init->repeat;
628 nvbios_exec(init);
629 if (count)
630 trace("REPEAT\t0x%02x\n", count);
631 }
632 init->offset = init->repend;
633 init->repeat = repeat;
634}
635
636/**
637 * INIT_IO_RESTRICT_PLL - opcode 0x34
638 *
639 */
640static void
641init_io_restrict_pll(struct nvbios_init *init)
642{
643 struct nouveau_bios *bios = init->bios;
644 u16 port = nv_ro16(bios, init->offset + 1);
645 u8 index = nv_ro08(bios, init->offset + 3);
646 u8 mask = nv_ro08(bios, init->offset + 4);
647 u8 shift = nv_ro08(bios, init->offset + 5);
648 s8 iofc = nv_ro08(bios, init->offset + 6);
649 u8 count = nv_ro08(bios, init->offset + 7);
650 u32 reg = nv_ro32(bios, init->offset + 8);
651 u8 conf, i;
652
653 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
654 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
655 reg, port, index, mask, shift, iofc);
656 init->offset += 12;
657
658 conf = (init_rdvgai(init, port, index) & mask) >> shift;
659 for (i = 0; i < count; i++) {
660 u32 freq = nv_ro16(bios, init->offset) * 10;
661
662 if (i == conf) {
663 trace("\t%dkHz *\n", freq);
664 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
665 freq *= 2;
666 init_prog_pll(init, reg, freq);
667 } else {
668 trace("\t%dkHz\n", freq);
669 }
670
671 init->offset += 2;
672 }
673 trace("}]\n");
674}
675
676/**
677 * INIT_END_REPEAT - opcode 0x36
678 *
679 */
680static void
681init_end_repeat(struct nvbios_init *init)
682{
683 trace("END_REPEAT\n");
684 init->offset += 1;
685
686 if (init->repeat) {
687 init->repend = init->offset;
688 init->offset = 0;
689 }
690}
691
692/**
693 * INIT_COPY - opcode 0x37
694 *
695 */
696static void
697init_copy(struct nvbios_init *init)
698{
699 struct nouveau_bios *bios = init->bios;
700 u32 reg = nv_ro32(bios, init->offset + 1);
701 u8 shift = nv_ro08(bios, init->offset + 5);
702 u8 smask = nv_ro08(bios, init->offset + 6);
703 u16 port = nv_ro16(bios, init->offset + 7);
704 u8 index = nv_ro08(bios, init->offset + 9);
705 u8 mask = nv_ro08(bios, init->offset + 10);
706 u8 data;
707
708 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
709 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
710 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
711 (shift & 0x80) ? (0x100 - shift) : shift, smask);
712 init->offset += 11;
713
714 data = init_rdvgai(init, port, index) & mask;
715 data |= init_shift(init_rd32(init, reg), shift) & smask;
716 init_wrvgai(init, port, index, data);
717}
718
719/**
720 * INIT_NOT - opcode 0x38
721 *
722 */
723static void
724init_not(struct nvbios_init *init)
725{
726 trace("NOT\n");
727 init->offset += 1;
728 init_exec_inv(init);
729}
730
731/**
732 * INIT_IO_FLAG_CONDITION - opcode 0x39
733 *
734 */
735static void
736init_io_flag_condition(struct nvbios_init *init)
737{
738 struct nouveau_bios *bios = init->bios;
739 u8 cond = nv_ro08(bios, init->offset + 1);
740
741 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
742 init->offset += 2;
743
744 if (!init_io_flag_condition_met(init, cond))
745 init_exec_set(init, false);
746}
747
748/**
749 * INIT_DP_CONDITION - opcode 0x3a
750 *
751 */
752static void
753init_dp_condition(struct nvbios_init *init)
754{
755 struct nouveau_bios *bios = init->bios;
65c78660 756 struct nvbios_dpout info;
cb75d97e
BS		 757 u8 cond = nv_ro08(bios, init->offset + 1);
758 u8 unkn = nv_ro08(bios, init->offset + 2);
65c78660 759 u8 ver, hdr, cnt, len;
cb75d97e
BS		 760 u16 data;
761
762 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
763 init->offset += 3;
764
765 switch (cond) {
766 case 0:
767 if (init_conn(init) != DCB_CONNECTOR_eDP)
768 init_exec_set(init, false);
769 break;
770 case 1:
771 case 2:
772 if ( init->outp &&
65c78660
BS		 773 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
774 (init->outp->or << 0) |
775 (init->outp->sorconf.link << 6),
776 &ver, &hdr, &cnt, &len, &info)))
777 {
778 if (!(info.flags & cond))
cb75d97e
BS		 779 init_exec_set(init, false);
780 break;
781 }
782
28ec70f7
BS		 783 if (init_exec(init))
784 warn("script needs dp output table data\n");
cb75d97e
BS		 785 break;
786 case 5:
787 if (!(init_rdauxr(init, 0x0d) & 1))
788 init_exec_set(init, false);
789 break;
790 default:
791 warn("unknown dp condition 0x%02x\n", cond);
792 break;
793 }
794}
795
796/**
797 * INIT_IO_MASK_OR - opcode 0x3b
798 *
799 */
800static void
801init_io_mask_or(struct nvbios_init *init)
802{
803 struct nouveau_bios *bios = init->bios;
804 u8 index = nv_ro08(bios, init->offset + 1);
805 u8 or = init_or(init);
806 u8 data;
807
b9a3140c 808 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
cb75d97e
BS		 809 init->offset += 2;
810
811 data = init_rdvgai(init, 0x03d4, index);
812 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
813}
814
815/**
816 * INIT_IO_OR - opcode 0x3c
817 *
818 */
819static void
820init_io_or(struct nvbios_init *init)
821{
822 struct nouveau_bios *bios = init->bios;
823 u8 index = nv_ro08(bios, init->offset + 1);
824 u8 or = init_or(init);
825 u8 data;
826
b9a3140c 827 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
cb75d97e
BS		 828 init->offset += 2;
829
830 data = init_rdvgai(init, 0x03d4, index);
831 init_wrvgai(init, 0x03d4, index, data | (1 << or));
832}
833
834/**
835 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
836 *
837 */
838static void
839init_idx_addr_latched(struct nvbios_init *init)
840{
841 struct nouveau_bios *bios = init->bios;
842 u32 creg = nv_ro32(bios, init->offset + 1);
843 u32 dreg = nv_ro32(bios, init->offset + 5);
844 u32 mask = nv_ro32(bios, init->offset + 9);
845 u32 data = nv_ro32(bios, init->offset + 13);
846 u8 count = nv_ro08(bios, init->offset + 17);
847
8db3a740
IM		 848 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
849 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
cb75d97e
BS		 850 init->offset += 18;
851
852 while (count--) {
853 u8 iaddr = nv_ro08(bios, init->offset + 0);
854 u8 idata = nv_ro08(bios, init->offset + 1);
855
856 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
857 init->offset += 2;
858
859 init_wr32(init, dreg, idata);
f6853faa 860 init_mask(init, creg, ~mask, data | iaddr);
cb75d97e
BS		 861 }
862}
863
864/**
865 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
866 *
867 */
868static void
869init_io_restrict_pll2(struct nvbios_init *init)
870{
871 struct nouveau_bios *bios = init->bios;
872 u16 port = nv_ro16(bios, init->offset + 1);
873 u8 index = nv_ro08(bios, init->offset + 3);
874 u8 mask = nv_ro08(bios, init->offset + 4);
875 u8 shift = nv_ro08(bios, init->offset + 5);
876 u8 count = nv_ro08(bios, init->offset + 6);
877 u32 reg = nv_ro32(bios, init->offset + 7);
878 u8 conf, i;
879
880 trace("IO_RESTRICT_PLL2\t"
881 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
882 reg, port, index, mask, shift);
883 init->offset += 11;
884
885 conf = (init_rdvgai(init, port, index) & mask) >> shift;
886 for (i = 0; i < count; i++) {
887 u32 freq = nv_ro32(bios, init->offset);
888 if (i == conf) {
889 trace("\t%dkHz *\n", freq);
890 init_prog_pll(init, reg, freq);
891 } else {
892 trace("\t%dkHz\n", freq);
893 }
894 init->offset += 4;
895 }
896 trace("}]\n");
897}
898
899/**
900 * INIT_PLL2 - opcode 0x4b
901 *
902 */
903static void
904init_pll2(struct nvbios_init *init)
905{
906 struct nouveau_bios *bios = init->bios;
907 u32 reg = nv_ro32(bios, init->offset + 1);
908 u32 freq = nv_ro32(bios, init->offset + 5);
909
910 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
911 init->offset += 9;
912
913 init_prog_pll(init, reg, freq);
914}
915
916/**
917 * INIT_I2C_BYTE - opcode 0x4c
918 *
919 */
920static void
921init_i2c_byte(struct nvbios_init *init)
922{
923 struct nouveau_bios *bios = init->bios;
924 u8 index = nv_ro08(bios, init->offset + 1);
925 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
926 u8 count = nv_ro08(bios, init->offset + 3);
927
928 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
929 init->offset += 4;
930
931 while (count--) {
932 u8 reg = nv_ro08(bios, init->offset + 0);
933 u8 mask = nv_ro08(bios, init->offset + 1);
934 u8 data = nv_ro08(bios, init->offset + 2);
935 int val;
936
937 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
938 init->offset += 3;
939
940 val = init_rdi2cr(init, index, addr, reg);
941 if (val < 0)
942 continue;
943 init_wri2cr(init, index, addr, reg, (val & mask) | data);
944 }
945}
946
947/**
948 * INIT_ZM_I2C_BYTE - opcode 0x4d
949 *
950 */
951static void
952init_zm_i2c_byte(struct nvbios_init *init)
953{
954 struct nouveau_bios *bios = init->bios;
955 u8 index = nv_ro08(bios, init->offset + 1);
956 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
957 u8 count = nv_ro08(bios, init->offset + 3);
958
959 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
960 init->offset += 4;
961
962 while (count--) {
963 u8 reg = nv_ro08(bios, init->offset + 0);
964 u8 data = nv_ro08(bios, init->offset + 1);
965
966 trace("\t[0x%02x] = 0x%02x\n", reg, data);
967 init->offset += 2;
968
969 init_wri2cr(init, index, addr, reg, data);
970 }
971
972}
973
974/**
975 * INIT_ZM_I2C - opcode 0x4e
976 *
977 */
978static void
979init_zm_i2c(struct nvbios_init *init)
980{
981 struct nouveau_bios *bios = init->bios;
982 u8 index = nv_ro08(bios, init->offset + 1);
983 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
984 u8 count = nv_ro08(bios, init->offset + 3);
985 u8 data[256], i;
986
987 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
988 init->offset += 4;
989
990 for (i = 0; i < count; i++) {
991 data[i] = nv_ro08(bios, init->offset);
992 trace("\t0x%02x\n", data[i]);
993 init->offset++;
994 }
995
996 if (init_exec(init)) {
997 struct nouveau_i2c_port *port = init_i2c(init, index);
998 struct i2c_msg msg = {
999 .addr = addr, .flags = 0, .len = count, .buf = data,
1000 };
1001 int ret;
1002
1003 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1004 warn("i2c wr failed, %d\n", ret);
1005 }
1006}
1007
1008/**
1009 * INIT_TMDS - opcode 0x4f
1010 *
1011 */
1012static void
1013init_tmds(struct nvbios_init *init)
1014{
1015 struct nouveau_bios *bios = init->bios;
1016 u8 tmds = nv_ro08(bios, init->offset + 1);
1017 u8 addr = nv_ro08(bios, init->offset + 2);
1018 u8 mask = nv_ro08(bios, init->offset + 3);
1019 u8 data = nv_ro08(bios, init->offset + 4);
1020 u32 reg = init_tmds_reg(init, tmds);
1021
1022 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1023 tmds, addr, mask, data);
1024 init->offset += 5;
1025
1026 if (reg == 0)
1027 return;
1028
1029 init_wr32(init, reg + 0, addr | 0x00010000);
1030 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1031 init_wr32(init, reg + 0, addr);
1032}
1033
1034/**
1035 * INIT_ZM_TMDS_GROUP - opcode 0x50
1036 *
1037 */
1038static void
1039init_zm_tmds_group(struct nvbios_init *init)
1040{
1041 struct nouveau_bios *bios = init->bios;
1042 u8 tmds = nv_ro08(bios, init->offset + 1);
1043 u8 count = nv_ro08(bios, init->offset + 2);
1044 u32 reg = init_tmds_reg(init, tmds);
1045
1046 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1047 init->offset += 3;
1048
1049 while (count--) {
1050 u8 addr = nv_ro08(bios, init->offset + 0);
1051 u8 data = nv_ro08(bios, init->offset + 1);
1052
1053 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1054 init->offset += 2;
1055
1056 init_wr32(init, reg + 4, data);
1057 init_wr32(init, reg + 0, addr);
1058 }
1059}
1060
1061/**
1062 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1063 *
1064 */
1065static void
1066init_cr_idx_adr_latch(struct nvbios_init *init)
1067{
1068 struct nouveau_bios *bios = init->bios;
1069 u8 addr0 = nv_ro08(bios, init->offset + 1);
1070 u8 addr1 = nv_ro08(bios, init->offset + 2);
1071 u8 base = nv_ro08(bios, init->offset + 3);
1072 u8 count = nv_ro08(bios, init->offset + 4);
1073 u8 save0;
1074
1075 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1076 init->offset += 5;
1077
1078 save0 = init_rdvgai(init, 0x03d4, addr0);
1079 while (count--) {
1080 u8 data = nv_ro08(bios, init->offset);
1081
1082 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1083 init->offset += 1;
1084
1085 init_wrvgai(init, 0x03d4, addr0, base++);
1086 init_wrvgai(init, 0x03d4, addr1, data);
1087 }
1088 init_wrvgai(init, 0x03d4, addr0, save0);
1089}
1090
1091/**
1092 * INIT_CR - opcode 0x52
1093 *
1094 */
1095static void
1096init_cr(struct nvbios_init *init)
1097{
1098 struct nouveau_bios *bios = init->bios;
1099 u8 addr = nv_ro08(bios, init->offset + 1);
1100 u8 mask = nv_ro08(bios, init->offset + 2);
1101 u8 data = nv_ro08(bios, init->offset + 3);
1102 u8 val;
1103
1104 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1105 init->offset += 4;
1106
1107 val = init_rdvgai(init, 0x03d4, addr) & mask;
1108 init_wrvgai(init, 0x03d4, addr, val | data);
1109}
1110
1111/**
1112 * INIT_ZM_CR - opcode 0x53
1113 *
1114 */
1115static void
1116init_zm_cr(struct nvbios_init *init)
1117{
1118 struct nouveau_bios *bios = init->bios;
1119 u8 addr = nv_ro08(bios, init->offset + 1);
1120 u8 data = nv_ro08(bios, init->offset + 2);
1121
1122 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1123 init->offset += 3;
1124
1125 init_wrvgai(init, 0x03d4, addr, data);
1126}
1127
1128/**
1129 * INIT_ZM_CR_GROUP - opcode 0x54
1130 *
1131 */
1132static void
1133init_zm_cr_group(struct nvbios_init *init)
1134{
1135 struct nouveau_bios *bios = init->bios;
1136 u8 count = nv_ro08(bios, init->offset + 1);
1137
1138 trace("ZM_CR_GROUP\n");
1139 init->offset += 2;
1140
1141 while (count--) {
1142 u8 addr = nv_ro08(bios, init->offset + 0);
1143 u8 data = nv_ro08(bios, init->offset + 1);
1144
1145 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1146 init->offset += 2;
1147
1148 init_wrvgai(init, 0x03d4, addr, data);
1149 }
1150}
1151
1152/**
1153 * INIT_CONDITION_TIME - opcode 0x56
1154 *
1155 */
1156static void
1157init_condition_time(struct nvbios_init *init)
1158{
1159 struct nouveau_bios *bios = init->bios;
1160 u8 cond = nv_ro08(bios, init->offset + 1);
1161 u8 retry = nv_ro08(bios, init->offset + 2);
1162 u8 wait = min((u16)retry * 50, 100);
1163
1164 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1165 init->offset += 3;
1166
1167 if (!init_exec(init))
1168 return;
1169
1170 while (wait--) {
1171 if (init_condition_met(init, cond))
1172 return;
1173 mdelay(20);
1174 }
1175
1176 init_exec_set(init, false);
1177}
1178
1179/**
1180 * INIT_LTIME - opcode 0x57
1181 *
1182 */
1183static void
1184init_ltime(struct nvbios_init *init)
1185{
1186 struct nouveau_bios *bios = init->bios;
1187 u16 msec = nv_ro16(bios, init->offset + 1);
1188
1189 trace("LTIME\t0x%04x\n", msec);
1190 init->offset += 3;
1191
1192 if (init_exec(init))
1193 mdelay(msec);
1194}
1195
1196/**
1197 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1198 *
1199 */
1200static void
1201init_zm_reg_sequence(struct nvbios_init *init)
1202{
1203 struct nouveau_bios *bios = init->bios;
1204 u32 base = nv_ro32(bios, init->offset + 1);
1205 u8 count = nv_ro08(bios, init->offset + 5);
1206
1207 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1208 init->offset += 6;
1209
1210 while (count--) {
1211 u32 data = nv_ro32(bios, init->offset);
1212
1213 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1214 init->offset += 4;
1215
1216 init_wr32(init, base, data);
1217 base += 4;
1218 }
1219}
1220
1221/**
1222 * INIT_SUB_DIRECT - opcode 0x5b
1223 *
1224 */
1225static void
1226init_sub_direct(struct nvbios_init *init)
1227{
1228 struct nouveau_bios *bios = init->bios;
1229 u16 addr = nv_ro16(bios, init->offset + 1);
1230 u16 save;
1231
1232 trace("SUB_DIRECT\t0x%04x\n", addr);
1233
1234 if (init_exec(init)) {
1235 save = init->offset;
1236 init->offset = addr;
1237 if (nvbios_exec(init)) {
1238 error("error parsing sub-table\n");
1239 return;
1240 }
1241 init->offset = save;
1242 }
1243
1244 init->offset += 3;
1245}
1246
1247/**
1248 * INIT_JUMP - opcode 0x5c
1249 *
1250 */
1251static void
1252init_jump(struct nvbios_init *init)
1253{
1254 struct nouveau_bios *bios = init->bios;
1255 u16 offset = nv_ro16(bios, init->offset + 1);
1256
1257 trace("JUMP\t0x%04x\n", offset);
6d60792e
IM		 1258
1259 if (init_exec(init))
1260 init->offset = offset;
1261 else
1262 init->offset += 3;
cb75d97e
BS		 1263}
1264
1265/**
1266 * INIT_I2C_IF - opcode 0x5e
1267 *
1268 */
1269static void
1270init_i2c_if(struct nvbios_init *init)
1271{
1272 struct nouveau_bios *bios = init->bios;
1273 u8 index = nv_ro08(bios, init->offset + 1);
1274 u8 addr = nv_ro08(bios, init->offset + 2);
1275 u8 reg = nv_ro08(bios, init->offset + 3);
1276 u8 mask = nv_ro08(bios, init->offset + 4);
1277 u8 data = nv_ro08(bios, init->offset + 5);
1278 u8 value;
1279
1280 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1281 index, addr, reg, mask, data);
1282 init->offset += 6;
1283 init_exec_force(init, true);
1284
1285 value = init_rdi2cr(init, index, addr, reg);
1286 if ((value & mask) != data)
1287 init_exec_set(init, false);
1288
1289 init_exec_force(init, false);
1290}
1291
1292/**
1293 * INIT_COPY_NV_REG - opcode 0x5f
1294 *
1295 */
1296static void
1297init_copy_nv_reg(struct nvbios_init *init)
1298{
1299 struct nouveau_bios *bios = init->bios;
1300 u32 sreg = nv_ro32(bios, init->offset + 1);
1301 u8 shift = nv_ro08(bios, init->offset + 5);
1302 u32 smask = nv_ro32(bios, init->offset + 6);
1303 u32 sxor = nv_ro32(bios, init->offset + 10);
1304 u32 dreg = nv_ro32(bios, init->offset + 14);
1305 u32 dmask = nv_ro32(bios, init->offset + 18);
1306 u32 data;
1307
1308 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1309 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1310 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1311 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1312 init->offset += 22;
1313
1314 data = init_shift(init_rd32(init, sreg), shift);
1315 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1316}
1317
1318/**
1319 * INIT_ZM_INDEX_IO - opcode 0x62
1320 *
1321 */
1322static void
1323init_zm_index_io(struct nvbios_init *init)
1324{
1325 struct nouveau_bios *bios = init->bios;
1326 u16 port = nv_ro16(bios, init->offset + 1);
1327 u8 index = nv_ro08(bios, init->offset + 3);
1328 u8 data = nv_ro08(bios, init->offset + 4);
1329
1330 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1331 init->offset += 5;
1332
1333 init_wrvgai(init, port, index, data);
1334}
1335
1336/**
1337 * INIT_COMPUTE_MEM - opcode 0x63
1338 *
1339 */
1340static void
1341init_compute_mem(struct nvbios_init *init)
1342{
1343 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1344
1345 trace("COMPUTE_MEM\n");
1346 init->offset += 1;
1347
1348 init_exec_force(init, true);
1349 if (init_exec(init) && devinit->meminit)
1350 devinit->meminit(devinit);
1351 init_exec_force(init, false);
1352}
1353
1354/**
1355 * INIT_RESET - opcode 0x65
1356 *
1357 */
1358static void
1359init_reset(struct nvbios_init *init)
1360{
1361 struct nouveau_bios *bios = init->bios;
1362 u32 reg = nv_ro32(bios, init->offset + 1);
1363 u32 data1 = nv_ro32(bios, init->offset + 5);
1364 u32 data2 = nv_ro32(bios, init->offset + 9);
1365 u32 savepci19;
1366
1367 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1368 init->offset += 13;
1369 init_exec_force(init, true);
1370
1371 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1372 init_wr32(init, reg, data1);
1373 udelay(10);
1374 init_wr32(init, reg, data2);
1375 init_wr32(init, 0x00184c, savepci19);
1376 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1377
1378 init_exec_force(init, false);
1379}
1380
1381/**
1382 * INIT_CONFIGURE_MEM - opcode 0x66
1383 *
1384 */
1385static u16
1386init_configure_mem_clk(struct nvbios_init *init)
1387{
1388 u16 mdata = bmp_mem_init_table(init->bios);
1389 if (mdata)
1390 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1391 return mdata;
1392}
1393
1394static void
1395init_configure_mem(struct nvbios_init *init)
1396{
1397 struct nouveau_bios *bios = init->bios;
1398 u16 mdata, sdata;
1399 u32 addr, data;
1400
1401 trace("CONFIGURE_MEM\n");
1402 init->offset += 1;
1403
1404 if (bios->version.major > 2) {
1405 init_done(init);
1406 return;
1407 }
1408 init_exec_force(init, true);
1409
1410 mdata = init_configure_mem_clk(init);
1411 sdata = bmp_sdr_seq_table(bios);
1412 if (nv_ro08(bios, mdata) & 0x01)
1413 sdata = bmp_ddr_seq_table(bios);
1414 mdata += 6; /* skip to data */
1415
1416 data = init_rdvgai(init, 0x03c4, 0x01);
1417 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1418
6b19e47d 1419 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
cb75d97e
BS		 1420 switch (addr) {
1421 case 0x10021c: /* CKE_NORMAL */
1422 case 0x1002d0: /* CMD_REFRESH */
1423 case 0x1002d4: /* CMD_PRECHARGE */
1424 data = 0x00000001;
1425 break;
1426 default:
1427 data = nv_ro32(bios, mdata);
1428 mdata += 4;
1429 if (data == 0xffffffff)
1430 continue;
1431 break;
1432 }
1433
1434 init_wr32(init, addr, data);
1435 }
1436
1437 init_exec_force(init, false);
1438}
1439
1440/**
1441 * INIT_CONFIGURE_CLK - opcode 0x67
1442 *
1443 */
1444static void
1445init_configure_clk(struct nvbios_init *init)
1446{
1447 struct nouveau_bios *bios = init->bios;
1448 u16 mdata, clock;
1449
1450 trace("CONFIGURE_CLK\n");
1451 init->offset += 1;
1452
1453 if (bios->version.major > 2) {
1454 init_done(init);
1455 return;
1456 }
1457 init_exec_force(init, true);
1458
1459 mdata = init_configure_mem_clk(init);
1460
1461 /* NVPLL */
1462 clock = nv_ro16(bios, mdata + 4) * 10;
1463 init_prog_pll(init, 0x680500, clock);
1464
1465 /* MPLL */
1466 clock = nv_ro16(bios, mdata + 2) * 10;
1467 if (nv_ro08(bios, mdata) & 0x01)
1468 clock *= 2;
1469 init_prog_pll(init, 0x680504, clock);
1470
1471 init_exec_force(init, false);
1472}
1473
1474/**
1475 * INIT_CONFIGURE_PREINIT - opcode 0x68
1476 *
1477 */
1478static void
1479init_configure_preinit(struct nvbios_init *init)
1480{
1481 struct nouveau_bios *bios = init->bios;
1482 u32 strap;
1483
1484 trace("CONFIGURE_PREINIT\n");
1485 init->offset += 1;
1486
1487 if (bios->version.major > 2) {
1488 init_done(init);
1489 return;
1490 }
1491 init_exec_force(init, true);
1492
1493 strap = init_rd32(init, 0x101000);
1494 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1495 init_wrvgai(init, 0x03d4, 0x3c, strap);
1496
1497 init_exec_force(init, false);
1498}
1499
1500/**
1501 * INIT_IO - opcode 0x69
1502 *
1503 */
1504static void
1505init_io(struct nvbios_init *init)
1506{
1507 struct nouveau_bios *bios = init->bios;
1508 u16 port = nv_ro16(bios, init->offset + 1);
1509 u8 mask = nv_ro16(bios, init->offset + 3);
1510 u8 data = nv_ro16(bios, init->offset + 4);
1511 u8 value;
1512
1513 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1514 init->offset += 5;
1515
1516 /* ummm.. yes.. should really figure out wtf this is and why it's
1517 * needed some day.. it's almost certainly wrong, but, it also
1518 * somehow makes things work...
1519 */
1520 if (nv_device(init->bios)->card_type >= NV_50 &&
1521 port == 0x03c3 && data == 0x01) {
1522 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1523 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1524 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1525 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1526 mdelay(10);
1527 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1528 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1529 init_wr32(init, 0x614100, 0x00800018);
1530 init_wr32(init, 0x614900, 0x00800018);
1531 mdelay(10);
1532 init_wr32(init, 0x614100, 0x10000018);
1533 init_wr32(init, 0x614900, 0x10000018);
cb75d97e
BS		 1534 }
1535
1536 value = init_rdport(init, port) & mask;
1537 init_wrport(init, port, data | value);
1538}
1539
1540/**
1541 * INIT_SUB - opcode 0x6b
1542 *
1543 */
1544static void
1545init_sub(struct nvbios_init *init)
1546{
1547 struct nouveau_bios *bios = init->bios;
1548 u8 index = nv_ro08(bios, init->offset + 1);
1549 u16 addr, save;
1550
1551 trace("SUB\t0x%02x\n", index);
1552
1553 addr = init_script(bios, index);
1554 if (addr && init_exec(init)) {
1555 save = init->offset;
1556 init->offset = addr;
1557 if (nvbios_exec(init)) {
1558 error("error parsing sub-table\n");
1559 return;
1560 }
1561 init->offset = save;
1562 }
1563
1564 init->offset += 2;
1565}
1566
1567/**
1568 * INIT_RAM_CONDITION - opcode 0x6d
1569 *
1570 */
1571static void
1572init_ram_condition(struct nvbios_init *init)
1573{
1574 struct nouveau_bios *bios = init->bios;
1575 u8 mask = nv_ro08(bios, init->offset + 1);
1576 u8 value = nv_ro08(bios, init->offset + 2);
1577
1578 trace("RAM_CONDITION\t"
1579 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1580 init->offset += 3;
1581
1582 if ((init_rd32(init, 0x100000) & mask) != value)
1583 init_exec_set(init, false);
1584}
1585
1586/**
1587 * INIT_NV_REG - opcode 0x6e
1588 *
1589 */
1590static void
1591init_nv_reg(struct nvbios_init *init)
1592{
1593 struct nouveau_bios *bios = init->bios;
1594 u32 reg = nv_ro32(bios, init->offset + 1);
1595 u32 mask = nv_ro32(bios, init->offset + 5);
1596 u32 data = nv_ro32(bios, init->offset + 9);
1597
1598 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1599 init->offset += 13;
1600
1601 init_mask(init, reg, ~mask, data);
1602}
1603
1604/**
1605 * INIT_MACRO - opcode 0x6f
1606 *
1607 */
1608static void
1609init_macro(struct nvbios_init *init)
1610{
1611 struct nouveau_bios *bios = init->bios;
1612 u8 macro = nv_ro08(bios, init->offset + 1);
1613 u16 table;
1614
1615 trace("MACRO\t0x%02x\n", macro);
1616
1617 table = init_macro_table(init);
1618 if (table) {
1619 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1620 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1621 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1622 init_wr32(init, addr, data);
1623 }
1624
1625 init->offset += 2;
1626}
1627
1628/**
1629 * INIT_RESUME - opcode 0x72
1630 *
1631 */
1632static void
1633init_resume(struct nvbios_init *init)
1634{
1635 trace("RESUME\n");
1636 init->offset += 1;
1637 init_exec_set(init, true);
1638}
1639
1640/**
1641 * INIT_TIME - opcode 0x74
1642 *
1643 */
1644static void
1645init_time(struct nvbios_init *init)
1646{
1647 struct nouveau_bios *bios = init->bios;
1648 u16 usec = nv_ro16(bios, init->offset + 1);
1649
1650 trace("TIME\t0x%04x\n", usec);
1651 init->offset += 3;
1652
1653 if (init_exec(init)) {
1654 if (usec < 1000)
1655 udelay(usec);
1656 else
1657 mdelay((usec + 900) / 1000);
1658 }
1659}
1660
1661/**
1662 * INIT_CONDITION - opcode 0x75
1663 *
1664 */
1665static void
1666init_condition(struct nvbios_init *init)
1667{
1668 struct nouveau_bios *bios = init->bios;
1669 u8 cond = nv_ro08(bios, init->offset + 1);
1670
1671 trace("CONDITION\t0x%02x\n", cond);
1672 init->offset += 2;
1673
1674 if (!init_condition_met(init, cond))
1675 init_exec_set(init, false);
1676}
1677
1678/**
1679 * INIT_IO_CONDITION - opcode 0x76
1680 *
1681 */
1682static void
1683init_io_condition(struct nvbios_init *init)
1684{
1685 struct nouveau_bios *bios = init->bios;
1686 u8 cond = nv_ro08(bios, init->offset + 1);
1687
1688 trace("IO_CONDITION\t0x%02x\n", cond);
1689 init->offset += 2;
1690
1691 if (!init_io_condition_met(init, cond))
1692 init_exec_set(init, false);
1693}
1694
1695/**
1696 * INIT_INDEX_IO - opcode 0x78
1697 *
1698 */
1699static void
1700init_index_io(struct nvbios_init *init)
1701{
1702 struct nouveau_bios *bios = init->bios;
1703 u16 port = nv_ro16(bios, init->offset + 1);
1704 u8 index = nv_ro16(bios, init->offset + 3);
1705 u8 mask = nv_ro08(bios, init->offset + 4);
1706 u8 data = nv_ro08(bios, init->offset + 5);
1707 u8 value;
1708
1709 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1710 port, index, mask, data);
1711 init->offset += 6;
1712
1713 value = init_rdvgai(init, port, index) & mask;
1714 init_wrvgai(init, port, index, data | value);
1715}
1716
1717/**
1718 * INIT_PLL - opcode 0x79
1719 *
1720 */
1721static void
1722init_pll(struct nvbios_init *init)
1723{
1724 struct nouveau_bios *bios = init->bios;
1725 u32 reg = nv_ro32(bios, init->offset + 1);
1726 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1727
1728 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1729 init->offset += 7;
1730
1731 init_prog_pll(init, reg, freq);
1732}
1733
1734/**
1735 * INIT_ZM_REG - opcode 0x7a
1736 *
1737 */
1738static void
1739init_zm_reg(struct nvbios_init *init)
1740{
1741 struct nouveau_bios *bios = init->bios;
1742 u32 addr = nv_ro32(bios, init->offset + 1);
1743 u32 data = nv_ro32(bios, init->offset + 5);
1744
1745 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1746 init->offset += 9;
1747
1748 if (addr == 0x000200)
1749 data |= 0x00000001;
1750
1751 init_wr32(init, addr, data);
1752}
1753
1754/**
1755 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1756 *
1757 */
1758static void
1759init_ram_restrict_pll(struct nvbios_init *init)
1760{
1761 struct nouveau_bios *bios = init->bios;
1762 u8 type = nv_ro08(bios, init->offset + 1);
1763 u8 count = init_ram_restrict_group_count(init);
1764 u8 strap = init_ram_restrict(init);
1765 u8 cconf;
1766
1767 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1768 init->offset += 2;
1769
1770 for (cconf = 0; cconf < count; cconf++) {
1771 u32 freq = nv_ro32(bios, init->offset);
1772
1773 if (cconf == strap) {
1774 trace("%dkHz *\n", freq);
1775 init_prog_pll(init, type, freq);
1776 } else {
1777 trace("%dkHz\n", freq);
1778 }
1779
1780 init->offset += 4;
1781 }
1782}
1783
1784/**
1785 * INIT_GPIO - opcode 0x8e
1786 *
1787 */
1788static void
1789init_gpio(struct nvbios_init *init)
1790{
1791 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1792
1793 trace("GPIO\n");
1794 init->offset += 1;
1795
1796 if (init_exec(init) && gpio && gpio->reset)
1ed73166 1797 gpio->reset(gpio, DCB_GPIO_UNUSED);
cb75d97e
BS		 1798}
1799
1800/**
1801 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1802 *
1803 */
1804static void
1805init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1806{
1807 struct nouveau_bios *bios = init->bios;
1808 u32 addr = nv_ro32(bios, init->offset + 1);
1809 u8 incr = nv_ro08(bios, init->offset + 5);
1810 u8 num = nv_ro08(bios, init->offset + 6);
1811 u8 count = init_ram_restrict_group_count(init);
1812 u8 index = init_ram_restrict(init);
1813 u8 i, j;
1814
1815 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
bfd8bd1f 1816 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
cb75d97e
BS		 1817 init->offset += 7;
1818
1819 for (i = 0; i < num; i++) {
1820 trace("\tR[0x%06x] = {\n", addr);
1821 for (j = 0; j < count; j++) {
1822 u32 data = nv_ro32(bios, init->offset);
1823
1824 if (j == index) {
1825 trace("\t\t0x%08x *\n", data);
1826 init_wr32(init, addr, data);
1827 } else {
1828 trace("\t\t0x%08x\n", data);
1829 }
1830
1831 init->offset += 4;
1832 }
1833 trace("\t}\n");
1834 addr += incr;
1835 }
1836}
1837
1838/**
1839 * INIT_COPY_ZM_REG - opcode 0x90
1840 *
1841 */
1842static void
1843init_copy_zm_reg(struct nvbios_init *init)
1844{
1845 struct nouveau_bios *bios = init->bios;
1846 u32 sreg = nv_ro32(bios, init->offset + 1);
1847 u32 dreg = nv_ro32(bios, init->offset + 5);
1848
bfd8bd1f 1849 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
cb75d97e
BS		 1850 init->offset += 9;
1851
1852 init_wr32(init, dreg, init_rd32(init, sreg));
1853}
1854
1855/**
1856 * INIT_ZM_REG_GROUP - opcode 0x91
1857 *
1858 */
1859static void
1860init_zm_reg_group(struct nvbios_init *init)
1861{
1862 struct nouveau_bios *bios = init->bios;
1863 u32 addr = nv_ro32(bios, init->offset + 1);
1864 u8 count = nv_ro08(bios, init->offset + 5);
1865
950fbfab 1866 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
cb75d97e
BS		 1867 init->offset += 6;
1868
1869 while (count--) {
1870 u32 data = nv_ro32(bios, init->offset);
1871 trace("\t0x%08x\n", data);
1872 init_wr32(init, addr, data);
1873 init->offset += 4;
1874 }
1875}
1876
1877/**
1878 * INIT_XLAT - opcode 0x96
1879 *
1880 */
1881static void
1882init_xlat(struct nvbios_init *init)
1883{
1884 struct nouveau_bios *bios = init->bios;
1885 u32 saddr = nv_ro32(bios, init->offset + 1);
1886 u8 sshift = nv_ro08(bios, init->offset + 5);
1887 u8 smask = nv_ro08(bios, init->offset + 6);
1888 u8 index = nv_ro08(bios, init->offset + 7);
1889 u32 daddr = nv_ro32(bios, init->offset + 8);
1890 u32 dmask = nv_ro32(bios, init->offset + 12);
1891 u8 shift = nv_ro08(bios, init->offset + 16);
1892 u32 data;
1893
1894 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1895 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1896 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1897 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1898 init->offset += 17;
1899
1900 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1901 data = init_xlat_(init, index, data) << shift;
1902 init_mask(init, daddr, ~dmask, data);
1903}
1904
1905/**
1906 * INIT_ZM_MASK_ADD - opcode 0x97
1907 *
1908 */
1909static void
1910init_zm_mask_add(struct nvbios_init *init)
1911{
1912 struct nouveau_bios *bios = init->bios;
1913 u32 addr = nv_ro32(bios, init->offset + 1);
1914 u32 mask = nv_ro32(bios, init->offset + 5);
1915 u32 add = nv_ro32(bios, init->offset + 9);
1916 u32 data;
1917
1918 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1919 init->offset += 13;
1920
46b47b8a
BS		 1921 data = init_rd32(init, addr);
1922 data = (data & mask) | ((data + add) & ~mask);
cb75d97e
BS		 1923 init_wr32(init, addr, data);
1924}
1925
1926/**
1927 * INIT_AUXCH - opcode 0x98
1928 *
1929 */
1930static void
1931init_auxch(struct nvbios_init *init)
1932{
1933 struct nouveau_bios *bios = init->bios;
1934 u32 addr = nv_ro32(bios, init->offset + 1);
1935 u8 count = nv_ro08(bios, init->offset + 5);
1936
1937 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1938 init->offset += 6;
1939
1940 while (count--) {
1941 u8 mask = nv_ro08(bios, init->offset + 0);
1942 u8 data = nv_ro08(bios, init->offset + 1);
1943 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1944 mask = init_rdauxr(init, addr) & mask;
1945 init_wrauxr(init, addr, mask | data);
1946 init->offset += 2;
1947 }
1948}
1949
1950/**
1951 * INIT_AUXCH - opcode 0x99
1952 *
1953 */
1954static void
1955init_zm_auxch(struct nvbios_init *init)
1956{
1957 struct nouveau_bios *bios = init->bios;
1958 u32 addr = nv_ro32(bios, init->offset + 1);
1959 u8 count = nv_ro08(bios, init->offset + 5);
1960
1961 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1962 init->offset += 6;
1963
1964 while (count--) {
1965 u8 data = nv_ro08(bios, init->offset + 0);
1966 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1967 init_wrauxr(init, addr, data);
1968 init->offset += 1;
1969 }
1970}
1971
1972/**
1973 * INIT_I2C_LONG_IF - opcode 0x9a
1974 *
1975 */
1976static void
1977init_i2c_long_if(struct nvbios_init *init)
1978{
1979 struct nouveau_bios *bios = init->bios;
1980 u8 index = nv_ro08(bios, init->offset + 1);
1981 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1982 u8 reglo = nv_ro08(bios, init->offset + 3);
1983 u8 reghi = nv_ro08(bios, init->offset + 4);
1984 u8 mask = nv_ro08(bios, init->offset + 5);
1985 u8 data = nv_ro08(bios, init->offset + 6);
1986 struct nouveau_i2c_port *port;
1987
1988 trace("I2C_LONG_IF\t"
1989 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1990 index, addr, reglo, reghi, mask, data);
1991 init->offset += 7;
1992
1993 port = init_i2c(init, index);
1994 if (port) {
1995 u8 i[2] = { reghi, reglo };
1996 u8 o[1] = {};
1997 struct i2c_msg msg[] = {
1998 { .addr = addr, .flags = 0, .len = 2, .buf = i },
1999 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2000 };
2001 int ret;
2002
2003 ret = i2c_transfer(&port->adapter, msg, 2);
2004 if (ret == 2 && ((o[0] & mask) == data))
2005 return;
2006 }
2007
2008 init_exec_set(init, false);
2009}
2010
1ed73166
BS		 2011/**
2012 * INIT_GPIO_NE - opcode 0xa9
2013 *
2014 */
2015static void
2016init_gpio_ne(struct nvbios_init *init)
2017{
2018 struct nouveau_bios *bios = init->bios;
2019 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2020 struct dcb_gpio_func func;
2021 u8 count = nv_ro08(bios, init->offset + 1);
2022 u8 idx = 0, ver, len;
2023 u16 data, i;
2024
2025 trace("GPIO_NE\t");
2026 init->offset += 2;
2027
2028 for (i = init->offset; i < init->offset + count; i++)
2029 cont("0x%02x ", nv_ro08(bios, i));
2030 cont("\n");
2031
2032 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2033 if (func.func != DCB_GPIO_UNUSED) {
2034 for (i = init->offset; i < init->offset + count; i++) {
2035 if (func.func == nv_ro08(bios, i))
2036 break;
2037 }
2038
2039 trace("\tFUNC[0x%02x]", func.func);
2040 if (i == (init->offset + count)) {
2041 cont(" *");
2042 if (init_exec(init) && gpio && gpio->reset)
2043 gpio->reset(gpio, func.func);
2044 }
2045 cont("\n");
2046 }
2047 }
2048
2049 init->offset += count;
2050}
2051
cb75d97e
BS		 2052static struct nvbios_init_opcode {
2053 void (*exec)(struct nvbios_init *);
2054} init_opcode[] = {
2055 [0x32] = { init_io_restrict_prog },
2056 [0x33] = { init_repeat },
2057 [0x34] = { init_io_restrict_pll },
2058 [0x36] = { init_end_repeat },
2059 [0x37] = { init_copy },
2060 [0x38] = { init_not },
2061 [0x39] = { init_io_flag_condition },
2062 [0x3a] = { init_dp_condition },
2063 [0x3b] = { init_io_mask_or },
2064 [0x3c] = { init_io_or },
2065 [0x49] = { init_idx_addr_latched },
2066 [0x4a] = { init_io_restrict_pll2 },
2067 [0x4b] = { init_pll2 },
2068 [0x4c] = { init_i2c_byte },
2069 [0x4d] = { init_zm_i2c_byte },
2070 [0x4e] = { init_zm_i2c },
2071 [0x4f] = { init_tmds },
2072 [0x50] = { init_zm_tmds_group },
2073 [0x51] = { init_cr_idx_adr_latch },
2074 [0x52] = { init_cr },
2075 [0x53] = { init_zm_cr },
2076 [0x54] = { init_zm_cr_group },
2077 [0x56] = { init_condition_time },
2078 [0x57] = { init_ltime },
2079 [0x58] = { init_zm_reg_sequence },
2080 [0x5b] = { init_sub_direct },
2081 [0x5c] = { init_jump },
2082 [0x5e] = { init_i2c_if },
2083 [0x5f] = { init_copy_nv_reg },
2084 [0x62] = { init_zm_index_io },
2085 [0x63] = { init_compute_mem },
2086 [0x65] = { init_reset },
2087 [0x66] = { init_configure_mem },
2088 [0x67] = { init_configure_clk },
2089 [0x68] = { init_configure_preinit },
2090 [0x69] = { init_io },
2091 [0x6b] = { init_sub },
2092 [0x6d] = { init_ram_condition },
2093 [0x6e] = { init_nv_reg },
2094 [0x6f] = { init_macro },
2095 [0x71] = { init_done },
2096 [0x72] = { init_resume },
2097 [0x74] = { init_time },
2098 [0x75] = { init_condition },
2099 [0x76] = { init_io_condition },
2100 [0x78] = { init_index_io },
2101 [0x79] = { init_pll },
2102 [0x7a] = { init_zm_reg },
2103 [0x87] = { init_ram_restrict_pll },
2104 [0x8c] = { init_reserved },
2105 [0x8d] = { init_reserved },
2106 [0x8e] = { init_gpio },
2107 [0x8f] = { init_ram_restrict_zm_reg_group },
2108 [0x90] = { init_copy_zm_reg },
2109 [0x91] = { init_zm_reg_group },
2110 [0x92] = { init_reserved },
2111 [0x96] = { init_xlat },
2112 [0x97] = { init_zm_mask_add },
2113 [0x98] = { init_auxch },
2114 [0x99] = { init_zm_auxch },
2115 [0x9a] = { init_i2c_long_if },
1ed73166 2116 [0xa9] = { init_gpio_ne },
5495e39f 2117 [0xaa] = { init_reserved },
cb75d97e
BS		 2118};
2119
2120#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2121
2122int
2123nvbios_exec(struct nvbios_init *init)
2124{
2125 init->nested++;
2126 while (init->offset) {
2127 u8 opcode = nv_ro08(init->bios, init->offset);
2128 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2129 error("unknown opcode 0x%02x\n", opcode);
2130 return -EINVAL;
2131 }
2132
2133 init_opcode[opcode].exec(init);
2134 }
2135 init->nested--;
2136 return 0;
2137}
2138
2139int
2140nvbios_init(struct nouveau_subdev *subdev, bool execute)
2141{
2142 struct nouveau_bios *bios = nouveau_bios(subdev);
2143 int ret = 0;
2144 int i = -1;
2145 u16 data;
2146
2147 if (execute)
c52f4fa6 2148 nv_info(bios, "running init tables\n");
cb75d97e
BS		 2149 while (!ret && (data = (init_script(bios, ++i)))) {
2150 struct nvbios_init init = {
2151 .subdev = subdev,
2152 .bios = bios,
2153 .offset = data,
2154 .outp = NULL,
2155 .crtc = -1,
2156 .execute = execute ? 1 : 0,
2157 };
2158
2159 ret = nvbios_exec(&init);
2160 }
2161
2162 /* the vbios parser will run this right after the normal init
2163 * tables, whereas the binary driver appears to run it later.
2164 */
2165 if (!ret && (data = init_unknown_script(bios))) {
2166 struct nvbios_init init = {
2167 .subdev = subdev,
2168 .bios = bios,
2169 .offset = data,
2170 .outp = NULL,
2171 .crtc = -1,
2172 .execute = execute ? 1 : 0,
2173 };
2174
2175 ret = nvbios_exec(&init);
2176 }
2177
3db0fdb4 2178 return ret;
cb75d97e 2179}
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