[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / nouveau / core / subdev / device / nv40.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/device.h>
#include <subdev/bios.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>

int
nv40_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0x40:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x41:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x42:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x43:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x45:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x47:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x49:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x4b:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv04_mc_oclass;
		break;
	case 0x44:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x46:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x4a:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x4c:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x4e:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x63:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x67:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	case 0x68:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv10_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nv40_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nv44_mc_oclass;
		break;
	default:
		nv_fatal(device, "unknown Curie chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/device.h>
70c0f263	26	#include <subdev/bios.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
cb75d97e	30	#include <subdev/devinit.h>
7d9115de	31	#include <subdev/mc.h>
9274f4a9 BS	32
	33	int
	34	nv40_identify(struct nouveau_device *device)
	35	{
	36	switch (device->chipset) {
	37	case 0x40:
70c0f263	38	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	39	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	40	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	41	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	42	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	43	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	44	break;
9274f4a9 BS	45	case 0x41:
70c0f263	46	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	47	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	48	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	49	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	50	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	51	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	52	break;
9274f4a9 BS	53	case 0x42:
70c0f263	54	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	55	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	56	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	57	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	58	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	59	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	60	break;
9274f4a9 BS	61	case 0x43:
70c0f263	62	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	63	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	64	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	65	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	66	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	67	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	68	break;
9274f4a9 BS	69	case 0x45:
70c0f263	70	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	71	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	72	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	73	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	74	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	75	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	76	break;
9274f4a9 BS	77	case 0x47:
70c0f263	78	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	79	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	80	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	81	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	82	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	83	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	84	break;
9274f4a9 BS	85	case 0x49:
70c0f263	86	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	87	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	88	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	89	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	90	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	91	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	92	break;
9274f4a9 BS	93	case 0x4b:
70c0f263	94	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	95	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	96	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	97	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	98	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	99	device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
9274f4a9 BS	100	break;
9274f4a9 BS	101	case 0x44:
70c0f263	102	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	103	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	104	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	105	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	106	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	107	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	108	break;
9274f4a9 BS	109	case 0x46:
70c0f263	110	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	111	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	112	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	113	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	114	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	115	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	116	break;
9274f4a9 BS	117	case 0x4a:
70c0f263	118	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	119	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	120	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	121	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	122	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	123	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	124	break;
9274f4a9 BS	125	case 0x4c:
70c0f263	126	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	127	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	128	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	129	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	130	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	131	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	132	break;
9274f4a9 BS	133	case 0x4e:
70c0f263	134	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	135	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	136	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	137	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	138	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	139	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	140	break;
9274f4a9 BS	141	case 0x63:
70c0f263	142	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	143	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	144	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	145	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	146	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	147	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	148	break;
9274f4a9 BS	149	case 0x67:
70c0f263	150	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	151	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	152	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	153	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	154	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	155	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	156	break;
9274f4a9 BS	157	case 0x68:
70c0f263	158	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	159	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
4196faa8	160	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	161	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
cb75d97e	162	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
7d9115de	163	device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
9274f4a9 BS	164	break;
	165	default:
	166	nv_fatal(device, "unknown Curie chipset\n");
	167	return -EINVAL;
	168	}
	169
	170	return 0;
	171	}