[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / core / subdev / fb / nv50.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/object.h>
#include <core/enum.h>

#include <subdev/fb.h>
#include <subdev/bios.h>

struct nv50_fb_priv {
	struct nouveau_fb base;
	struct page *r100c08_page;
	dma_addr_t r100c08;
};

static int types[0x80] = {
	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
	1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
	0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
	1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
};

static bool
nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
{
	return types[(memtype & 0xff00) >> 8] != 0;
}

static int
nv50_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
		 u32 memtype, struct nouveau_mem **pmem)
{
	struct nv50_fb_priv *priv = (void *)pfb;
	struct nouveau_mm *heap = &priv->base.vram;
	struct nouveau_mm *tags = &priv->base.tags;
	struct nouveau_mm_node *r;
	struct nouveau_mem *mem;
	int comp = (memtype & 0x300) >> 8;
	int type = (memtype & 0x07f);
	int back = (memtype & 0x800);
	int min, max, ret;

	max = (size >> 12);
	min = ncmin ? (ncmin >> 12) : max;
	align >>= 12;

	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
	if (!mem)
		return -ENOMEM;

	mutex_lock(&pfb->base.mutex);
	if (comp) {
		if (align == 16) {
			int n = (max >> 4) * comp;

			ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
			if (ret)
				mem->tag = NULL;
		}

		if (unlikely(!mem->tag))
			comp = 0;
	}

	INIT_LIST_HEAD(&mem->regions);
	mem->memtype = (comp << 7) | type;
	mem->size = max;

	type = types[type];
	do {
		if (back)
			ret = nouveau_mm_tail(heap, type, max, min, align, &r);
		else
			ret = nouveau_mm_head(heap, type, max, min, align, &r);
		if (ret) {
			mutex_unlock(&pfb->base.mutex);
			pfb->ram.put(pfb, &mem);
			return ret;
		}

		list_add_tail(&r->rl_entry, &mem->regions);
		max -= r->length;
	} while (max);
	mutex_unlock(&pfb->base.mutex);

	r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
	mem->offset = (u64)r->offset << 12;
	*pmem = mem;
	return 0;
}

void
nv50_fb_vram_del(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
{
	struct nv50_fb_priv *priv = (void *)pfb;
	struct nouveau_mm_node *this;
	struct nouveau_mem *mem;

	mem = *pmem;
	*pmem = NULL;
	if (unlikely(mem == NULL))
		return;

	mutex_lock(&pfb->base.mutex);
	while (!list_empty(&mem->regions)) {
		this = list_first_entry(&mem->regions, typeof(*this), rl_entry);

		list_del(&this->rl_entry);
		nouveau_mm_free(&priv->base.vram, &this);
	}

	nouveau_mm_free(&priv->base.tags, &mem->tag);
	mutex_unlock(&pfb->base.mutex);

	kfree(mem);
}

static u32
nv50_vram_rblock(struct nv50_fb_priv *priv)
{
	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	u64 rowsize, predicted;
	u32 r0, r4, rt, ru, rblock_size;

	r0 = nv_rd32(priv, 0x100200);
	r4 = nv_rd32(priv, 0x100204);
	rt = nv_rd32(priv, 0x100250);
	ru = nv_rd32(priv, 0x001540);
	nv_debug(priv, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);

	for (i = 0, parts = 0; i < 8; i++) {
		if (ru & (0x00010000 << i))
			parts++;
	}

	colbits  =  (r4 & 0x0000f000) >> 12;
	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);

	rowsize = parts * banks * (1 << colbits) * 8;
	predicted = rowsize << rowbitsa;
	if (r0 & 0x00000004)
		predicted += rowsize << rowbitsb;

	if (predicted != priv->base.ram.size) {
		nv_warn(priv, "memory controller reports %d MiB VRAM\n",
			(u32)(priv->base.ram.size >> 20));
	}

	rblock_size = rowsize;
	if (rt & 1)
		rblock_size *= 3;

	nv_debug(priv, "rblock %d bytes\n", rblock_size);
	return rblock_size;
}

static int
nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
	     struct nouveau_oclass *oclass, void *data, u32 size,
	     struct nouveau_object **pobject)
{
	struct nouveau_device *device = nv_device(parent);
	struct nouveau_bios *bios = nouveau_bios(device);
	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
	struct nv50_fb_priv *priv;
	u32 tags;
	int ret;

	ret = nouveau_fb_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	switch (nv_rd32(priv, 0x100714) & 0x00000007) {
	case 0: priv->base.ram.type = NV_MEM_TYPE_DDR1; break;
	case 1:
		if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
			priv->base.ram.type = NV_MEM_TYPE_DDR3;
		else
			priv->base.ram.type = NV_MEM_TYPE_DDR2;
		break;
	case 2: priv->base.ram.type = NV_MEM_TYPE_GDDR3; break;
	case 3: priv->base.ram.type = NV_MEM_TYPE_GDDR4; break;
	case 4: priv->base.ram.type = NV_MEM_TYPE_GDDR5; break;
	default:
		break;
	}

	priv->base.ram.size = nv_rd32(priv, 0x10020c);
	priv->base.ram.size = (priv->base.ram.size & 0xffffff00) |
			     ((priv->base.ram.size & 0x000000ff) << 32);

	tags = nv_rd32(priv, 0x100320);
	ret = nouveau_mm_init(&priv->base.tags, 0, tags, 1);
	if (ret)
		return ret;

	nv_debug(priv, "%d compression tags\n", tags);

	size = (priv->base.ram.size >> 12) - rsvd_head - rsvd_tail;
	switch (device->chipset) {
	case 0xaa:
	case 0xac:
	case 0xaf: /* IGPs, no reordering, no real VRAM */
		ret = nouveau_mm_init(&priv->base.vram, rsvd_head, size, 1);
		if (ret)
			return ret;

		priv->base.ram.stolen = (u64)nv_rd32(priv, 0x100e10) << 12;
		priv->base.ram.type = NV_MEM_TYPE_STOLEN;
		break;
	default:
		ret = nouveau_mm_init(&priv->base.vram, rsvd_head, size,
				      nv50_vram_rblock(priv) >> 12);
		if (ret)
			return ret;

		priv->base.ram.ranks = (nv_rd32(priv, 0x100200) & 0x4) ? 2 : 1;
		break;
	}

	priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
	if (priv->r100c08_page) {
		priv->r100c08 = pci_map_page(device->pdev, priv->r100c08_page,
					     0, PAGE_SIZE,
					     PCI_DMA_BIDIRECTIONAL);
		if (pci_dma_mapping_error(device->pdev, priv->r100c08))
			nv_warn(priv, "failed 0x100c08 page map\n");
	} else {
		nv_warn(priv, "failed 0x100c08 page alloc\n");
	}

	priv->base.memtype_valid = nv50_fb_memtype_valid;
	priv->base.ram.get = nv50_fb_vram_new;
	priv->base.ram.put = nv50_fb_vram_del;
	return nouveau_fb_created(&priv->base);
}

static void
nv50_fb_dtor(struct nouveau_object *object)
{
	struct nouveau_device *device = nv_device(object);
	struct nv50_fb_priv *priv = (void *)object;

	if (priv->r100c08_page) {
		pci_unmap_page(device->pdev, priv->r100c08, PAGE_SIZE,
			       PCI_DMA_BIDIRECTIONAL);
		__free_page(priv->r100c08_page);
	}

	nouveau_fb_destroy(&priv->base);
}

static int
nv50_fb_init(struct nouveau_object *object)
{
	struct nouveau_device *device = nv_device(object);
	struct nv50_fb_priv *priv = (void *)object;
	int ret;

	ret = nouveau_fb_init(&priv->base);
	if (ret)
		return ret;

	/* Not a clue what this is exactly.  Without pointing it at a
	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	 * cause IOMMU "read from address 0" errors (rh#561267)
	 */
	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);

	/* This is needed to get meaningful information from 100c90
	 * on traps. No idea what these values mean exactly. */
	switch (device->chipset) {
	case 0x50:
		nv_wr32(priv, 0x100c90, 0x000707ff);
		break;
	case 0xa3:
	case 0xa5:
	case 0xa8:
		nv_wr32(priv, 0x100c90, 0x000d0fff);
		break;
	case 0xaf:
		nv_wr32(priv, 0x100c90, 0x089d1fff);
		break;
	default:
		nv_wr32(priv, 0x100c90, 0x001d07ff);
		break;
	}

	return 0;
}

struct nouveau_oclass
nv50_fb_oclass = {
	.handle = NV_SUBDEV(FB, 0x50),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_fb_ctor,
		.dtor = nv50_fb_dtor,
		.init = nv50_fb_init,
		.fini = _nouveau_fb_fini,
	},
};

static const struct nouveau_enum vm_dispatch_subclients[] = {
	{ 0x00000000, "GRCTX", NULL },
	{ 0x00000001, "NOTIFY", NULL },
	{ 0x00000002, "QUERY", NULL },
	{ 0x00000003, "COND", NULL },
	{ 0x00000004, "M2M_IN", NULL },
	{ 0x00000005, "M2M_OUT", NULL },
	{ 0x00000006, "M2M_NOTIFY", NULL },
	{}
};

static const struct nouveau_enum vm_ccache_subclients[] = {
	{ 0x00000000, "CB", NULL },
	{ 0x00000001, "TIC", NULL },
	{ 0x00000002, "TSC", NULL },
	{}
};

static const struct nouveau_enum vm_prop_subclients[] = {
	{ 0x00000000, "RT0", NULL },
	{ 0x00000001, "RT1", NULL },
	{ 0x00000002, "RT2", NULL },
	{ 0x00000003, "RT3", NULL },
	{ 0x00000004, "RT4", NULL },
	{ 0x00000005, "RT5", NULL },
	{ 0x00000006, "RT6", NULL },
	{ 0x00000007, "RT7", NULL },
	{ 0x00000008, "ZETA", NULL },
	{ 0x00000009, "LOCAL", NULL },
	{ 0x0000000a, "GLOBAL", NULL },
	{ 0x0000000b, "STACK", NULL },
	{ 0x0000000c, "DST2D", NULL },
	{}
};

static const struct nouveau_enum vm_pfifo_subclients[] = {
	{ 0x00000000, "PUSHBUF", NULL },
	{ 0x00000001, "SEMAPHORE", NULL },
	{}
};

static const struct nouveau_enum vm_bar_subclients[] = {
	{ 0x00000000, "FB", NULL },
	{ 0x00000001, "IN", NULL },
	{}
};

static const struct nouveau_enum vm_client[] = {
	{ 0x00000000, "STRMOUT", NULL },
	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
	{ 0x00000004, "PFIFO_WRITE", NULL },
	{ 0x00000005, "CCACHE", vm_ccache_subclients },
	{ 0x00000006, "PPPP", NULL },
	{ 0x00000007, "CLIPID", NULL },
	{ 0x00000008, "PFIFO_READ", NULL },
	{ 0x00000009, "VFETCH", NULL },
	{ 0x0000000a, "TEXTURE", NULL },
	{ 0x0000000b, "PROP", vm_prop_subclients },
	{ 0x0000000c, "PVP", NULL },
	{ 0x0000000d, "PBSP", NULL },
	{ 0x0000000e, "PCRYPT", NULL },
	{ 0x0000000f, "PCOUNTER", NULL },
	{ 0x00000011, "PDAEMON", NULL },
	{}
};

static const struct nouveau_enum vm_engine[] = {
	{ 0x00000000, "PGRAPH", NULL },
	{ 0x00000001, "PVP", NULL },
	{ 0x00000004, "PEEPHOLE", NULL },
	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
	{ 0x00000006, "BAR", vm_bar_subclients },
	{ 0x00000008, "PPPP", NULL },
	{ 0x00000009, "PBSP", NULL },
	{ 0x0000000a, "PCRYPT", NULL },
	{ 0x0000000b, "PCOUNTER", NULL },
	{ 0x0000000c, "SEMAPHORE_BG", NULL },
	{ 0x0000000d, "PCOPY", NULL },
	{ 0x0000000e, "PDAEMON", NULL },
	{}
};

static const struct nouveau_enum vm_fault[] = {
	{ 0x00000000, "PT_NOT_PRESENT", NULL },
	{ 0x00000001, "PT_TOO_SHORT", NULL },
	{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
	{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
	{ 0x00000004, "PAGE_READ_ONLY", NULL },
	{ 0x00000006, "NULL_DMAOBJ", NULL },
	{ 0x00000007, "WRONG_MEMTYPE", NULL },
	{ 0x0000000b, "VRAM_LIMIT", NULL },
	{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
	{}
};

void
nv50_fb_trap(struct nouveau_fb *pfb, int display)
{
	struct nouveau_device *device = nv_device(pfb);
	struct nv50_fb_priv *priv = (void *)pfb;
	const struct nouveau_enum *en, *cl;
	u32 trap[6], idx, chan;
	u8 st0, st1, st2, st3;
	int i;

	idx = nv_rd32(priv, 0x100c90);
	if (!(idx & 0x80000000))
		return;
	idx &= 0x00ffffff;

	for (i = 0; i < 6; i++) {
		nv_wr32(priv, 0x100c90, idx | i << 24);
		trap[i] = nv_rd32(priv, 0x100c94);
	}
	nv_wr32(priv, 0x100c90, idx | 0x80000000);

	if (!display)
		return;

	/* decode status bits into something more useful */
	if (device->chipset  < 0xa3 ||
	    device->chipset == 0xaa || device->chipset == 0xac) {
		st0 = (trap[0] & 0x0000000f) >> 0;
		st1 = (trap[0] & 0x000000f0) >> 4;
		st2 = (trap[0] & 0x00000f00) >> 8;
		st3 = (trap[0] & 0x0000f000) >> 12;
	} else {
		st0 = (trap[0] & 0x000000ff) >> 0;
		st1 = (trap[0] & 0x0000ff00) >> 8;
		st2 = (trap[0] & 0x00ff0000) >> 16;
		st3 = (trap[0] & 0xff000000) >> 24;
	}
	chan = (trap[2] << 16) | trap[1];

	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x ",
		 (trap[5] & 0x00000100) ? "read" : "write",
		 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan);

	en = nouveau_enum_find(vm_engine, st0);
	if (en)
		printk("%s/", en->name);
	else
		printk("%02x/", st0);

	cl = nouveau_enum_find(vm_client, st2);
	if (cl)
		printk("%s/", cl->name);
	else
		printk("%02x/", st2);

	if      (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
	else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
	else                     cl = NULL;
	if (cl)
		printk("%s", cl->name);
	else
		printk("%02x", st3);

	printk(" reason: ");
	en = nouveau_enum_find(vm_fault, st1);
	if (en)
		printk("%s\n", en->name);
	else
		printk("0x%08x\n", st1);
}
Commit	Line	Data
861d2107 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <core/object.h>
	26	#include <core/enum.h>
	27
	28	#include <subdev/fb.h>
	29	#include <subdev/bios.h>
304424e1	30
20f63afe	31	struct nv50_fb_priv {
861d2107	32	struct nouveau_fb base;
20f63afe BS	33	struct page *r100c08_page;
	34	dma_addr_t r100c08;
	35	};
	36
861d2107 BS	37	static int types[0x80] = {
	38	1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	39	1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
	40	1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
	41	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	42	1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
	43	0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	44	1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
	45	1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
	46	};
	47
	48	static bool
	49	nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
8f7286f8	50	{
861d2107 BS	51	return types[(memtype & 0xff00) >> 8] != 0;
861d2107 BS	52	}
8f7286f8	53
861d2107 BS	54	static int
	55	nv50_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
	56	u32 memtype, struct nouveau_mem **pmem)
	57	{
	58	struct nv50_fb_priv priv = (void )pfb;
	59	struct nouveau_mm *heap = &priv->base.vram;
	60	struct nouveau_mm *tags = &priv->base.tags;
	61	struct nouveau_mm_node *r;
	62	struct nouveau_mem *mem;
	63	int comp = (memtype & 0x300) >> 8;
	64	int type = (memtype & 0x07f);
	65	int back = (memtype & 0x800);
	66	int min, max, ret;
	67
	68	max = (size >> 12);
	69	min = ncmin ? (ncmin >> 12) : max;
	70	align >>= 12;
	71
	72	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
	73	if (!mem)
	74	return -ENOMEM;
8f7286f8	75
861d2107 BS	76	mutex_lock(&pfb->base.mutex);
	77	if (comp) {
	78	if (align == 16) {
	79	int n = (max >> 4) * comp;
	80
	81	ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
	82	if (ret)
	83	mem->tag = NULL;
	84	}
	85
	86	if (unlikely(!mem->tag))
	87	comp = 0;
8f7286f8 BS	88	}
8f7286f8 BS	89
861d2107 BS	90	INIT_LIST_HEAD(&mem->regions);
	91	mem->memtype = (comp << 7) \| type;
	92	mem->size = max;
	93
	94	type = types[type];
	95	do {
	96	if (back)
	97	ret = nouveau_mm_tail(heap, type, max, min, align, &r);
	98	else
	99	ret = nouveau_mm_head(heap, type, max, min, align, &r);
	100	if (ret) {
	101	mutex_unlock(&pfb->base.mutex);
	102	pfb->ram.put(pfb, &mem);
	103	return ret;
	104	}
	105
	106	list_add_tail(&r->rl_entry, &mem->regions);
	107	max -= r->length;
	108	} while (max);
	109	mutex_unlock(&pfb->base.mutex);
	110
	111	r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
	112	mem->offset = (u64)r->offset << 12;
	113	*pmem = mem;
	114	return 0;
8f7286f8 BS	115	}
8f7286f8 BS	116
861d2107 BS	117	void
861d2107 BS	118	nv50_fb_vram_del(struct nouveau_fb pfb, struct nouveau_mem *pmem)
20f63afe	119	{
861d2107 BS	120	struct nv50_fb_priv priv = (void )pfb;
	121	struct nouveau_mm_node *this;
	122	struct nouveau_mem *mem;
20f63afe	123
861d2107 BS	124	mem = *pmem;
	125	*pmem = NULL;
	126	if (unlikely(mem == NULL))
	127	return;
20f63afe	128
861d2107 BS	129	mutex_lock(&pfb->base.mutex);
	130	while (!list_empty(&mem->regions)) {
	131	this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
	132
	133	list_del(&this->rl_entry);
	134	nouveau_mm_free(&priv->base.vram, &this);
20f63afe BS	135	}
20f63afe BS	136
861d2107 BS	137	nouveau_mm_free(&priv->base.tags, &mem->tag);
	138	mutex_unlock(&pfb->base.mutex);
	139
	140	kfree(mem);
	141	}
	142
	143	static u32
	144	nv50_vram_rblock(struct nv50_fb_priv *priv)
	145	{
	146	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	147	u64 rowsize, predicted;
	148	u32 r0, r4, rt, ru, rblock_size;
	149
	150	r0 = nv_rd32(priv, 0x100200);
	151	r4 = nv_rd32(priv, 0x100204);
	152	rt = nv_rd32(priv, 0x100250);
	153	ru = nv_rd32(priv, 0x001540);
	154	nv_debug(priv, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
	155
	156	for (i = 0, parts = 0; i < 8; i++) {
	157	if (ru & (0x00010000 << i))
	158	parts++;
20f63afe BS	159	}
20f63afe BS	160
861d2107 BS	161	colbits = (r4 & 0x0000f000) >> 12;
	162	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	163	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	164	banks = 1 << (((r4 & 0x03000000) >> 24) + 2);
	165
	166	rowsize = parts * banks * (1 << colbits) * 8;
	167	predicted = rowsize << rowbitsa;
	168	if (r0 & 0x00000004)
	169	predicted += rowsize << rowbitsb;
	170
	171	if (predicted != priv->base.ram.size) {
	172	nv_warn(priv, "memory controller reports %d MiB VRAM\n",
	173	(u32)(priv->base.ram.size >> 20));
8f7286f8 BS	174	}
8f7286f8 BS	175
861d2107 BS	176	rblock_size = rowsize;
	177	if (rt & 1)
	178	rblock_size *= 3;
	179
	180	nv_debug(priv, "rblock %d bytes\n", rblock_size);
	181	return rblock_size;
20f63afe BS	182	}
20f63afe BS	183
861d2107 BS	184	static int
	185	nv50_fb_ctor(struct nouveau_object parent, struct nouveau_object engine,
	186	struct nouveau_oclass oclass, void data, u32 size,
	187	struct nouveau_object **pobject)
304424e1	188	{
861d2107 BS	189	struct nouveau_device *device = nv_device(parent);
	190	struct nouveau_bios *bios = nouveau_bios(device);
	191	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
	192	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
20f63afe	193	struct nv50_fb_priv *priv;
861d2107	194	u32 tags;
20f63afe BS	195	int ret;
20f63afe BS	196
861d2107 BS	197	ret = nouveau_fb_create(parent, engine, oclass, &priv);
	198	*pobject = nv_object(priv);
	199	if (ret)
	200	return ret;
	201
	202	switch (nv_rd32(priv, 0x100714) & 0x00000007) {
	203	case 0: priv->base.ram.type = NV_MEM_TYPE_DDR1; break;
	204	case 1:
	205	if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
	206	priv->base.ram.type = NV_MEM_TYPE_DDR3;
	207	else
	208	priv->base.ram.type = NV_MEM_TYPE_DDR2;
	209	break;
	210	case 2: priv->base.ram.type = NV_MEM_TYPE_GDDR3; break;
	211	case 3: priv->base.ram.type = NV_MEM_TYPE_GDDR4; break;
	212	case 4: priv->base.ram.type = NV_MEM_TYPE_GDDR5; break;
	213	default:
	214	break;
	215	}
	216
	217	priv->base.ram.size = nv_rd32(priv, 0x10020c);
	218	priv->base.ram.size = (priv->base.ram.size & 0xffffff00) \|
	219	((priv->base.ram.size & 0x000000ff) << 32);
	220
	221	tags = nv_rd32(priv, 0x100320);
5cad16ac BS	222	ret = nouveau_mm_init(&priv->base.tags, 0, tags, 1);
	223	if (ret)
	224	return ret;
861d2107	225
5cad16ac	226	nv_debug(priv, "%d compression tags\n", tags);
861d2107 BS	227
	228	size = (priv->base.ram.size >> 12) - rsvd_head - rsvd_tail;
	229	switch (device->chipset) {
	230	case 0xaa:
	231	case 0xac:
	232	case 0xaf: /* IGPs, no reordering, no real VRAM */
	233	ret = nouveau_mm_init(&priv->base.vram, rsvd_head, size, 1);
	234	if (ret)
	235	return ret;
	236
	237	priv->base.ram.stolen = (u64)nv_rd32(priv, 0x100e10) << 12;
2c25b739	238	priv->base.ram.type = NV_MEM_TYPE_STOLEN;
861d2107 BS	239	break;
	240	default:
	241	ret = nouveau_mm_init(&priv->base.vram, rsvd_head, size,
	242	nv50_vram_rblock(priv) >> 12);
	243	if (ret)
	244	return ret;
	245
	246	priv->base.ram.ranks = (nv_rd32(priv, 0x100200) & 0x4) ? 2 : 1;
	247	break;
	248	}
	249
	250	priv->r100c08_page = alloc_page(GFP_KERNEL \| __GFP_ZERO);
	251	if (priv->r100c08_page) {
	252	priv->r100c08 = pci_map_page(device->pdev, priv->r100c08_page,
	253	0, PAGE_SIZE,
	254	PCI_DMA_BIDIRECTIONAL);
	255	if (pci_dma_mapping_error(device->pdev, priv->r100c08))
	256	nv_warn(priv, "failed 0x100c08 page map\n");
	257	} else {
	258	nv_warn(priv, "failed 0x100c08 page alloc\n");
20f63afe	259	}
861d2107 BS	260
	261	priv->base.memtype_valid = nv50_fb_memtype_valid;
	262	priv->base.ram.get = nv50_fb_vram_new;
	263	priv->base.ram.put = nv50_fb_vram_del;
	264	return nouveau_fb_created(&priv->base);
	265	}
	266
	267	static void
	268	nv50_fb_dtor(struct nouveau_object *object)
	269	{
	270	struct nouveau_device *device = nv_device(object);
	271	struct nv50_fb_priv priv = (void )object;
	272
	273	if (priv->r100c08_page) {
	274	pci_unmap_page(device->pdev, priv->r100c08, PAGE_SIZE,
	275	PCI_DMA_BIDIRECTIONAL);
	276	__free_page(priv->r100c08_page);
	277	}
	278
861d2107 BS	279	nouveau_fb_destroy(&priv->base);
	280	}
	281
	282	static int
	283	nv50_fb_init(struct nouveau_object *object)
	284	{
	285	struct nouveau_device *device = nv_device(object);
	286	struct nv50_fb_priv priv = (void )object;
	287	int ret;
	288
	289	ret = nouveau_fb_init(&priv->base);
	290	if (ret)
	291	return ret;
304424e1	292
4eb3033c BS	293	/* Not a clue what this is exactly. Without pointing it at a
	294	* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	295	* cause IOMMU "read from address 0" errors (rh#561267)
	296	*/
861d2107	297	nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
4eb3033c BS	298
	299	/* This is needed to get meaningful information from 100c90
	300	* on traps. No idea what these values mean exactly. */
861d2107	301	switch (device->chipset) {
304424e1	302	case 0x50:
861d2107	303	nv_wr32(priv, 0x100c90, 0x000707ff);
304424e1	304	break;
f9aafdd3	305	case 0xa3:
304424e1 MK	306	case 0xa5:
304424e1 MK	307	case 0xa8:
861d2107	308	nv_wr32(priv, 0x100c90, 0x000d0fff);
9fea1bcb BS	309	break;
9fea1bcb BS	310	case 0xaf:
861d2107	311	nv_wr32(priv, 0x100c90, 0x089d1fff);
304424e1 MK	312	break;
304424e1 MK	313	default:
861d2107	314	nv_wr32(priv, 0x100c90, 0x001d07ff);
304424e1 MK	315	break;
	316	}
	317
	318	return 0;
	319	}
	320
861d2107 BS	321	struct nouveau_oclass
	322	nv50_fb_oclass = {
	323	.handle = NV_SUBDEV(FB, 0x50),
	324	.ofuncs = &(struct nouveau_ofuncs) {
	325	.ctor = nv50_fb_ctor,
	326	.dtor = nv50_fb_dtor,
	327	.init = nv50_fb_init,
	328	.fini = _nouveau_fb_fini,
	329	},
	330	};
d96773e7	331
e6626254	332	static const struct nouveau_enum vm_dispatch_subclients[] = {
312d1d5f BS	333	{ 0x00000000, "GRCTX", NULL },
	334	{ 0x00000001, "NOTIFY", NULL },
	335	{ 0x00000002, "QUERY", NULL },
	336	{ 0x00000003, "COND", NULL },
	337	{ 0x00000004, "M2M_IN", NULL },
	338	{ 0x00000005, "M2M_OUT", NULL },
	339	{ 0x00000006, "M2M_NOTIFY", NULL },
	340	{}
	341	};
	342
e6626254	343	static const struct nouveau_enum vm_ccache_subclients[] = {
312d1d5f BS	344	{ 0x00000000, "CB", NULL },
	345	{ 0x00000001, "TIC", NULL },
	346	{ 0x00000002, "TSC", NULL },
	347	{}
	348	};
	349
e6626254	350	static const struct nouveau_enum vm_prop_subclients[] = {
312d1d5f BS	351	{ 0x00000000, "RT0", NULL },
	352	{ 0x00000001, "RT1", NULL },
	353	{ 0x00000002, "RT2", NULL },
	354	{ 0x00000003, "RT3", NULL },
	355	{ 0x00000004, "RT4", NULL },
	356	{ 0x00000005, "RT5", NULL },
	357	{ 0x00000006, "RT6", NULL },
	358	{ 0x00000007, "RT7", NULL },
	359	{ 0x00000008, "ZETA", NULL },
	360	{ 0x00000009, "LOCAL", NULL },
	361	{ 0x0000000a, "GLOBAL", NULL },
	362	{ 0x0000000b, "STACK", NULL },
	363	{ 0x0000000c, "DST2D", NULL },
	364	{}
	365	};
	366
e6626254	367	static const struct nouveau_enum vm_pfifo_subclients[] = {
312d1d5f BS	368	{ 0x00000000, "PUSHBUF", NULL },
	369	{ 0x00000001, "SEMAPHORE", NULL },
	370	{}
	371	};
	372
e6626254	373	static const struct nouveau_enum vm_bar_subclients[] = {
312d1d5f BS	374	{ 0x00000000, "FB", NULL },
	375	{ 0x00000001, "IN", NULL },
	376	{}
	377	};
	378
e6626254	379	static const struct nouveau_enum vm_client[] = {
312d1d5f BS	380	{ 0x00000000, "STRMOUT", NULL },
	381	{ 0x00000003, "DISPATCH", vm_dispatch_subclients },
	382	{ 0x00000004, "PFIFO_WRITE", NULL },
	383	{ 0x00000005, "CCACHE", vm_ccache_subclients },
	384	{ 0x00000006, "PPPP", NULL },
	385	{ 0x00000007, "CLIPID", NULL },
	386	{ 0x00000008, "PFIFO_READ", NULL },
	387	{ 0x00000009, "VFETCH", NULL },
	388	{ 0x0000000a, "TEXTURE", NULL },
	389	{ 0x0000000b, "PROP", vm_prop_subclients },
	390	{ 0x0000000c, "PVP", NULL },
	391	{ 0x0000000d, "PBSP", NULL },
	392	{ 0x0000000e, "PCRYPT", NULL },
	393	{ 0x0000000f, "PCOUNTER", NULL },
	394	{ 0x00000011, "PDAEMON", NULL },
	395	{}
	396	};
	397
e6626254	398	static const struct nouveau_enum vm_engine[] = {
312d1d5f BS	399	{ 0x00000000, "PGRAPH", NULL },
	400	{ 0x00000001, "PVP", NULL },
	401	{ 0x00000004, "PEEPHOLE", NULL },
	402	{ 0x00000005, "PFIFO", vm_pfifo_subclients },
	403	{ 0x00000006, "BAR", vm_bar_subclients },
	404	{ 0x00000008, "PPPP", NULL },
	405	{ 0x00000009, "PBSP", NULL },
	406	{ 0x0000000a, "PCRYPT", NULL },
	407	{ 0x0000000b, "PCOUNTER", NULL },
	408	{ 0x0000000c, "SEMAPHORE_BG", NULL },
	409	{ 0x0000000d, "PCOPY", NULL },
	410	{ 0x0000000e, "PDAEMON", NULL },
	411	{}
	412	};
	413
e6626254	414	static const struct nouveau_enum vm_fault[] = {
312d1d5f BS	415	{ 0x00000000, "PT_NOT_PRESENT", NULL },
	416	{ 0x00000001, "PT_TOO_SHORT", NULL },
	417	{ 0x00000002, "PAGE_NOT_PRESENT", NULL },
	418	{ 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
	419	{ 0x00000004, "PAGE_READ_ONLY", NULL },
	420	{ 0x00000006, "NULL_DMAOBJ", NULL },
	421	{ 0x00000007, "WRONG_MEMTYPE", NULL },
	422	{ 0x0000000b, "VRAM_LIMIT", NULL },
	423	{ 0x0000000f, "DMAOBJ_LIMIT", NULL },
	424	{}
	425	};
	426
d96773e7	427	void
861d2107	428	nv50_fb_trap(struct nouveau_fb *pfb, int display)
d96773e7	429	{
861d2107 BS	430	struct nouveau_device *device = nv_device(pfb);
861d2107 BS	431	struct nv50_fb_priv priv = (void )pfb;
312d1d5f	432	const struct nouveau_enum en, cl;
861d2107	433	u32 trap[6], idx, chan;
312d1d5f	434	u8 st0, st1, st2, st3;
861d2107	435	int i;
d96773e7	436
861d2107	437	idx = nv_rd32(priv, 0x100c90);
d96773e7 BS	438	if (!(idx & 0x80000000))
	439	return;
	440	idx &= 0x00ffffff;
	441
	442	for (i = 0; i < 6; i++) {
861d2107 BS	443	nv_wr32(priv, 0x100c90, idx \| i << 24);
861d2107 BS	444	trap[i] = nv_rd32(priv, 0x100c94);
d96773e7	445	}
861d2107	446	nv_wr32(priv, 0x100c90, idx \| 0x80000000);
d96773e7 BS	447
	448	if (!display)
	449	return;
	450
312d1d5f	451	/* decode status bits into something more useful */
861d2107 BS	452	if (device->chipset < 0xa3 \|\|
861d2107 BS	453	device->chipset == 0xaa \|\| device->chipset == 0xac) {
312d1d5f BS	454	st0 = (trap[0] & 0x0000000f) >> 0;
	455	st1 = (trap[0] & 0x000000f0) >> 4;
	456	st2 = (trap[0] & 0x00000f00) >> 8;
	457	st3 = (trap[0] & 0x0000f000) >> 12;
	458	} else {
	459	st0 = (trap[0] & 0x000000ff) >> 0;
	460	st1 = (trap[0] & 0x0000ff00) >> 8;
	461	st2 = (trap[0] & 0x00ff0000) >> 16;
	462	st3 = (trap[0] & 0xff000000) >> 24;
	463	}
861d2107	464	chan = (trap[2] << 16) \| trap[1];
312d1d5f	465
861d2107 BS	466	nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x ",
	467	(trap[5] & 0x00000100) ? "read" : "write",
	468	trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan);
312d1d5f BS	469
	470	en = nouveau_enum_find(vm_engine, st0);
	471	if (en)
	472	printk("%s/", en->name);
	473	else
	474	printk("%02x/", st0);
	475
	476	cl = nouveau_enum_find(vm_client, st2);
	477	if (cl)
	478	printk("%s/", cl->name);
	479	else
	480	printk("%02x/", st2);
	481
	482	if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
	483	else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
	484	else cl = NULL;
	485	if (cl)
	486	printk("%s", cl->name);
	487	else
	488	printk("%02x", st3);
	489
	490	printk(" reason: ");
	491	en = nouveau_enum_find(vm_fault, st1);
	492	if (en)
	493	printk("%s\n", en->name);
	494	else
	495	printk("0x%08x\n", st1);
d96773e7	496	}