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UBUNTU: Ubuntu-4.10.0-37.41
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / nouveau / dispnv04 / crtc.c
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6ee73861
BS		 1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
5addcf0a 25#include <linux/pm_runtime.h>
6ee73861 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
3cb9ae4f 29#include <drm/drm_plane_helper.h>
6ee73861 30
4dc28134 31#include "nouveau_drv.h"
77145f1c 32#include "nouveau_reg.h"
4dc28134 33#include "nouveau_ttm.h"
77145f1c
BS		 34#include "nouveau_bo.h"
35#include "nouveau_gem.h"
6ee73861
BS		 36#include "nouveau_encoder.h"
37#include "nouveau_connector.h"
38#include "nouveau_crtc.h"
1a646342 39#include "hw.h"
6ee73861 40#include "nvreg.h"
a424d761 41#include "nouveau_fbcon.h"
1a646342 42#include "disp.h"
77145f1c
BS		 43
44#include <subdev/bios/pll.h>
f3867f43 45#include <subdev/clk.h>
6ee73861
BS		 46
47static int
48nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
49 struct drm_framebuffer *old_fb);
50
51static void
52crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
53{
54 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
55 crtcstate->CRTC[index]);
56}
57
58static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
59{
60 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 61 struct drm_device *dev = crtc->dev;
62 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 63
64 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
65 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
66 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
67 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
69 }
70 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
71}
72
73static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
74{
75 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 76 struct drm_device *dev = crtc->dev;
77 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 78
79 nv_crtc->sharpness = level;
80 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
81 level += 0x40;
82 regp->ramdac_634 = level;
83 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
84}
85
86#define PLLSEL_VPLL1_MASK \
87 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
88 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
89#define PLLSEL_VPLL2_MASK \
90 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
91 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
92#define PLLSEL_TV_MASK \
93 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
95 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
96 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
97
98/* NV4x 0x40.. pll notes:
99 * gpu pll: 0x4000 + 0x4004
100 * ?gpu? pll: 0x4008 + 0x400c
101 * vpll1: 0x4010 + 0x4014
102 * vpll2: 0x4018 + 0x401c
103 * mpll: 0x4020 + 0x4024
104 * mpll: 0x4038 + 0x403c
105 *
106 * the first register of each pair has some unknown details:
107 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
108 * bits 20-23: (mpll) something to do with post divider?
109 * bits 28-31: related to single stage mode? (bit 8/12)
110 */
111
112static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
113{
114 struct drm_device *dev = crtc->dev;
77145f1c 115 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e
BS		 116 struct nvkm_bios *bios = nvxx_bios(&drm->device);
117 struct nvkm_clk *clk = nvxx_clk(&drm->device);
6ee73861 118 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 119 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861 120 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
be83cd4e 121 struct nvkm_pll_vals *pv = &regp->pllvals;
70790f4f 122 struct nvbios_pll pll_lim;
6ee73861 123
77145f1c
BS		 124 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
125 &pll_lim))
6ee73861
BS		 126 return;
127
128 /* NM2 == 0 is used to determine single stage mode on two stage plls */
129 pv->NM2 = 0;
130
131 /* for newer nv4x the blob uses only the first stage of the vpll below a
132 * certain clock. for a certain nv4b this is 150MHz. since the max
133 * output frequency of the first stage for this card is 300MHz, it is
134 * assumed the threshold is given by vco1 maxfreq/2
135 */
136 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
137 * not 8, others unknown), the blob always uses both plls. no problem
138 * has yet been observed in allowing the use a single stage pll on all
139 * nv43 however. the behaviour of single stage use is untested on nv40
140 */
967e7bde 141 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
6ee73861
BS		 142 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
143
77145f1c
BS		 144
145 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
6ee73861
BS		 146 return;
147
148 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
149
150 /* The blob uses this always, so let's do the same */
967e7bde 151 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 152 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
153 /* again nv40 and some nv43 act more like nv3x as described above */
967e7bde 154 if (drm->device.info.chipset < 0x41)
6ee73861
BS		 155 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
156 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
157 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
158
159 if (pv->NM2)
77145f1c 160 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
6ee73861
BS		 161 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
162 else
77145f1c 163 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
6ee73861
BS		 164 pv->N1, pv->M1, pv->log2P);
165
166 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
167}
168
169static void
170nv_crtc_dpms(struct drm_crtc *crtc, int mode)
171{
172 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
173 struct drm_device *dev = crtc->dev;
77145f1c 174 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861
BS		 175 unsigned char seq1 = 0, crtc17 = 0;
176 unsigned char crtc1A;
177
77145f1c 178 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
6ee73861
BS		 179 nv_crtc->index);
180
25985edc 181 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
6ee73861
BS		 182 return;
183
184 nv_crtc->last_dpms = mode;
185
186 if (nv_two_heads(dev))
187 NVSetOwner(dev, nv_crtc->index);
188
189 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
190 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
191 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
192 switch (mode) {
193 case DRM_MODE_DPMS_STANDBY:
194 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
195 seq1 = 0x20;
196 crtc17 = 0x80;
197 crtc1A |= 0x80;
198 break;
199 case DRM_MODE_DPMS_SUSPEND:
200 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
201 seq1 = 0x20;
202 crtc17 = 0x80;
203 crtc1A |= 0x40;
204 break;
205 case DRM_MODE_DPMS_OFF:
206 /* Screen: Off; HSync: Off, VSync: Off */
207 seq1 = 0x20;
208 crtc17 = 0x00;
209 crtc1A |= 0xC0;
210 break;
211 case DRM_MODE_DPMS_ON:
212 default:
213 /* Screen: On; HSync: On, VSync: On */
214 seq1 = 0x00;
215 crtc17 = 0x80;
216 break;
217 }
218
219 NVVgaSeqReset(dev, nv_crtc->index, true);
220 /* Each head has it's own sequencer, so we can turn it off when we want */
221 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
222 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
223 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
224 mdelay(10);
225 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
226 NVVgaSeqReset(dev, nv_crtc->index, false);
227
228 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
229}
230
6ee73861
BS		 231static void
232nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
233{
234 struct drm_device *dev = crtc->dev;
6ee73861 235 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 236 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
f4510a27 237 struct drm_framebuffer *fb = crtc->primary->fb;
6ee73861
BS		 238
239 /* Calculate our timings */
e5ec882c
FJ		 240 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
241 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
242 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
6ee73861
BS		 243 int horizTotal = (mode->crtc_htotal >> 3) - 5;
244 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
245 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
246 int vertDisplay = mode->crtc_vdisplay - 1;
247 int vertStart = mode->crtc_vsync_start - 1;
248 int vertEnd = mode->crtc_vsync_end - 1;
249 int vertTotal = mode->crtc_vtotal - 2;
250 int vertBlankStart = mode->crtc_vdisplay - 1;
251 int vertBlankEnd = mode->crtc_vtotal - 1;
252
253 struct drm_encoder *encoder;
254 bool fp_output = false;
255
256 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
257 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
258
259 if (encoder->crtc == crtc &&
cb75d97e
BS		 260 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
261 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
6ee73861
BS		 262 fp_output = true;
263 }
264
265 if (fp_output) {
266 vertStart = vertTotal - 3;
267 vertEnd = vertTotal - 2;
268 vertBlankStart = vertStart;
269 horizStart = horizTotal - 5;
270 horizEnd = horizTotal - 2;
271 horizBlankEnd = horizTotal + 4;
272#if 0
967e7bde 273 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 274 /* This reportedly works around some video overlay bandwidth problems */
275 horizTotal += 2;
276#endif
277 }
278
279 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
280 vertTotal |= 1;
281
282#if 0
283 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
284 ErrorF("horizStart: 0x%X \n", horizStart);
285 ErrorF("horizEnd: 0x%X \n", horizEnd);
286 ErrorF("horizTotal: 0x%X \n", horizTotal);
287 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
288 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
289 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
290 ErrorF("vertStart: 0x%X \n", vertStart);
291 ErrorF("vertEnd: 0x%X \n", vertEnd);
292 ErrorF("vertTotal: 0x%X \n", vertTotal);
293 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
294 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
295#endif
296
297 /*
298 * compute correct Hsync & Vsync polarity
299 */
300 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
301 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
302
303 regp->MiscOutReg = 0x23;
304 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
305 regp->MiscOutReg |= 0x40;
306 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
307 regp->MiscOutReg |= 0x80;
308 } else {
309 int vdisplay = mode->vdisplay;
310 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
311 vdisplay *= 2;
312 if (mode->vscan > 1)
313 vdisplay *= mode->vscan;
314 if (vdisplay < 400)
315 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
316 else if (vdisplay < 480)
317 regp->MiscOutReg = 0x63; /* -hsync +vsync */
318 else if (vdisplay < 768)
319 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
320 else
321 regp->MiscOutReg = 0x23; /* +hsync +vsync */
322 }
323
6ee73861
BS		 324 /*
325 * Time Sequencer
326 */
327 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
328 /* 0x20 disables the sequencer */
329 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
330 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
331 else
332 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
333 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
334 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
335 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
336
337 /*
338 * CRTC
339 */
340 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
341 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
342 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
343 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
344 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
345 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
346 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
347 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
348 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
349 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
350 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
351 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
352 (1 << 4) |
353 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
354 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
355 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
356 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
357 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
359 1 << 6 |
360 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
361 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
364 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
365 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
366 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
368 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
369 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
370 /* framebuffer can be larger than crtc scanout area. */
01f2c773 371 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
6ee73861
BS		 372 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
373 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
374 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
375 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
376 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
377
378 /*
379 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
380 */
381
382 /* framebuffer can be larger than crtc scanout area. */
c1003d9c 383 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 384 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 385 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 386 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 387 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
388 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
389 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
390 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
391 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
392 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
393 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
394 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
395 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
396 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
397 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
398 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
399 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
400 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
401 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
402
403 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
404 horizTotal = (horizTotal >> 1) & ~1;
405 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
406 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
407 } else
408 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
409
410 /*
411 * Graphics Display Controller
412 */
413 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
414 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
415 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
416 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
417 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
418 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
419 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
420 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
421 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
422
423 regp->Attribute[0] = 0x00; /* standard colormap translation */
424 regp->Attribute[1] = 0x01;
425 regp->Attribute[2] = 0x02;
426 regp->Attribute[3] = 0x03;
427 regp->Attribute[4] = 0x04;
428 regp->Attribute[5] = 0x05;
429 regp->Attribute[6] = 0x06;
430 regp->Attribute[7] = 0x07;
431 regp->Attribute[8] = 0x08;
432 regp->Attribute[9] = 0x09;
433 regp->Attribute[10] = 0x0A;
434 regp->Attribute[11] = 0x0B;
435 regp->Attribute[12] = 0x0C;
436 regp->Attribute[13] = 0x0D;
437 regp->Attribute[14] = 0x0E;
438 regp->Attribute[15] = 0x0F;
439 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
440 /* Non-vga */
441 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
442 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
443 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
444 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
445}
446
447/**
448 * Sets up registers for the given mode/adjusted_mode pair.
449 *
450 * The clocks, CRTCs and outputs attached to this CRTC must be off.
451 *
452 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
453 * be easily turned on/off after this.
454 */
455static void
456nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
457{
458 struct drm_device *dev = crtc->dev;
77145f1c 459 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 460 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 461 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
462 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 463 struct drm_encoder *encoder;
464 bool lvds_output = false, tmds_output = false, tv_output = false,
465 off_chip_digital = false;
466
467 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
468 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
469 bool digital = false;
470
471 if (encoder->crtc != crtc)
472 continue;
473
cb75d97e 474 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
6ee73861 475 digital = lvds_output = true;
cb75d97e 476 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
6ee73861 477 tv_output = true;
cb75d97e 478 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
6ee73861
BS		 479 digital = tmds_output = true;
480 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
481 off_chip_digital = true;
482 }
483
484 /* Registers not directly related to the (s)vga mode */
485
486 /* What is the meaning of this register? */
487 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
488 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
489
490 regp->crtc_eng_ctrl = 0;
491 /* Except for rare conditions I2C is enabled on the primary crtc */
492 if (nv_crtc->index == 0)
493 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
494#if 0
495 /* Set overlay to desired crtc. */
496 if (dev->overlayAdaptor) {
497 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
498 if (pPriv->overlayCRTC == nv_crtc->index)
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
500 }
501#endif
502
503 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
504 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
505 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
506 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
967e7bde 507 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 508 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
509 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
510 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
511
512 /* Unblock some timings */
513 regp->CRTC[NV_CIO_CRE_53] = 0;
514 regp->CRTC[NV_CIO_CRE_54] = 0;
515
516 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
517 if (lvds_output)
518 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
519 else if (tmds_output)
520 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
521 else
522 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
523
524 /* These values seem to vary */
525 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
526 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
527
528 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
529
530 /* probably a scratch reg, but kept for cargo-cult purposes:
531 * bit0: crtc0?, head A
532 * bit6: lvds, head A
533 * bit7: (only in X), head A
534 */
535 if (nv_crtc->index == 0)
536 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
537
538 /* The blob seems to take the current value from crtc 0, add 4 to that
539 * and reuse the old value for crtc 1 */
017e6e29 540 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
6ee73861
BS		 541 if (!nv_crtc->index)
542 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
543
544 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
545 * 1 << 30 on 0x60.830), for no apparent reason */
546 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
547
967e7bde 548 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
4a9f822f
FJ		 549 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
550
6ee73861
BS		 551 regp->crtc_830 = mode->crtc_vdisplay - 3;
552 regp->crtc_834 = mode->crtc_vdisplay - 1;
553
967e7bde 554 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 555 /* This is what the blob does */
556 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
557
967e7bde 558 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
6ee73861
BS		 559 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
560
967e7bde 561 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
63f7fcfe
FJ		 562 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
563 else
564 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
6ee73861
BS		 565
566 /* Some misc regs */
967e7bde 567 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 568 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
569 regp->CRTC[NV_CIO_CRE_86] = 0x1;
570 }
571
f4510a27 572 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;
6ee73861
BS		 573 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
574 if (lvds_output || tmds_output || tv_output)
575 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
576
577 /* Generic PRAMDAC regs */
578
967e7bde 579 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 580 /* Only bit that bios and blob set. */
581 regp->nv10_cursync = (1 << 25);
582
583 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
584 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
585 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
f4510a27 586 if (crtc->primary->fb->depth == 16)
6ee73861 587 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
967e7bde 588 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 589 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
590
591 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
592 regp->tv_setup = 0;
593
594 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
595
596 /* Some values the blob sets */
597 regp->ramdac_8c0 = 0x100;
598 regp->ramdac_a20 = 0x0;
599 regp->ramdac_a24 = 0xfffff;
600 regp->ramdac_a34 = 0x1;
601}
602
78ae0ad4
BS		 603static int
604nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
605{
606 struct nv04_display *disp = nv04_display(crtc->dev);
f4510a27 607 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
78ae0ad4
BS		 608 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
609 int ret;
610
ad76b3f7 611 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false);
78ae0ad4
BS		 612 if (ret == 0) {
613 if (disp->image[nv_crtc->index])
614 nouveau_bo_unpin(disp->image[nv_crtc->index]);
615 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);
616 }
617
618 return ret;
619}
620
6ee73861
BS		 621/**
622 * Sets up registers for the given mode/adjusted_mode pair.
623 *
624 * The clocks, CRTCs and outputs attached to this CRTC must be off.
625 *
626 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
627 * be easily turned on/off after this.
628 */
629static int
630nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
631 struct drm_display_mode *adjusted_mode,
632 int x, int y, struct drm_framebuffer *old_fb)
633{
634 struct drm_device *dev = crtc->dev;
635 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
77145f1c 636 struct nouveau_drm *drm = nouveau_drm(dev);
78ae0ad4 637 int ret;
6ee73861 638
77145f1c 639 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 640 drm_mode_debug_printmodeline(adjusted_mode);
641
78ae0ad4
BS		 642 ret = nv_crtc_swap_fbs(crtc, old_fb);
643 if (ret)
644 return ret;
645
6ee73861
BS		 646 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
647 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
648
649 nv_crtc_mode_set_vga(crtc, adjusted_mode);
650 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
967e7bde 651 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
017e6e29 652 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
6ee73861
BS		 653 nv_crtc_mode_set_regs(crtc, adjusted_mode);
654 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
655 return 0;
656}
657
658static void nv_crtc_save(struct drm_crtc *crtc)
659{
660 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 661 struct drm_device *dev = crtc->dev;
662 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861 663 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
017e6e29 664 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
6ee73861
BS		 665 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
666
667 if (nv_two_heads(crtc->dev))
668 NVSetOwner(crtc->dev, nv_crtc->index);
669
670 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
671
672 /* init some state to saved value */
673 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
674 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
675 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
676 crtc_state->gpio_ext = crtc_saved->gpio_ext;
677}
678
679static void nv_crtc_restore(struct drm_crtc *crtc)
680{
681 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 682 struct drm_device *dev = crtc->dev;
6ee73861 683 int head = nv_crtc->index;
017e6e29 684 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
6ee73861
BS		 685
686 if (nv_two_heads(crtc->dev))
687 NVSetOwner(crtc->dev, head);
688
017e6e29 689 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
6ee73861
BS		 690 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
691
692 nv_crtc->last_dpms = NV_DPMS_CLEARED;
693}
694
695static void nv_crtc_prepare(struct drm_crtc *crtc)
696{
697 struct drm_device *dev = crtc->dev;
77145f1c 698 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 699 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
d58ded76 700 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
6ee73861
BS		 701
702 if (nv_two_heads(dev))
703 NVSetOwner(dev, nv_crtc->index);
704
9bc6db0d 705 drm_crtc_vblank_off(crtc);
6ee73861
BS		 706 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
707
708 NVBlankScreen(dev, nv_crtc->index, true);
709
25985edc 710 /* Some more preparation. */
6ee73861 711 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
967e7bde 712 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 713 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
714 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
715 }
716}
717
718static void nv_crtc_commit(struct drm_crtc *crtc)
719{
720 struct drm_device *dev = crtc->dev;
d58ded76 721 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
6ee73861
BS		 722 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
723
017e6e29 724 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 725 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
726
727#ifdef __BIG_ENDIAN
728 /* turn on LFB swapping */
729 {
730 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
731 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
732 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
733 }
734#endif
735
736 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
9bc6db0d 737 drm_crtc_vblank_on(crtc);
6ee73861
BS		 738}
739
740static void nv_crtc_destroy(struct drm_crtc *crtc)
741{
78ae0ad4 742 struct nv04_display *disp = nv04_display(crtc->dev);
6ee73861
BS		 743 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
744
6ee73861
BS		 745 if (!nv_crtc)
746 return;
747
748 drm_crtc_cleanup(crtc);
749
78ae0ad4
BS		 750 if (disp->image[nv_crtc->index])
751 nouveau_bo_unpin(disp->image[nv_crtc->index]);
752 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
753
9d59e8a1 754 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210 755 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
6ee73861
BS		 756 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
757 kfree(nv_crtc);
758}
759
760static void
761nv_crtc_gamma_load(struct drm_crtc *crtc)
762{
763 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
764 struct drm_device *dev = nv_crtc->base.dev;
6ee73861
BS		 765 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
766 int i;
767
017e6e29 768 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
6ee73861
BS		 769 for (i = 0; i < 256; i++) {
770 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
771 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
772 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
773 }
774
017e6e29 775 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 776}
777
78ae0ad4
BS		 778static void
779nv_crtc_disable(struct drm_crtc *crtc)
780{
781 struct nv04_display *disp = nv04_display(crtc->dev);
782 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
783 if (disp->image[nv_crtc->index])
784 nouveau_bo_unpin(disp->image[nv_crtc->index]);
785 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
786}
787
7ea77283
ML		 788static int
789nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
7203425a 790 uint32_t size)
6ee73861
BS		 791{
792 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
7ea77283 793 int i;
6ee73861 794
7ea77283 795 for (i = 0; i < size; i++) {
6ee73861
BS		 796 nv_crtc->lut.r[i] = r[i];
797 nv_crtc->lut.g[i] = g[i];
798 nv_crtc->lut.b[i] = b[i];
799 }
800
801 /* We need to know the depth before we upload, but it's possible to
802 * get called before a framebuffer is bound. If this is the case,
803 * mark the lut values as dirty by setting depth==0, and it'll be
804 * uploaded on the first mode_set_base()
805 */
f4510a27 806 if (!nv_crtc->base.primary->fb) {
6ee73861 807 nv_crtc->lut.depth = 0;
7ea77283 808 return 0;
6ee73861
BS		 809 }
810
811 nv_crtc_gamma_load(crtc);
7ea77283
ML		 812
813 return 0;
6ee73861
BS		 814}
815
816static int
be64c2bb
CB		 817nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
818 struct drm_framebuffer *passed_fb,
819 int x, int y, bool atomic)
6ee73861
BS		 820{
821 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
822 struct drm_device *dev = crtc->dev;
77145f1c 823 struct nouveau_drm *drm = nouveau_drm(dev);
017e6e29 824 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0e83bb4e
EV		 825 struct drm_framebuffer *drm_fb;
826 struct nouveau_framebuffer *fb;
6ee73861 827 int arb_burst, arb_lwm;
6ee73861 828
77145f1c 829 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
0e83bb4e
EV		 830
831 /* no fb bound */
f4510a27 832 if (!atomic && !crtc->primary->fb) {
77145f1c 833 NV_DEBUG(drm, "No FB bound\n");
0e83bb4e
EV		 834 return 0;
835 }
836
be64c2bb 837 /* If atomic, we want to switch to the fb we were passed, so
78ae0ad4 838 * now we update pointers to do that.
be64c2bb
CB		 839 */
840 if (atomic) {
841 drm_fb = passed_fb;
842 fb = nouveau_framebuffer(passed_fb);
f9ec8f6c 843 } else {
f4510a27
MR		 844 drm_fb = crtc->primary->fb;
845 fb = nouveau_framebuffer(crtc->primary->fb);
6ee73861
BS		 846 }
847
848 nv_crtc->fb.offset = fb->nvbo->bo.offset;
849
850 if (nv_crtc->lut.depth != drm_fb->depth) {
851 nv_crtc->lut.depth = drm_fb->depth;
852 nv_crtc_gamma_load(crtc);
853 }
854
855 /* Update the framebuffer format. */
856 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
f4510a27 857 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8;
6ee73861 858 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
f4510a27 859 if (crtc->primary->fb->depth == 16)
6ee73861
BS		 860 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
861 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
862 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
863 regp->ramdac_gen_ctrl);
864
01f2c773 865 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
6ee73861 866 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 867 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 868 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 869 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 870 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
871 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
c1003d9c 872 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
6ee73861
BS		 873
874 /* Update the framebuffer location. */
875 regp->fb_start = nv_crtc->fb.offset & ~3;
01f2c773 876 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
5794b5fd 877 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
6ee73861
BS		 878
879 /* Update the arbitration parameters. */
880 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
881 &arb_burst, &arb_lwm);
882
883 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
884 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
885 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
886 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
887
967e7bde 888 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
6ee73861
BS		 889 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
891 }
892
893 return 0;
894}
895
be64c2bb
CB		 896static int
897nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
898 struct drm_framebuffer *old_fb)
899{
78ae0ad4
BS		 900 int ret = nv_crtc_swap_fbs(crtc, old_fb);
901 if (ret)
902 return ret;
be64c2bb
CB		 903 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
904}
905
906static int
907nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
908 struct drm_framebuffer *fb,
21c74a8e 909 int x, int y, enum mode_set_atomic state)
be64c2bb 910{
77145f1c
BS		 911 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
912 struct drm_device *dev = drm->dev;
a424d761 913
21c74a8e 914 if (state == ENTER_ATOMIC_MODE_SET)
4b5098f3 915 nouveau_fbcon_accel_save_disable(dev);
a424d761 916 else
4b5098f3 917 nouveau_fbcon_accel_restore(dev);
a424d761 918
be64c2bb
CB		 919 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
920}
921
6ee73861
BS		 922static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
923 struct nouveau_bo *dst)
924{
925 int width = nv_cursor_width(dev);
926 uint32_t pixel;
927 int i, j;
928
929 for (i = 0; i < width; i++) {
930 for (j = 0; j < width; j++) {
931 pixel = nouveau_bo_rd32(src, i*64 + j);
932
933 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
934 | (pixel & 0xf80000) >> 9
935 | (pixel & 0xf800) >> 6
936 | (pixel & 0xf8) >> 3);
937 }
938 }
939}
940
941static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
942 struct nouveau_bo *dst)
943{
944 uint32_t pixel;
945 int alpha, i;
946
947 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
948 * cursors (though NPM in combination with fp dithering may not work on
949 * nv11, from "nv" driver history)
950 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
951 * blob uses, however we get given PM cursors so we use PM mode
952 */
953 for (i = 0; i < 64 * 64; i++) {
954 pixel = nouveau_bo_rd32(src, i);
955
956 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
957 * than" shouldn't happen; fix "equal to" case by adding one to
958 * alpha channel (slightly inaccurate, but so is attempting to
959 * get back to NPM images, due to limits of integer precision)
960 */
961 alpha = pixel >> 24;
962 if (alpha > 0 && alpha < 255)
963 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
964
965#ifdef __BIG_ENDIAN
966 {
77145f1c 967 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 968
967e7bde 969 if (drm->device.info.chipset == 0x11) {
6ee73861
BS		 970 pixel = ((pixel & 0x000000ff) << 24) |
971 ((pixel & 0x0000ff00) << 8) |
972 ((pixel & 0x00ff0000) >> 8) |
973 ((pixel & 0xff000000) >> 24);
974 }
975 }
976#endif
977
978 nouveau_bo_wr32(dst, i, pixel);
979 }
980}
981
982static int
983nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
984 uint32_t buffer_handle, uint32_t width, uint32_t height)
985{
77145f1c
BS		 986 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
987 struct drm_device *dev = drm->dev;
6ee73861
BS		 988 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
989 struct nouveau_bo *cursor = NULL;
990 struct drm_gem_object *gem;
991 int ret = 0;
992
6ee73861
BS		 993 if (!buffer_handle) {
994 nv_crtc->cursor.hide(nv_crtc, true);
995 return 0;
996 }
997
b4fa9d0f
MS		 998 if (width != 64 || height != 64)
999 return -EINVAL;
1000
a8ad0bd8 1001 gem = drm_gem_object_lookup(file_priv, buffer_handle);
6ee73861 1002 if (!gem)
bf79cb91 1003 return -ENOENT;
6ee73861
BS		 1004 cursor = nouveau_gem_object(gem);
1005
1006 ret = nouveau_bo_map(cursor);
1007 if (ret)
1008 goto out;
1009
967e7bde 1010 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 1011 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1012 else
1013 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1014
1015 nouveau_bo_unmap(cursor);
1016 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1017 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1018 nv_crtc->cursor.show(nv_crtc, true);
1019out:
bc9025bd 1020 drm_gem_object_unreference_unlocked(gem);
6ee73861
BS		 1021 return ret;
1022}
1023
1024static int
1025nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1026{
1027 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1028
1029 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1030 return 0;
1031}
1032
5addcf0a
DA		 1033int
1034nouveau_crtc_set_config(struct drm_mode_set *set)
1035{
1036 struct drm_device *dev;
1037 struct nouveau_drm *drm;
1038 int ret;
1039 struct drm_crtc *crtc;
1040 bool active = false;
1041 if (!set || !set->crtc)
1042 return -EINVAL;
1043
1044 dev = set->crtc->dev;
1045
1046 /* get a pm reference here */
1047 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 1048 if (ret < 0 && ret != -EACCES)
5addcf0a
DA		 1049 return ret;
1050
1051 ret = drm_crtc_helper_set_config(set);
1052
1053 drm = nouveau_drm(dev);
1054
1055 /* if we get here with no crtcs active then we can drop a reference */
1056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1057 if (crtc->enabled)
1058 active = true;
1059 }
1060
1061 pm_runtime_mark_last_busy(dev->dev);
1062 /* if we have active crtcs and we don't have a power ref,
1063 take the current one */
1064 if (active && !drm->have_disp_power_ref) {
1065 drm->have_disp_power_ref = true;
1066 return ret;
1067 }
1068 /* if we have no active crtcs, then drop the power ref
1069 we got before */
1070 if (!active && drm->have_disp_power_ref) {
1071 pm_runtime_put_autosuspend(dev->dev);
1072 drm->have_disp_power_ref = false;
1073 }
1074 /* drop the power reference we got coming in here */
1075 pm_runtime_put_autosuspend(dev->dev);
1076 return ret;
1077}
1078
6ee73861 1079static const struct drm_crtc_funcs nv04_crtc_funcs = {
6ee73861
BS		 1080 .cursor_set = nv04_crtc_cursor_set,
1081 .cursor_move = nv04_crtc_cursor_move,
1082 .gamma_set = nv_crtc_gamma_set,
5addcf0a 1083 .set_config = nouveau_crtc_set_config,
332b242f 1084 .page_flip = nouveau_crtc_page_flip,
6ee73861
BS		 1085 .destroy = nv_crtc_destroy,
1086};
1087
1088static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1089 .dpms = nv_crtc_dpms,
1090 .prepare = nv_crtc_prepare,
1091 .commit = nv_crtc_commit,
6ee73861
BS		 1092 .mode_set = nv_crtc_mode_set,
1093 .mode_set_base = nv04_crtc_mode_set_base,
be64c2bb 1094 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
6ee73861 1095 .load_lut = nv_crtc_gamma_load,
78ae0ad4 1096 .disable = nv_crtc_disable,
6ee73861
BS		 1097};
1098
1099int
1100nv04_crtc_create(struct drm_device *dev, int crtc_num)
1101{
1102 struct nouveau_crtc *nv_crtc;
1103 int ret, i;
1104
1105 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1106 if (!nv_crtc)
1107 return -ENOMEM;
1108
1109 for (i = 0; i < 256; i++) {
1110 nv_crtc->lut.r[i] = i << 8;
1111 nv_crtc->lut.g[i] = i << 8;
1112 nv_crtc->lut.b[i] = i << 8;
1113 }
1114 nv_crtc->lut.depth = 0;
1115
1116 nv_crtc->index = crtc_num;
1117 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1118
2c3d7715
DV		 1119 nv_crtc->save = nv_crtc_save;
1120 nv_crtc->restore = nv_crtc_restore;
1121
6ee73861
BS		 1122 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
1123 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1124 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1125
7375c95b 1126 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
bb6178b0 1127 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo);
6ee73861 1128 if (!ret) {
ad76b3f7 1129 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false);
04c8c210 1130 if (!ret) {
6ee73861 1131 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
04c8c210
MS		 1132 if (ret)
1133 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1134 }
6ee73861
BS		 1135 if (ret)
1136 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1137 }
1138
1139 nv04_cursor_init(nv_crtc);
1140
1141 return 0;
1142}
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