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6ee73861 BS |
1 | /* |
2 | * Copyright 2003 NVIDIA, Corporation | |
3 | * Copyright 2006 Dave Airlie | |
4 | * Copyright 2007 Maarten Maathuis | |
5 | * Copyright 2007-2009 Stuart Bennett | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the "Software"), | |
9 | * to deal in the Software without restriction, including without limitation | |
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
11 | * and/or sell copies of the Software, and to permit persons to whom the | |
12 | * Software is furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the next | |
15 | * paragraph) shall be included in all copies or substantial portions of the | |
16 | * Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
24 | * DEALINGS IN THE SOFTWARE. | |
25 | */ | |
26 | ||
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
6ee73861 | 29 | |
77145f1c BS |
30 | #include "nouveau_drm.h" |
31 | #include "nouveau_reg.h" | |
6ee73861 BS |
32 | #include "nouveau_encoder.h" |
33 | #include "nouveau_connector.h" | |
34 | #include "nouveau_crtc.h" | |
1a646342 | 35 | #include "hw.h" |
6ee73861 BS |
36 | #include "nvreg.h" |
37 | ||
760285e7 | 38 | #include <drm/i2c/sil164.h> |
4a9f822f | 39 | |
77145f1c BS |
40 | #include <subdev/i2c.h> |
41 | ||
6ee73861 BS |
42 | #define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \ |
43 | NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \ | |
44 | NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS) | |
45 | #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \ | |
46 | NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \ | |
47 | NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE) | |
48 | ||
49 | static inline bool is_fpc_off(uint32_t fpc) | |
50 | { | |
51 | return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) == | |
52 | FP_TG_CONTROL_OFF); | |
53 | } | |
54 | ||
cb75d97e | 55 | int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent) |
6ee73861 BS |
56 | { |
57 | /* special case of nv_read_tmds to find crtc associated with an output. | |
58 | * this does not give a correct answer for off-chip dvi, but there's no | |
59 | * use for such an answer anyway | |
60 | */ | |
cb75d97e | 61 | int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; |
6ee73861 BS |
62 | |
63 | NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL, | |
64 | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4); | |
65 | return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac; | |
66 | } | |
67 | ||
cb75d97e | 68 | void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent, |
6ee73861 BS |
69 | int head, bool dl) |
70 | { | |
71 | /* The BIOS scripts don't do this for us, sadly | |
72 | * Luckily we do know the values ;-) | |
73 | * | |
74 | * head < 0 indicates we wish to force a setting with the overrideval | |
75 | * (for VT restore etc.) | |
76 | */ | |
77 | ||
cb75d97e | 78 | int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; |
6ee73861 BS |
79 | uint8_t tmds04 = 0x80; |
80 | ||
81 | if (head != ramdac) | |
82 | tmds04 = 0x88; | |
83 | ||
cb75d97e | 84 | if (dcbent->type == DCB_OUTPUT_LVDS) |
6ee73861 BS |
85 | tmds04 |= 0x01; |
86 | ||
87 | nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); | |
88 | ||
89 | if (dl) /* dual link */ | |
90 | nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); | |
91 | } | |
92 | ||
93 | void nv04_dfp_disable(struct drm_device *dev, int head) | |
94 | { | |
017e6e29 | 95 | struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; |
6ee73861 BS |
96 | |
97 | if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) & | |
98 | FP_TG_CONTROL_ON) { | |
99 | /* digital remnants must be cleaned before new crtc | |
100 | * values programmed. delay is time for the vga stuff | |
101 | * to realise it's in control again | |
102 | */ | |
103 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, | |
104 | FP_TG_CONTROL_OFF); | |
105 | msleep(50); | |
106 | } | |
107 | /* don't inadvertently turn it on when state written later */ | |
108 | crtcstate[head].fp_control = FP_TG_CONTROL_OFF; | |
cd2fb2e9 FJ |
109 | crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= |
110 | ~NV_CIO_CRE_LCD_ROUTE_MASK; | |
6ee73861 BS |
111 | } |
112 | ||
113 | void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode) | |
114 | { | |
115 | struct drm_device *dev = encoder->dev; | |
6ee73861 BS |
116 | struct drm_crtc *crtc; |
117 | struct nouveau_crtc *nv_crtc; | |
118 | uint32_t *fpc; | |
119 | ||
120 | if (mode == DRM_MODE_DPMS_ON) { | |
121 | nv_crtc = nouveau_crtc(encoder->crtc); | |
017e6e29 | 122 | fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; |
6ee73861 BS |
123 | |
124 | if (is_fpc_off(*fpc)) { | |
125 | /* using saved value is ok, as (is_digital && dpms_on && | |
126 | * fp_control==OFF) is (at present) *only* true when | |
127 | * fpc's most recent change was by below "off" code | |
128 | */ | |
129 | *fpc = nv_crtc->dpms_saved_fp_control; | |
130 | } | |
131 | ||
132 | nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index; | |
133 | NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc); | |
134 | } else { | |
135 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
136 | nv_crtc = nouveau_crtc(crtc); | |
017e6e29 | 137 | fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; |
6ee73861 BS |
138 | |
139 | nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index); | |
140 | if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) { | |
141 | nv_crtc->dpms_saved_fp_control = *fpc; | |
142 | /* cut the FP output */ | |
143 | *fpc &= ~FP_TG_CONTROL_ON; | |
144 | *fpc |= FP_TG_CONTROL_OFF; | |
145 | NVWriteRAMDAC(dev, nv_crtc->index, | |
146 | NV_PRAMDAC_FP_TG_CONTROL, *fpc); | |
147 | } | |
148 | } | |
149 | } | |
150 | } | |
151 | ||
2d14e35c FJ |
152 | static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder) |
153 | { | |
154 | struct drm_device *dev = encoder->dev; | |
cb75d97e | 155 | struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; |
2d14e35c FJ |
156 | struct drm_encoder *slave; |
157 | ||
cb75d97e | 158 | if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP) |
2d14e35c FJ |
159 | return NULL; |
160 | ||
161 | /* Some BIOSes (e.g. the one in a Quadro FX1000) report several | |
162 | * TMDS transmitters at the same I2C address, in the same I2C | |
163 | * bus. This can still work because in that case one of them is | |
164 | * always hard-wired to a reasonable configuration using straps, | |
165 | * and the other one needs to be programmed. | |
166 | * | |
167 | * I don't think there's a way to know which is which, even the | |
168 | * blob programs the one exposed via I2C for *both* heads, so | |
169 | * let's do the same. | |
170 | */ | |
171 | list_for_each_entry(slave, &dev->mode_config.encoder_list, head) { | |
cb75d97e | 172 | struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb; |
2d14e35c | 173 | |
cb75d97e | 174 | if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) && |
2d14e35c FJ |
175 | slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr) |
176 | return slave; | |
177 | } | |
178 | ||
179 | return NULL; | |
180 | } | |
181 | ||
6ee73861 | 182 | static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 183 | const struct drm_display_mode *mode, |
6ee73861 BS |
184 | struct drm_display_mode *adjusted_mode) |
185 | { | |
186 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
187 | struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
188 | ||
327ceae6 FJ |
189 | if (!nv_connector->native_mode || |
190 | nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || | |
191 | mode->hdisplay > nv_connector->native_mode->hdisplay || | |
192 | mode->vdisplay > nv_connector->native_mode->vdisplay) { | |
193 | nv_encoder->mode = *adjusted_mode; | |
194 | ||
195 | } else { | |
6ee73861 BS |
196 | nv_encoder->mode = *nv_connector->native_mode; |
197 | adjusted_mode->clock = nv_connector->native_mode->clock; | |
6ee73861 BS |
198 | } |
199 | ||
200 | return true; | |
201 | } | |
202 | ||
203 | static void nv04_dfp_prepare_sel_clk(struct drm_device *dev, | |
204 | struct nouveau_encoder *nv_encoder, int head) | |
205 | { | |
017e6e29 | 206 | struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; |
cb75d97e | 207 | uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000; |
6ee73861 BS |
208 | |
209 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP) | |
210 | return; | |
211 | ||
212 | /* SEL_CLK is only used on the primary ramdac | |
213 | * It toggles spread spectrum PLL output and sets the bindings of PLLs | |
214 | * to heads on digital outputs | |
215 | */ | |
216 | if (head) | |
217 | state->sel_clk |= bits1618; | |
218 | else | |
219 | state->sel_clk &= ~bits1618; | |
220 | ||
221 | /* nv30: | |
222 | * bit 0 NVClk spread spectrum on/off | |
223 | * bit 2 MemClk spread spectrum on/off | |
224 | * bit 4 PixClk1 spread spectrum on/off toggle | |
225 | * bit 6 PixClk2 spread spectrum on/off toggle | |
226 | * | |
227 | * nv40 (observations from bios behaviour and mmio traces): | |
228 | * bits 4&6 as for nv30 | |
229 | * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6; | |
230 | * maybe a different spread mode | |
231 | * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts) | |
232 | * The logic behind turning spread spectrum on/off in the first place, | |
233 | * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table | |
234 | * entry has the necessary info) | |
235 | */ | |
017e6e29 BS |
236 | if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) { |
237 | int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1; | |
6ee73861 BS |
238 | |
239 | state->sel_clk &= ~0xf0; | |
240 | state->sel_clk |= (head ? 0x40 : 0x10) << shift; | |
241 | } | |
242 | } | |
243 | ||
244 | static void nv04_dfp_prepare(struct drm_encoder *encoder) | |
245 | { | |
246 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
247 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; | |
248 | struct drm_device *dev = encoder->dev; | |
6ee73861 | 249 | int head = nouveau_crtc(encoder->crtc)->index; |
017e6e29 | 250 | struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; |
6ee73861 BS |
251 | uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; |
252 | uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; | |
253 | ||
254 | helper->dpms(encoder, DRM_MODE_DPMS_OFF); | |
255 | ||
256 | nv04_dfp_prepare_sel_clk(dev, nv_encoder, head); | |
257 | ||
cd2fb2e9 | 258 | *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3; |
217275d0 FJ |
259 | |
260 | if (nv_two_heads(dev)) { | |
261 | if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP) | |
262 | *cr_lcd |= head ? 0x0 : 0x8; | |
263 | else { | |
264 | *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; | |
cb75d97e | 265 | if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) |
217275d0 FJ |
266 | *cr_lcd |= 0x30; |
267 | if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) { | |
268 | /* avoid being connected to both crtcs */ | |
269 | *cr_lcd_oth &= ~0x30; | |
270 | NVWriteVgaCrtc(dev, head ^ 1, | |
271 | NV_CIO_CRE_LCD__INDEX, | |
272 | *cr_lcd_oth); | |
6ee73861 BS |
273 | } |
274 | } | |
275 | } | |
276 | } | |
277 | ||
278 | ||
279 | static void nv04_dfp_mode_set(struct drm_encoder *encoder, | |
280 | struct drm_display_mode *mode, | |
281 | struct drm_display_mode *adjusted_mode) | |
282 | { | |
283 | struct drm_device *dev = encoder->dev; | |
77145f1c BS |
284 | struct nouveau_device *device = nouveau_dev(dev); |
285 | struct nouveau_drm *drm = nouveau_drm(dev); | |
6ee73861 | 286 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
017e6e29 BS |
287 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
288 | struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; | |
6ee73861 BS |
289 | struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc); |
290 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
291 | struct drm_display_mode *output_mode = &nv_encoder->mode; | |
de691855 | 292 | struct drm_connector *connector = &nv_connector->base; |
6ee73861 BS |
293 | uint32_t mode_ratio, panel_ratio; |
294 | ||
77145f1c | 295 | NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index); |
6ee73861 BS |
296 | drm_mode_debug_printmodeline(output_mode); |
297 | ||
298 | /* Initialize the FP registers in this CRTC. */ | |
299 | regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; | |
300 | regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; | |
301 | if (!nv_gf4_disp_arch(dev) || | |
302 | (output_mode->hsync_start - output_mode->hdisplay) >= | |
77145f1c | 303 | drm->vbios.digital_min_front_porch) |
6ee73861 BS |
304 | regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; |
305 | else | |
77145f1c | 306 | regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; |
6ee73861 BS |
307 | regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; |
308 | regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; | |
309 | regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; | |
310 | regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; | |
311 | ||
312 | regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; | |
313 | regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; | |
314 | regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; | |
315 | regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; | |
316 | regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; | |
317 | regp->fp_vert_regs[FP_VALID_START] = 0; | |
318 | regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; | |
319 | ||
320 | /* bit26: a bit seen on some g7x, no as yet discernable purpose */ | |
321 | regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | | |
322 | (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG)); | |
323 | /* Deal with vsync/hsync polarity */ | |
324 | /* LVDS screens do set this, but modes with +ve syncs are very rare */ | |
325 | if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
326 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; | |
327 | if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
328 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; | |
329 | /* panel scaling first, as native would get set otherwise */ | |
330 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || | |
331 | nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */ | |
332 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; | |
333 | else if (adjusted_mode->hdisplay == output_mode->hdisplay && | |
334 | adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ | |
335 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; | |
336 | else /* gpu needs to scale */ | |
337 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; | |
77145f1c | 338 | if (nv_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) |
6ee73861 BS |
339 | regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; |
340 | if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && | |
341 | output_mode->clock > 165000) | |
342 | regp->fp_control |= (2 << 24); | |
cb75d97e | 343 | if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) { |
abbd3f8e BS |
344 | bool duallink = false, dummy; |
345 | if (nv_connector->edid && | |
346 | nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { | |
347 | duallink = (((u8 *)nv_connector->edid)[121] == 2); | |
348 | } else { | |
349 | nouveau_bios_parse_lvds_table(dev, output_mode->clock, | |
350 | &duallink, &dummy); | |
351 | } | |
6ee73861 | 352 | |
6ee73861 BS |
353 | if (duallink) |
354 | regp->fp_control |= (8 << 28); | |
355 | } else | |
356 | if (output_mode->clock > 165000) | |
357 | regp->fp_control |= (8 << 28); | |
358 | ||
359 | regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | | |
360 | NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | | |
361 | NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | | |
362 | NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | | |
363 | NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | | |
364 | NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | | |
365 | NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; | |
366 | ||
367 | /* We want automatic scaling */ | |
368 | regp->fp_debug_1 = 0; | |
369 | /* This can override HTOTAL and VTOTAL */ | |
370 | regp->fp_debug_2 = 0; | |
371 | ||
372 | /* Use 20.12 fixed point format to avoid floats */ | |
373 | mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; | |
374 | panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; | |
375 | /* if ratios are equal, SCALE_ASPECT will automatically (and correctly) | |
376 | * get treated the same as SCALE_FULLSCREEN */ | |
377 | if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT && | |
378 | mode_ratio != panel_ratio) { | |
379 | uint32_t diff, scale; | |
380 | bool divide_by_2 = nv_gf4_disp_arch(dev); | |
381 | ||
382 | if (mode_ratio < panel_ratio) { | |
383 | /* vertical needs to expand to glass size (automatic) | |
384 | * horizontal needs to be scaled at vertical scale factor | |
385 | * to maintain aspect */ | |
386 | ||
387 | scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; | |
388 | regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | | |
389 | XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE); | |
390 | ||
391 | /* restrict area of screen used, horizontally */ | |
392 | diff = output_mode->hdisplay - | |
393 | output_mode->vdisplay * mode_ratio / (1 << 12); | |
394 | regp->fp_horiz_regs[FP_VALID_START] += diff / 2; | |
395 | regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; | |
396 | } | |
397 | ||
398 | if (mode_ratio > panel_ratio) { | |
399 | /* horizontal needs to expand to glass size (automatic) | |
400 | * vertical needs to be scaled at horizontal scale factor | |
401 | * to maintain aspect */ | |
402 | ||
403 | scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; | |
404 | regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | | |
405 | XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE); | |
406 | ||
407 | /* restrict area of screen used, vertically */ | |
408 | diff = output_mode->vdisplay - | |
409 | (1 << 12) * output_mode->hdisplay / mode_ratio; | |
410 | regp->fp_vert_regs[FP_VALID_START] += diff / 2; | |
411 | regp->fp_vert_regs[FP_VALID_END] -= diff / 2; | |
412 | } | |
413 | } | |
414 | ||
415 | /* Output property. */ | |
de691855 BS |
416 | if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || |
417 | (nv_connector->dithering_mode == DITHERING_MODE_AUTO && | |
f4510a27 | 418 | encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) { |
77145f1c | 419 | if (nv_device(drm->device)->chipset == 0x11) |
6ee73861 BS |
420 | regp->dither = savep->dither | 0x00010000; |
421 | else { | |
422 | int i; | |
423 | regp->dither = savep->dither | 0x00000001; | |
424 | for (i = 0; i < 3; i++) { | |
425 | regp->dither_regs[i] = 0xe4e4e4e4; | |
426 | regp->dither_regs[i + 3] = 0x44444444; | |
427 | } | |
428 | } | |
429 | } else { | |
77145f1c | 430 | if (nv_device(drm->device)->chipset != 0x11) { |
6ee73861 BS |
431 | /* reset them */ |
432 | int i; | |
433 | for (i = 0; i < 3; i++) { | |
434 | regp->dither_regs[i] = savep->dither_regs[i]; | |
435 | regp->dither_regs[i + 3] = savep->dither_regs[i + 3]; | |
436 | } | |
437 | } | |
438 | regp->dither = savep->dither; | |
439 | } | |
440 | ||
441 | regp->fp_margin_color = 0; | |
442 | } | |
443 | ||
444 | static void nv04_dfp_commit(struct drm_encoder *encoder) | |
445 | { | |
446 | struct drm_device *dev = encoder->dev; | |
77145f1c | 447 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 BS |
448 | struct drm_encoder_helper_funcs *helper = encoder->helper_private; |
449 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
450 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
cb75d97e | 451 | struct dcb_output *dcbe = nv_encoder->dcb; |
6ee73861 | 452 | int head = nouveau_crtc(encoder->crtc)->index; |
f5cb8ab1 | 453 | struct drm_encoder *slave_encoder; |
6ee73861 | 454 | |
cb75d97e | 455 | if (dcbe->type == DCB_OUTPUT_TMDS) |
6ee73861 | 456 | run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); |
cb75d97e | 457 | else if (dcbe->type == DCB_OUTPUT_LVDS) |
6ee73861 BS |
458 | call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock); |
459 | ||
460 | /* update fp_control state for any changes made by scripts, | |
461 | * so correct value is written at DPMS on */ | |
017e6e29 | 462 | nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = |
6ee73861 BS |
463 | NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); |
464 | ||
465 | /* This could use refinement for flatpanels, but it should work this way */ | |
77145f1c | 466 | if (nv_device(drm->device)->chipset < 0x44) |
6ee73861 BS |
467 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); |
468 | else | |
469 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); | |
470 | ||
4a9f822f | 471 | /* Init external transmitters */ |
f5cb8ab1 PM |
472 | slave_encoder = get_tmds_slave(encoder); |
473 | if (slave_encoder) | |
474 | get_slave_funcs(slave_encoder)->mode_set( | |
475 | slave_encoder, &nv_encoder->mode, &nv_encoder->mode); | |
4a9f822f | 476 | |
6ee73861 BS |
477 | helper->dpms(encoder, DRM_MODE_DPMS_ON); |
478 | ||
cee59f15 BS |
479 | NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", |
480 | drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), | |
481 | nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); | |
6ee73861 BS |
482 | } |
483 | ||
d31e078d FJ |
484 | static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) |
485 | { | |
486 | #ifdef __powerpc__ | |
487 | struct drm_device *dev = encoder->dev; | |
77145f1c | 488 | struct nouveau_device *device = nouveau_dev(dev); |
d31e078d FJ |
489 | |
490 | /* BIOS scripts usually take care of the backlight, thanks | |
491 | * Apple for your consistency. | |
492 | */ | |
ffbab09b VS |
493 | if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 || |
494 | dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) { | |
d31e078d | 495 | if (mode == DRM_MODE_DPMS_ON) { |
73f4b1f8 | 496 | nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31); |
77145f1c | 497 | nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1); |
d31e078d | 498 | } else { |
77145f1c BS |
499 | nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0); |
500 | nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0); | |
d31e078d FJ |
501 | } |
502 | } | |
503 | #endif | |
504 | } | |
505 | ||
6ee73861 BS |
506 | static inline bool is_powersaving_dpms(int mode) |
507 | { | |
92441b22 | 508 | return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED; |
6ee73861 BS |
509 | } |
510 | ||
511 | static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) | |
512 | { | |
513 | struct drm_device *dev = encoder->dev; | |
514 | struct drm_crtc *crtc = encoder->crtc; | |
77145f1c | 515 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 BS |
516 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
517 | bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms); | |
518 | ||
519 | if (nv_encoder->last_dpms == mode) | |
520 | return; | |
521 | nv_encoder->last_dpms = mode; | |
522 | ||
cee59f15 BS |
523 | NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n", |
524 | mode, nv_encoder->dcb->index); | |
6ee73861 BS |
525 | |
526 | if (was_powersaving && is_powersaving_dpms(mode)) | |
527 | return; | |
528 | ||
529 | if (nv_encoder->dcb->lvdsconf.use_power_scripts) { | |
6ee73861 BS |
530 | /* when removing an output, crtc may not be set, but PANEL_OFF |
531 | * must still be run | |
532 | */ | |
533 | int head = crtc ? nouveau_crtc(crtc)->index : | |
534 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); | |
535 | ||
536 | if (mode == DRM_MODE_DPMS_ON) { | |
6ee73861 | 537 | call_lvds_script(dev, nv_encoder->dcb, head, |
87886221 | 538 | LVDS_PANEL_ON, nv_encoder->mode.clock); |
6ee73861 BS |
539 | } else |
540 | /* pxclk of 0 is fine for PANEL_OFF, and for a | |
541 | * disconnected LVDS encoder there is no native_mode | |
542 | */ | |
543 | call_lvds_script(dev, nv_encoder->dcb, head, | |
544 | LVDS_PANEL_OFF, 0); | |
545 | } | |
546 | ||
d31e078d | 547 | nv04_dfp_update_backlight(encoder, mode); |
6ee73861 BS |
548 | nv04_dfp_update_fp_control(encoder, mode); |
549 | ||
550 | if (mode == DRM_MODE_DPMS_ON) | |
551 | nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index); | |
552 | else { | |
017e6e29 BS |
553 | nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); |
554 | nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; | |
6ee73861 | 555 | } |
017e6e29 | 556 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); |
6ee73861 BS |
557 | } |
558 | ||
559 | static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode) | |
560 | { | |
77145f1c | 561 | struct nouveau_drm *drm = nouveau_drm(encoder->dev); |
6ee73861 BS |
562 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
563 | ||
564 | if (nv_encoder->last_dpms == mode) | |
565 | return; | |
566 | nv_encoder->last_dpms = mode; | |
567 | ||
cee59f15 BS |
568 | NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n", |
569 | mode, nv_encoder->dcb->index); | |
6ee73861 | 570 | |
d31e078d | 571 | nv04_dfp_update_backlight(encoder, mode); |
6ee73861 BS |
572 | nv04_dfp_update_fp_control(encoder, mode); |
573 | } | |
574 | ||
575 | static void nv04_dfp_save(struct drm_encoder *encoder) | |
576 | { | |
577 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
578 | struct drm_device *dev = encoder->dev; | |
579 | ||
580 | if (nv_two_heads(dev)) | |
581 | nv_encoder->restore.head = | |
582 | nv04_dfp_get_bound_head(dev, nv_encoder->dcb); | |
583 | } | |
584 | ||
585 | static void nv04_dfp_restore(struct drm_encoder *encoder) | |
586 | { | |
587 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
588 | struct drm_device *dev = encoder->dev; | |
6ee73861 BS |
589 | int head = nv_encoder->restore.head; |
590 | ||
cb75d97e | 591 | if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) { |
fb522ee1 MS |
592 | struct nouveau_connector *connector = |
593 | nouveau_encoder_connector_get(nv_encoder); | |
594 | ||
595 | if (connector && connector->native_mode) | |
596 | call_lvds_script(dev, nv_encoder->dcb, head, | |
597 | LVDS_PANEL_ON, | |
598 | connector->native_mode->clock); | |
6ee73861 | 599 | |
cb75d97e | 600 | } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) { |
6ee73861 | 601 | int clock = nouveau_hw_pllvals_to_clk |
017e6e29 | 602 | (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals); |
6ee73861 BS |
603 | |
604 | run_tmds_table(dev, nv_encoder->dcb, head, clock); | |
605 | } | |
606 | ||
607 | nv_encoder->last_dpms = NV_DPMS_CLEARED; | |
608 | } | |
609 | ||
610 | static void nv04_dfp_destroy(struct drm_encoder *encoder) | |
611 | { | |
612 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
613 | ||
4a9f822f FJ |
614 | if (get_slave_funcs(encoder)) |
615 | get_slave_funcs(encoder)->destroy(encoder); | |
616 | ||
6ee73861 BS |
617 | drm_encoder_cleanup(encoder); |
618 | kfree(nv_encoder); | |
619 | } | |
620 | ||
4a9f822f FJ |
621 | static void nv04_tmds_slave_init(struct drm_encoder *encoder) |
622 | { | |
623 | struct drm_device *dev = encoder->dev; | |
cb75d97e | 624 | struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; |
77145f1c BS |
625 | struct nouveau_drm *drm = nouveau_drm(dev); |
626 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
627 | struct nouveau_i2c_port *port = i2c->find(i2c, 2); | |
9e2b734f | 628 | struct nouveau_i2c_board_info info[] = { |
4a9f822f | 629 | { |
9e2b734f MP |
630 | { |
631 | .type = "sil164", | |
632 | .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38), | |
633 | .platform_data = &(struct sil164_encoder_params) { | |
634 | SIL164_INPUT_EDGE_RISING | |
635 | } | |
636 | }, 0 | |
4a9f822f FJ |
637 | }, |
638 | { } | |
639 | }; | |
640 | int type; | |
641 | ||
77145f1c | 642 | if (!nv_gf4_disp_arch(dev) || !port || |
2d14e35c | 643 | get_tmds_slave(encoder)) |
4a9f822f FJ |
644 | return; |
645 | ||
fdd239ac | 646 | type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL, NULL); |
4a9f822f FJ |
647 | if (type < 0) |
648 | return; | |
649 | ||
650 | drm_i2c_encoder_init(dev, to_encoder_slave(encoder), | |
9e2b734f | 651 | &port->adapter, &info[type].dev); |
4a9f822f FJ |
652 | } |
653 | ||
6ee73861 BS |
654 | static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { |
655 | .dpms = nv04_lvds_dpms, | |
656 | .save = nv04_dfp_save, | |
657 | .restore = nv04_dfp_restore, | |
658 | .mode_fixup = nv04_dfp_mode_fixup, | |
659 | .prepare = nv04_dfp_prepare, | |
660 | .commit = nv04_dfp_commit, | |
661 | .mode_set = nv04_dfp_mode_set, | |
662 | .detect = NULL, | |
663 | }; | |
664 | ||
665 | static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = { | |
666 | .dpms = nv04_tmds_dpms, | |
667 | .save = nv04_dfp_save, | |
668 | .restore = nv04_dfp_restore, | |
669 | .mode_fixup = nv04_dfp_mode_fixup, | |
670 | .prepare = nv04_dfp_prepare, | |
671 | .commit = nv04_dfp_commit, | |
672 | .mode_set = nv04_dfp_mode_set, | |
673 | .detect = NULL, | |
674 | }; | |
675 | ||
676 | static const struct drm_encoder_funcs nv04_dfp_funcs = { | |
677 | .destroy = nv04_dfp_destroy, | |
678 | }; | |
679 | ||
8f1a6086 | 680 | int |
cb75d97e | 681 | nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry) |
6ee73861 BS |
682 | { |
683 | const struct drm_encoder_helper_funcs *helper; | |
6ee73861 | 684 | struct nouveau_encoder *nv_encoder = NULL; |
8f1a6086 | 685 | struct drm_encoder *encoder; |
6ee73861 BS |
686 | int type; |
687 | ||
688 | switch (entry->type) { | |
cb75d97e | 689 | case DCB_OUTPUT_TMDS: |
6ee73861 BS |
690 | type = DRM_MODE_ENCODER_TMDS; |
691 | helper = &nv04_tmds_helper_funcs; | |
692 | break; | |
cb75d97e | 693 | case DCB_OUTPUT_LVDS: |
6ee73861 BS |
694 | type = DRM_MODE_ENCODER_LVDS; |
695 | helper = &nv04_lvds_helper_funcs; | |
696 | break; | |
697 | default: | |
698 | return -EINVAL; | |
699 | } | |
700 | ||
701 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
702 | if (!nv_encoder) | |
703 | return -ENOMEM; | |
704 | ||
705 | encoder = to_drm_encoder(nv_encoder); | |
706 | ||
707 | nv_encoder->dcb = entry; | |
708 | nv_encoder->or = ffs(entry->or) - 1; | |
709 | ||
8f1a6086 | 710 | drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type); |
6ee73861 BS |
711 | drm_encoder_helper_add(encoder, helper); |
712 | ||
713 | encoder->possible_crtcs = entry->heads; | |
714 | encoder->possible_clones = 0; | |
715 | ||
cb75d97e | 716 | if (entry->type == DCB_OUTPUT_TMDS && |
4a9f822f FJ |
717 | entry->location != DCB_LOC_ON_CHIP) |
718 | nv04_tmds_slave_init(encoder); | |
719 | ||
8f1a6086 | 720 | drm_mode_connector_attach_encoder(connector, encoder); |
6ee73861 BS |
721 | return 0; |
722 | } |