[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / include / nvif / class.h

#ifndef __NVIF_CLASS_H__
#define __NVIF_CLASS_H__

/* these class numbers are made up by us, and not nvidia-assigned */
#define NVIF_CLASS_CONTROL                                                   -1
#define NVIF_CLASS_PERFMON                                                   -2
#define NVIF_CLASS_PERFDOM                                                   -3
#define NVIF_CLASS_SW_NV04                                    /* if0004.h */ -4
#define NVIF_CLASS_SW_NV10                                    /* if0005.h */ -5
#define NVIF_CLASS_SW_NV50                                    /* if0005.h */ -6
#define NVIF_CLASS_SW_GF100                                   /* if0005.h */ -7

/* the below match nvidia-assigned (either in hw, or sw) class numbers */
#define NV_DEVICE                                                    0x00000080

#define NV_DMA_FROM_MEMORY                                           0x00000002
#define NV_DMA_TO_MEMORY                                             0x00000003
#define NV_DMA_IN_MEMORY                                             0x0000003d

#define FERMI_TWOD_A                                                 0x0000902d

#define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039

#define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
#define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140

#define NV04_DISP                                                    0x00000046

#define NV03_CHANNEL_DMA                                             0x0000006b
#define NV10_CHANNEL_DMA                                             0x0000006e
#define NV17_CHANNEL_DMA                                             0x0000176e
#define NV40_CHANNEL_DMA                                             0x0000406e
#define NV50_CHANNEL_DMA                                             0x0000506e
#define G82_CHANNEL_DMA                                              0x0000826e

#define NV50_CHANNEL_GPFIFO                                          0x0000506f
#define G82_CHANNEL_GPFIFO                                           0x0000826f
#define FERMI_CHANNEL_GPFIFO                                         0x0000906f
#define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
#define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f

#define NV50_DISP                                                    0x00005070
#define G82_DISP                                                     0x00008270
#define GT200_DISP                                                   0x00008370
#define GT214_DISP                                                   0x00008570
#define GT206_DISP                                                   0x00008870
#define GF110_DISP                                                   0x00009070
#define GK104_DISP                                                   0x00009170
#define GK110_DISP                                                   0x00009270
#define GM107_DISP                                                   0x00009470
#define GM204_DISP                                                   0x00009570

#define NV31_MPEG                                                    0x00003174
#define G82_MPEG                                                     0x00008274

#define NV74_VP2                                                     0x00007476

#define NV50_DISP_CURSOR                                             0x0000507a
#define G82_DISP_CURSOR                                              0x0000827a
#define GT214_DISP_CURSOR                                            0x0000857a
#define GF110_DISP_CURSOR                                            0x0000907a
#define GK104_DISP_CURSOR                                            0x0000917a

#define NV50_DISP_OVERLAY                                            0x0000507b
#define G82_DISP_OVERLAY                                             0x0000827b
#define GT214_DISP_OVERLAY                                           0x0000857b
#define GF110_DISP_OVERLAY                                           0x0000907b
#define GK104_DISP_OVERLAY                                           0x0000917b

#define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
#define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
#define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
#define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
#define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
#define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c

#define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
#define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
#define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
#define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
#define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
#define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
#define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
#define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
#define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
#define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d

#define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
#define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
#define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
#define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
#define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e

#define FERMI_A                                       /* cl9097.h */ 0x00009097
#define FERMI_B                                       /* cl9097.h */ 0x00009197
#define FERMI_C                                       /* cl9097.h */ 0x00009297

#define KEPLER_A                                      /* cl9097.h */ 0x0000a097
#define KEPLER_B                                      /* cl9097.h */ 0x0000a197
#define KEPLER_C                                      /* cl9097.h */ 0x0000a297

#define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
#define MAXWELL_B                                     /* cl9097.h */ 0x0000b197

#define NV74_BSP                                                     0x000074b0

#define GT212_MSVLD                                                  0x000085b1
#define IGT21A_MSVLD                                                 0x000086b1
#define G98_MSVLD                                                    0x000088b1
#define GF100_MSVLD                                                  0x000090b1
#define GK104_MSVLD                                                  0x000095b1

#define GT212_MSPDEC                                                 0x000085b2
#define G98_MSPDEC                                                   0x000088b2
#define GF100_MSPDEC                                                 0x000090b2
#define GK104_MSPDEC                                                 0x000095b2

#define GT212_MSPPP                                                  0x000085b3
#define G98_MSPPP                                                    0x000088b3
#define GF100_MSPPP                                                  0x000090b3

#define G98_SEC                                                      0x000088b4

#define GT212_DMA                                                    0x000085b5
#define FERMI_DMA                                                    0x000090b5
#define KEPLER_DMA_COPY_A                                            0x0000a0b5
#define MAXWELL_DMA_COPY_A                                           0x0000b0b5

#define FERMI_DECOMPRESS                                             0x000090b8

#define FERMI_COMPUTE_A                                              0x000090c0
#define FERMI_COMPUTE_B                                              0x000091c0
#define KEPLER_COMPUTE_A                                             0x0000a0c0
#define KEPLER_COMPUTE_B                                             0x0000a1c0
#define MAXWELL_COMPUTE_A                                            0x0000b0c0
#define MAXWELL_COMPUTE_B                                            0x0000b1c0

#define NV74_CIPHER                                                  0x000074c1

/*******************************************************************************
 * client
 ******************************************************************************/

#define NV_CLIENT_DEVLIST                                                  0x00

struct nv_client_devlist_v0 {
	__u8  version;
	__u8  count;
	__u8  pad02[6];
	__u64 device[];
};


/*******************************************************************************
 * device
 ******************************************************************************/

struct nv_device_v0 {
	__u8  version;
	__u8  pad01[7];
	__u64 device;	/* device identifier, ~0 for client default */
};

#define NV_DEVICE_V0_INFO                                                  0x00
#define NV_DEVICE_V0_TIME                                                  0x01

struct nv_device_info_v0 {
	__u8  version;
#define NV_DEVICE_INFO_V0_IGP                                              0x00
#define NV_DEVICE_INFO_V0_PCI                                              0x01
#define NV_DEVICE_INFO_V0_AGP                                              0x02
#define NV_DEVICE_INFO_V0_PCIE                                             0x03
#define NV_DEVICE_INFO_V0_SOC                                              0x04
	__u8  platform;
	__u16 chipset;	/* from NV_PMC_BOOT_0 */
	__u8  revision;	/* from NV_PMC_BOOT_0 */
#define NV_DEVICE_INFO_V0_TNT                                              0x01
#define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
#define NV_DEVICE_INFO_V0_KELVIN                                           0x03
#define NV_DEVICE_INFO_V0_RANKINE                                          0x04
#define NV_DEVICE_INFO_V0_CURIE                                            0x05
#define NV_DEVICE_INFO_V0_TESLA                                            0x06
#define NV_DEVICE_INFO_V0_FERMI                                            0x07
#define NV_DEVICE_INFO_V0_KEPLER                                           0x08
#define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
	__u8  family;
	__u8  pad06[2];
	__u64 ram_size;
	__u64 ram_user;
	char  chip[16];
	char  name[64];
};

struct nv_device_time_v0 {
	__u8  version;
	__u8  pad01[7];
	__u64 time;
};


/*******************************************************************************
 * context dma
 ******************************************************************************/

struct nv_dma_v0 {
	__u8  version;
#define NV_DMA_V0_TARGET_VM                                                0x00
#define NV_DMA_V0_TARGET_VRAM                                              0x01
#define NV_DMA_V0_TARGET_PCI                                               0x02
#define NV_DMA_V0_TARGET_PCI_US                                            0x03
#define NV_DMA_V0_TARGET_AGP                                               0x04
	__u8  target;
#define NV_DMA_V0_ACCESS_VM                                                0x00
#define NV_DMA_V0_ACCESS_RD                                                0x01
#define NV_DMA_V0_ACCESS_WR                                                0x02
#define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
	__u8  access;
	__u8  pad03[5];
	__u64 start;
	__u64 limit;
	/* ... chipset-specific class data */
};

struct nv50_dma_v0 {
	__u8  version;
#define NV50_DMA_V0_PRIV_VM                                                0x00
#define NV50_DMA_V0_PRIV_US                                                0x01
#define NV50_DMA_V0_PRIV__S                                                0x02
	__u8  priv;
#define NV50_DMA_V0_PART_VM                                                0x00
#define NV50_DMA_V0_PART_256                                               0x01
#define NV50_DMA_V0_PART_1KB                                               0x02
	__u8  part;
#define NV50_DMA_V0_COMP_NONE                                              0x00
#define NV50_DMA_V0_COMP_1                                                 0x01
#define NV50_DMA_V0_COMP_2                                                 0x02
#define NV50_DMA_V0_COMP_VM                                                0x03
	__u8  comp;
#define NV50_DMA_V0_KIND_PITCH                                             0x00
#define NV50_DMA_V0_KIND_VM                                                0x7f
	__u8  kind;
	__u8  pad05[3];
};

struct gf100_dma_v0 {
	__u8  version;
#define GF100_DMA_V0_PRIV_VM                                               0x00
#define GF100_DMA_V0_PRIV_US                                               0x01
#define GF100_DMA_V0_PRIV__S                                               0x02
	__u8  priv;
#define GF100_DMA_V0_KIND_PITCH                                            0x00
#define GF100_DMA_V0_KIND_VM                                               0xff
	__u8  kind;
	__u8  pad03[5];
};

struct gf119_dma_v0 {
	__u8  version;
#define GF119_DMA_V0_PAGE_LP                                               0x00
#define GF119_DMA_V0_PAGE_SP                                               0x01
	__u8  page;
#define GF119_DMA_V0_KIND_PITCH                                            0x00
#define GF119_DMA_V0_KIND_VM                                               0xff
	__u8  kind;
	__u8  pad03[5];
};


/*******************************************************************************
 * perfmon
 ******************************************************************************/

#define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
#define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
#define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02

struct nvif_perfmon_query_domain_v0 {
	__u8  version;
	__u8  id;
	__u8  counter_nr;
	__u8  iter;
	__u16 signal_nr;
	__u8  pad05[2];
	char  name[64];
};

struct nvif_perfmon_query_signal_v0 {
	__u8  version;
	__u8  domain;
	__u16 iter;
	__u8  signal;
	__u8  source_nr;
	__u8  pad05[2];
	char  name[64];
};

struct nvif_perfmon_query_source_v0 {
	__u8  version;
	__u8  domain;
	__u8  signal;
	__u8  iter;
	__u8  pad04[4];
	__u32 source;
	__u32 mask;
	char  name[64];
};


/*******************************************************************************
 * perfdom
 ******************************************************************************/

struct nvif_perfdom_v0 {
	__u8  version;
	__u8  domain;
	__u8  mode;
	__u8  pad03[1];
	struct {
		__u8  signal[4];
		__u64 source[4][8];
		__u16 logic_op;
	} ctr[4];
};

#define NVIF_PERFDOM_V0_INIT                                               0x00
#define NVIF_PERFDOM_V0_SAMPLE                                             0x01
#define NVIF_PERFDOM_V0_READ                                               0x02

struct nvif_perfdom_init {
};

struct nvif_perfdom_sample {
};

struct nvif_perfdom_read_v0 {
	__u8  version;
	__u8  pad01[7];
	__u32 ctr[4];
	__u32 clk;
	__u8  pad04[4];
};


/*******************************************************************************
 * device control
 ******************************************************************************/

#define NVIF_CONTROL_PSTATE_INFO                                           0x00
#define NVIF_CONTROL_PSTATE_ATTR                                           0x01
#define NVIF_CONTROL_PSTATE_USER                                           0x02

struct nvif_control_pstate_info_v0 {
	__u8  version;
	__u8  count; /* out: number of power states */
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
	__s8  ustate_ac; /* out: target pstate index */
	__s8  ustate_dc; /* out: target pstate index */
	__s8  pwrsrc; /* out: current power source */
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
	__s8  pstate; /* out: current pstate index */
	__u8  pad06[2];
};

struct nvif_control_pstate_attr_v0 {
	__u8  version;
#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
	__s8  state; /*  in: index of pstate to query
		      * out: pstate identifier
		      */
	__u8  index; /*  in: index of attribute to query
		      * out: index of next attribute, or 0 if no more
		      */
	__u8  pad03[5];
	__u32 min;
	__u32 max;
	char  name[32];
	char  unit[16];
};

struct nvif_control_pstate_user_v0 {
	__u8  version;
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
	__s8  ustate; /*  in: pstate identifier */
	__s8  pwrsrc; /*  in: target power source */
	__u8  pad03[5];
};


/*******************************************************************************
 * DMA FIFO channels
 ******************************************************************************/

struct nv03_channel_dma_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad02[2];
	__u32 offset;
	__u64 pushbuf;
};

struct nv50_channel_dma_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad02[6];
	__u64 vm;
	__u64 pushbuf;
	__u64 offset;
};

#define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00

/*******************************************************************************
 * GPFIFO channels
 ******************************************************************************/

struct nv50_channel_gpfifo_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad02[2];
	__u32 ilength;
	__u64 ioffset;
	__u64 pushbuf;
	__u64 vm;
};

struct fermi_channel_gpfifo_v0 {
	__u8  version;
	__u8  chid;
	__u8  pad02[2];
	__u32 ilength;
	__u64 ioffset;
	__u64 vm;
};

struct kepler_channel_gpfifo_a_v0 {
	__u8  version;
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
	__u8  engine;
	__u16 chid;
	__u32 ilength;
	__u64 ioffset;
	__u64 vm;
};

/*******************************************************************************
 * legacy display
 ******************************************************************************/

#define NV04_DISP_NTFY_VBLANK                                              0x00
#define NV04_DISP_NTFY_CONN                                                0x01

struct nv04_disp_mthd_v0 {
	__u8  version;
#define NV04_DISP_SCANOUTPOS                                               0x00
	__u8  method;
	__u8  head;
	__u8  pad03[5];
};

struct nv04_disp_scanoutpos_v0 {
	__u8  version;
	__u8  pad01[7];
	__s64 time[2];
	__u16 vblanks;
	__u16 vblanke;
	__u16 vtotal;
	__u16 vline;
	__u16 hblanks;
	__u16 hblanke;
	__u16 htotal;
	__u16 hline;
};

/*******************************************************************************
 * display
 ******************************************************************************/

#define NV50_DISP_MTHD                                                     0x00

struct nv50_disp_mthd_v0 {
	__u8  version;
#define NV50_DISP_SCANOUTPOS                                               0x00
	__u8  method;
	__u8  head;
	__u8  pad03[5];
};

struct nv50_disp_mthd_v1 {
	__u8  version;
#define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
#define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
#define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
#define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
#define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
#define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
	__u8  method;
	__u16 hasht;
	__u16 hashm;
	__u8  pad06[2];
};

struct nv50_disp_dac_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  data;
	__u8  vsync;
	__u8  hsync;
	__u8  pad05[3];
};

struct nv50_disp_dac_load_v0 {
	__u8  version;
	__u8  load;
	__u8  pad02[2];
	__u32 data;
};

struct nv50_disp_sor_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  pad02[6];
};

struct nv50_disp_sor_hda_eld_v0 {
	__u8  version;
	__u8  pad01[7];
	__u8  data[];
};

struct nv50_disp_sor_hdmi_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  max_ac_packet;
	__u8  rekey;
	__u8  pad04[4];
};

struct nv50_disp_sor_lvds_script_v0 {
	__u8  version;
	__u8  pad01[1];
	__u16 script;
	__u8  pad04[4];
};

struct nv50_disp_sor_dp_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  pad02[6];
};

struct nv50_disp_pior_pwr_v0 {
	__u8  version;
	__u8  state;
	__u8  type;
	__u8  pad03[5];
};

/* core */
struct nv50_disp_core_channel_dma_v0 {
	__u8  version;
	__u8  pad01[7];
	__u64 pushbuf;
};

#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00

/* cursor immediate */
struct nv50_disp_cursor_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
};

#define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00

/* base */
struct nv50_disp_base_channel_dma_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
	__u64 pushbuf;
};

#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00

/* overlay */
struct nv50_disp_overlay_channel_dma_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
	__u64 pushbuf;
};

#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00

/* overlay immediate */
struct nv50_disp_overlay_v0 {
	__u8  version;
	__u8  head;
	__u8  pad02[6];
};

#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
#endif
Commit	Line	Data
d01c3092 BS	1	#ifndef __NVIF_CLASS_H__
	2	#define __NVIF_CLASS_H__
	3
08f7633c BS	4	/* these class numbers are made up by us, and not nvidia-assigned */
	5	#define NVIF_CLASS_CONTROL -1
	6	#define NVIF_CLASS_PERFMON -2
	7	#define NVIF_CLASS_PERFDOM -3
538b269b BS	8	#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4
	9	#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5
	10	#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6
	11	#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7
d01c3092 BS	12
	13	/* the below match nvidia-assigned (either in hw, or sw) class numbers */
	14	#define NV_DEVICE 0x00000080
	15
4acfd707 BS	16	#define NV_DMA_FROM_MEMORY 0x00000002
	17	#define NV_DMA_TO_MEMORY 0x00000003
	18	#define NV_DMA_IN_MEMORY 0x0000003d
	19
3740c825 BS	20	#define FERMI_TWOD_A 0x0000902d
3740c825 BS	21
9ee971a0	22	#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
3740c825 BS	23
	24	#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
	25	#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
	26
648d4dfd BS	27	#define NV04_DISP 0x00000046
648d4dfd BS	28
bbf8906b BS	29	#define NV03_CHANNEL_DMA 0x0000006b
	30	#define NV10_CHANNEL_DMA 0x0000006e
	31	#define NV17_CHANNEL_DMA 0x0000176e
	32	#define NV40_CHANNEL_DMA 0x0000406e
	33	#define NV50_CHANNEL_DMA 0x0000506e
	34	#define G82_CHANNEL_DMA 0x0000826e
	35
	36	#define NV50_CHANNEL_GPFIFO 0x0000506f
	37	#define G82_CHANNEL_GPFIFO 0x0000826f
	38	#define FERMI_CHANNEL_GPFIFO 0x0000906f
	39	#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
89025bd4	40	#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
bbf8906b	41
648d4dfd BS	42	#define NV50_DISP 0x00005070
	43	#define G82_DISP 0x00008270
	44	#define GT200_DISP 0x00008370
	45	#define GT214_DISP 0x00008570
	46	#define GT206_DISP 0x00008870
	47	#define GF110_DISP 0x00009070
	48	#define GK104_DISP 0x00009170
	49	#define GK110_DISP 0x00009270
	50	#define GM107_DISP 0x00009470
1f89b475	51	#define GM204_DISP 0x00009570
648d4dfd	52
218f978d BS	53	#define NV31_MPEG 0x00003174
	54	#define G82_MPEG 0x00008274
	55
c79a191b BS	56	#define NV74_VP2 0x00007476
c79a191b BS	57
648d4dfd BS	58	#define NV50_DISP_CURSOR 0x0000507a
	59	#define G82_DISP_CURSOR 0x0000827a
	60	#define GT214_DISP_CURSOR 0x0000857a
	61	#define GF110_DISP_CURSOR 0x0000907a
	62	#define GK104_DISP_CURSOR 0x0000917a
	63
	64	#define NV50_DISP_OVERLAY 0x0000507b
	65	#define G82_DISP_OVERLAY 0x0000827b
	66	#define GT214_DISP_OVERLAY 0x0000857b
	67	#define GF110_DISP_OVERLAY 0x0000907b
	68	#define GK104_DISP_OVERLAY 0x0000917b
	69
	70	#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
	71	#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
	72	#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
	73	#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
	74	#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
	75	#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
	76	#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
	77
	78	#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
	79	#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
	80	#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
	81	#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
	82	#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
	83	#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
	84	#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
	85	#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
	86	#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
1f89b475	87	#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
648d4dfd BS	88
	89	#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
	90	#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
	91	#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
	92	#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
	93	#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
	94	#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
	95
53a6df77 BS	96	#define FERMI_A /* cl9097.h */ 0x00009097
	97	#define FERMI_B /* cl9097.h */ 0x00009197
	98	#define FERMI_C /* cl9097.h */ 0x00009297
ac9738bb	99
53a6df77 BS	100	#define KEPLER_A /* cl9097.h */ 0x0000a097
	101	#define KEPLER_B /* cl9097.h */ 0x0000a197
	102	#define KEPLER_C /* cl9097.h */ 0x0000a297
ac9738bb	103
53a6df77 BS	104	#define MAXWELL_A /* cl9097.h */ 0x0000b097
53a6df77 BS	105	#define MAXWELL_B /* cl9097.h */ 0x0000b197
ac9738bb	106
c79a191b BS	107	#define NV74_BSP 0x000074b0
c79a191b BS	108
9d498e0f BS	109	#define GT212_MSVLD 0x000085b1
	110	#define IGT21A_MSVLD 0x000086b1
	111	#define G98_MSVLD 0x000088b1
	112	#define GF100_MSVLD 0x000090b1
	113	#define GK104_MSVLD 0x000095b1
	114
	115	#define GT212_MSPDEC 0x000085b2
	116	#define G98_MSPDEC 0x000088b2
	117	#define GF100_MSPDEC 0x000090b2
	118	#define GK104_MSPDEC 0x000095b2
	119
	120	#define GT212_MSPPP 0x000085b3
	121	#define G98_MSPPP 0x000088b3
	122	#define GF100_MSPPP 0x000090b3
	123
	124	#define G98_SEC 0x000088b4
	125
	126	#define GT212_DMA 0x000085b5
	127	#define FERMI_DMA 0x000090b5
e5ff1127 BS	128	#define KEPLER_DMA_COPY_A 0x0000a0b5
e5ff1127 BS	129	#define MAXWELL_DMA_COPY_A 0x0000b0b5
9d498e0f BS	130
	131	#define FERMI_DECOMPRESS 0x000090b8
	132
d6bd3803 BS	133	#define FERMI_COMPUTE_A 0x000090c0
d6bd3803 BS	134	#define FERMI_COMPUTE_B 0x000091c0
d6bd3803 BS	135	#define KEPLER_COMPUTE_A 0x0000a0c0
d6bd3803 BS	136	#define KEPLER_COMPUTE_B 0x0000a1c0
d6bd3803	137	#define MAXWELL_COMPUTE_A 0x0000b0c0
3fed3ea9	138	#define MAXWELL_COMPUTE_B 0x0000b1c0
d6bd3803	139
b3c98150	140	#define NV74_CIPHER 0x000074c1
d01c3092	141
803c1787 BS	142	/*******************************************************************************
	143	* client
	144	******************************************************************************/
	145
	146	#define NV_CLIENT_DEVLIST 0x00
	147
	148	struct nv_client_devlist_v0 {
	149	__u8 version;
	150	__u8 count;
	151	__u8 pad02[6];
	152	__u64 device[];
	153	};
	154
	155
d01c3092 BS	156	/*******************************************************************************
	157	* device
	158	******************************************************************************/
	159
586491e6 BS	160	struct nv_device_v0 {
	161	__u8 version;
	162	__u8 pad01[7];
	163	__u64 device; /* device identifier, ~0 for client default */
586491e6 BS	164	};
586491e6 BS	165
d01c3092	166	#define NV_DEVICE_V0_INFO 0x00
d61f4c17	167	#define NV_DEVICE_V0_TIME 0x01
d01c3092 BS	168
	169	struct nv_device_info_v0 {
	170	__u8 version;
	171	#define NV_DEVICE_INFO_V0_IGP 0x00
	172	#define NV_DEVICE_INFO_V0_PCI 0x01
	173	#define NV_DEVICE_INFO_V0_AGP 0x02
	174	#define NV_DEVICE_INFO_V0_PCIE 0x03
	175	#define NV_DEVICE_INFO_V0_SOC 0x04
	176	__u8 platform;
	177	__u16 chipset; /* from NV_PMC_BOOT_0 */
	178	__u8 revision; /* from NV_PMC_BOOT_0 */
	179	#define NV_DEVICE_INFO_V0_TNT 0x01
	180	#define NV_DEVICE_INFO_V0_CELSIUS 0x02
	181	#define NV_DEVICE_INFO_V0_KELVIN 0x03
	182	#define NV_DEVICE_INFO_V0_RANKINE 0x04
	183	#define NV_DEVICE_INFO_V0_CURIE 0x05
	184	#define NV_DEVICE_INFO_V0_TESLA 0x06
	185	#define NV_DEVICE_INFO_V0_FERMI 0x07
	186	#define NV_DEVICE_INFO_V0_KEPLER 0x08
	187	#define NV_DEVICE_INFO_V0_MAXWELL 0x09
	188	__u8 family;
	189	__u8 pad06[2];
	190	__u64 ram_size;
	191	__u64 ram_user;
22827fa4 BS	192	char chip[16];
22827fa4 BS	193	char name[64];
d01c3092 BS	194	};
d01c3092 BS	195
d61f4c17 BS	196	struct nv_device_time_v0 {
	197	__u8 version;
	198	__u8 pad01[7];
	199	__u64 time;
	200	};
	201
4acfd707 BS	202
	203	/*******************************************************************************
	204	* context dma
	205	******************************************************************************/
	206
	207	struct nv_dma_v0 {
	208	__u8 version;
	209	#define NV_DMA_V0_TARGET_VM 0x00
	210	#define NV_DMA_V0_TARGET_VRAM 0x01
	211	#define NV_DMA_V0_TARGET_PCI 0x02
	212	#define NV_DMA_V0_TARGET_PCI_US 0x03
	213	#define NV_DMA_V0_TARGET_AGP 0x04
	214	__u8 target;
	215	#define NV_DMA_V0_ACCESS_VM 0x00
	216	#define NV_DMA_V0_ACCESS_RD 0x01
	217	#define NV_DMA_V0_ACCESS_WR 0x02
	218	#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD \| NV_DMA_V0_ACCESS_WR)
	219	__u8 access;
	220	__u8 pad03[5];
	221	__u64 start;
	222	__u64 limit;
	223	/* ... chipset-specific class data */
	224	};
	225
	226	struct nv50_dma_v0 {
	227	__u8 version;
	228	#define NV50_DMA_V0_PRIV_VM 0x00
	229	#define NV50_DMA_V0_PRIV_US 0x01
	230	#define NV50_DMA_V0_PRIV__S 0x02
	231	__u8 priv;
	232	#define NV50_DMA_V0_PART_VM 0x00
	233	#define NV50_DMA_V0_PART_256 0x01
	234	#define NV50_DMA_V0_PART_1KB 0x02
	235	__u8 part;
	236	#define NV50_DMA_V0_COMP_NONE 0x00
	237	#define NV50_DMA_V0_COMP_1 0x01
	238	#define NV50_DMA_V0_COMP_2 0x02
	239	#define NV50_DMA_V0_COMP_VM 0x03
	240	__u8 comp;
	241	#define NV50_DMA_V0_KIND_PITCH 0x00
	242	#define NV50_DMA_V0_KIND_VM 0x7f
	243	__u8 kind;
	244	__u8 pad05[3];
	245	};
	246
	247	struct gf100_dma_v0 {
	248	__u8 version;
	249	#define GF100_DMA_V0_PRIV_VM 0x00
	250	#define GF100_DMA_V0_PRIV_US 0x01
	251	#define GF100_DMA_V0_PRIV__S 0x02
	252	__u8 priv;
	253	#define GF100_DMA_V0_KIND_PITCH 0x00
	254	#define GF100_DMA_V0_KIND_VM 0xff
	255	__u8 kind;
	256	__u8 pad03[5];
	257	};
	258
bd70563f	259	struct gf119_dma_v0 {
4acfd707	260	__u8 version;
bd70563f BS	261	#define GF119_DMA_V0_PAGE_LP 0x00
bd70563f BS	262	#define GF119_DMA_V0_PAGE_SP 0x01
4acfd707	263	__u8 page;
bd70563f BS	264	#define GF119_DMA_V0_KIND_PITCH 0x00
bd70563f BS	265	#define GF119_DMA_V0_KIND_VM 0xff
4acfd707 BS	266	__u8 kind;
	267	__u8 pad03[5];
	268	};
	269
96af8222 BS	270
	271	/*******************************************************************************
	272	* perfmon
	273	******************************************************************************/
	274
45f0f94d SP	275	#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
45f0f94d SP	276	#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
6f99c848	277	#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
45f0f94d SP	278
	279	struct nvif_perfmon_query_domain_v0 {
	280	__u8 version;
	281	__u8 id;
	282	__u8 counter_nr;
	283	__u8 iter;
e4047599 SP	284	__u16 signal_nr;
e4047599 SP	285	__u8 pad05[2];
df0b37ee	286	char name[64];
45f0f94d	287	};
5a0bc4b5 SP	288
	289	struct nvif_perfmon_query_signal_v0 {
	290	__u8 version;
3e1b3357	291	__u8 domain;
e4047599	292	__u16 iter;
10a4d2b2	293	__u8 signal;
50d138d7 SP	294	__u8 source_nr;
50d138d7 SP	295	__u8 pad05[2];
5a0bc4b5 SP	296	char name[64];
	297	};
	298
6f99c848 SP	299	struct nvif_perfmon_query_source_v0 {
	300	__u8 version;
	301	__u8 domain;
	302	__u8 signal;
	303	__u8 iter;
	304	__u8 pad04[4];
	305	__u32 source;
	306	__u32 mask;
	307	char name[64];
	308	};
	309
5a0bc4b5 SP	310
5a0bc4b5 SP	311	/*******************************************************************************
0f380436	312	* perfdom
5a0bc4b5 SP	313	******************************************************************************/
5a0bc4b5 SP	314
0f380436	315	struct nvif_perfdom_v0 {
96af8222	316	__u8 version;
10a4d2b2	317	__u8 domain;
0f380436 SP	318	__u8 mode;
	319	__u8 pad03[1];
	320	struct {
	321	__u8 signal[4];
6137b5a7	322	__u64 source[4][8];
0f380436 SP	323	__u16 logic_op;
0f380436 SP	324	} ctr[4];
96af8222 BS	325	};
96af8222 BS	326
0f380436 SP	327	#define NVIF_PERFDOM_V0_INIT 0x00
	328	#define NVIF_PERFDOM_V0_SAMPLE 0x01
	329	#define NVIF_PERFDOM_V0_READ 0x02
3bfdde17	330
0f380436	331	struct nvif_perfdom_init {
3bfdde17	332	};
96af8222	333
0f380436	334	struct nvif_perfdom_sample {
96af8222 BS	335	};
96af8222 BS	336
0f380436	337	struct nvif_perfdom_read_v0 {
96af8222 BS	338	__u8 version;
96af8222 BS	339	__u8 pad01[7];
0f380436	340	__u32 ctr[4];
96af8222	341	__u32 clk;
0f380436	342	__u8 pad04[4];
96af8222 BS	343	};
96af8222 BS	344
a532da97 BS	345
	346	/*******************************************************************************
	347	* device control
	348	******************************************************************************/
	349
	350	#define NVIF_CONTROL_PSTATE_INFO 0x00
	351	#define NVIF_CONTROL_PSTATE_ATTR 0x01
	352	#define NVIF_CONTROL_PSTATE_USER 0x02
	353
	354	struct nvif_control_pstate_info_v0 {
	355	__u8 version;
	356	__u8 count; /* out: number of power states */
	357	#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
	358	#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
	359	__s8 ustate_ac; /* out: target pstate index */
	360	__s8 ustate_dc; /* out: target pstate index */
	361	__s8 pwrsrc; /* out: current power source */
	362	#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
	363	#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
	364	__s8 pstate; /* out: current pstate index */
	365	__u8 pad06[2];
	366	};
	367
	368	struct nvif_control_pstate_attr_v0 {
	369	__u8 version;
	370	#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
	371	__s8 state; /* in: index of pstate to query
	372	* out: pstate identifier
	373	*/
	374	__u8 index; /* in: index of attribute to query
	375	* out: index of next attribute, or 0 if no more
	376	*/
	377	__u8 pad03[5];
	378	__u32 min;
	379	__u32 max;
	380	char name[32];
	381	char unit[16];
	382	};
	383
	384	struct nvif_control_pstate_user_v0 {
	385	__u8 version;
	386	#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
	387	#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
	388	__s8 ustate; /* in: pstate identifier */
	389	__s8 pwrsrc; /* in: target power source */
	390	__u8 pad03[5];
	391	};
	392
bbf8906b BS	393
	394	/*******************************************************************************
	395	* DMA FIFO channels
	396	******************************************************************************/
	397
	398	struct nv03_channel_dma_v0 {
159045cd BS	399	__u8 version;
	400	__u8 chid;
	401	__u8 pad02[2];
	402	__u32 offset;
	403	__u64 pushbuf;
	404	};
	405
	406	struct nv50_channel_dma_v0 {
bbf8906b BS	407	__u8 version;
bbf8906b BS	408	__u8 chid;
bf81df9b	409	__u8 pad02[6];
159045cd	410	__u64 vm;
bf81df9b	411	__u64 pushbuf;
bbf8906b BS	412	__u64 offset;
	413	};
	414
867920f8	415	#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
bbf8906b BS	416
	417	/*******************************************************************************
	418	* GPFIFO channels
	419	******************************************************************************/
	420
	421	struct nv50_channel_gpfifo_v0 {
	422	__u8 version;
	423	__u8 chid;
bf81df9b	424	__u8 pad02[2];
bbf8906b BS	425	__u32 ilength;
bbf8906b BS	426	__u64 ioffset;
bf81df9b	427	__u64 pushbuf;
159045cd BS	428	__u64 vm;
	429	};
	430
	431	struct fermi_channel_gpfifo_v0 {
	432	__u8 version;
	433	__u8 chid;
	434	__u8 pad02[2];
	435	__u32 ilength;
	436	__u64 ioffset;
	437	__u64 vm;
bbf8906b BS	438	};
	439
	440	struct kepler_channel_gpfifo_a_v0 {
	441	__u8 version;
	442	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
37a5d028	443	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
fd8666f7	444	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
eccf7e8a	445	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
bbf8906b BS	446	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
	447	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
	448	#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
	449	__u8 engine;
	450	__u16 chid;
bbf8906b BS	451	__u32 ilength;
bbf8906b BS	452	__u64 ioffset;
159045cd	453	__u64 vm;
bbf8906b BS	454	};
bbf8906b BS	455
bf0eb898 BS	456	/*******************************************************************************
	457	* legacy display
	458	******************************************************************************/
	459
80bc340b BS	460	#define NV04_DISP_NTFY_VBLANK 0x00
	461	#define NV04_DISP_NTFY_CONN 0x01
	462
4952b4d3 BS	463	struct nv04_disp_mthd_v0 {
	464	__u8 version;
	465	#define NV04_DISP_SCANOUTPOS 0x00
	466	__u8 method;
	467	__u8 head;
	468	__u8 pad03[5];
	469	};
	470
	471	struct nv04_disp_scanoutpos_v0 {
	472	__u8 version;
	473	__u8 pad01[7];
	474	__s64 time[2];
	475	__u16 vblanks;
	476	__u16 vblanke;
	477	__u16 vtotal;
	478	__u16 vline;
	479	__u16 hblanks;
	480	__u16 hblanke;
	481	__u16 htotal;
	482	__u16 hline;
	483	};
	484
bf0eb898 BS	485	/*******************************************************************************
	486	* display
	487	******************************************************************************/
	488
	489	#define NV50_DISP_MTHD 0x00
	490
	491	struct nv50_disp_mthd_v0 {
	492	__u8 version;
4952b4d3	493	#define NV50_DISP_SCANOUTPOS 0x00
bf0eb898 BS	494	__u8 method;
	495	__u8 head;
	496	__u8 pad03[5];
	497	};
	498
	499	struct nv50_disp_mthd_v1 {
	500	__u8 version;
	501	#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
	502	#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
	503	#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
	504	#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
	505	#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
	506	#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
	507	#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
	508	#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
	509	__u8 method;
	510	__u16 hasht;
	511	__u16 hashm;
	512	__u8 pad06[2];
	513	};
	514
	515	struct nv50_disp_dac_pwr_v0 {
	516	__u8 version;
	517	__u8 state;
	518	__u8 data;
	519	__u8 vsync;
	520	__u8 hsync;
	521	__u8 pad05[3];
	522	};
	523
c4abd317 BS	524	struct nv50_disp_dac_load_v0 {
	525	__u8 version;
	526	__u8 load;
8bd62a83 BS	527	__u8 pad02[2];
8bd62a83 BS	528	__u32 data;
c4abd317 BS	529	};
c4abd317 BS	530
d55b4af9 BS	531	struct nv50_disp_sor_pwr_v0 {
	532	__u8 version;
	533	__u8 state;
	534	__u8 pad02[6];
	535	};
	536
120b0c39 BS	537	struct nv50_disp_sor_hda_eld_v0 {
	538	__u8 version;
	539	__u8 pad01[7];
	540	__u8 data[];
	541	};
	542
e00f2235 BS	543	struct nv50_disp_sor_hdmi_pwr_v0 {
	544	__u8 version;
	545	__u8 state;
	546	__u8 max_ac_packet;
	547	__u8 rekey;
	548	__u8 pad04[4];
	549	};
	550
a3761fa2 BS	551	struct nv50_disp_sor_lvds_script_v0 {
	552	__u8 version;
	553	__u8 pad01[1];
	554	__u16 script;
	555	__u8 pad04[4];
	556	};
	557
c02ed2bf BS	558	struct nv50_disp_sor_dp_pwr_v0 {
	559	__u8 version;
	560	__u8 state;
	561	__u8 pad02[6];
	562	};
	563
67cb49c4 BS	564	struct nv50_disp_pior_pwr_v0 {
	565	__u8 version;
	566	__u8 state;
	567	__u8 type;
	568	__u8 pad03[5];
	569	};
	570
648d4dfd BS	571	/* core */
	572	struct nv50_disp_core_channel_dma_v0 {
	573	__u8 version;
bf81df9b BS	574	__u8 pad01[7];
bf81df9b BS	575	__u64 pushbuf;
648d4dfd BS	576	};
648d4dfd BS	577
b38a2322 BS	578	#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	579
648d4dfd BS	580	/* cursor immediate */
	581	struct nv50_disp_cursor_v0 {
	582	__u8 version;
	583	__u8 head;
	584	__u8 pad02[6];
	585	};
	586
b38a2322 BS	587	#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
b38a2322 BS	588
648d4dfd BS	589	/* base */
	590	struct nv50_disp_base_channel_dma_v0 {
	591	__u8 version;
648d4dfd	592	__u8 head;
bf81df9b BS	593	__u8 pad02[6];
bf81df9b BS	594	__u64 pushbuf;
648d4dfd BS	595	};
648d4dfd BS	596
b38a2322 BS	597	#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	598
648d4dfd BS	599	/* overlay */
	600	struct nv50_disp_overlay_channel_dma_v0 {
	601	__u8 version;
648d4dfd	602	__u8 head;
bf81df9b BS	603	__u8 pad02[6];
bf81df9b BS	604	__u64 pushbuf;
648d4dfd BS	605	};
648d4dfd BS	606
b38a2322 BS	607	#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
b38a2322 BS	608
648d4dfd BS	609	/* overlay immediate */
	610	struct nv50_disp_overlay_v0 {
	611	__u8 version;
	612	__u8 head;
	613	__u8 pad02[6];
	614	};
	615
b38a2322	616	#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
d01c3092	617	#endif