[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / include / nvkm / subdev / bios / pll.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __NVBIOS_PLL_H__
#define __NVBIOS_PLL_H__
/*XXX: kill me */
struct nvkm_pll_vals {
	union {
		struct {
#ifdef __BIG_ENDIAN
			uint8_t N1, M1, N2, M2;
#else
			uint8_t M1, N1, M2, N2;
#endif
		};
		struct {
			uint16_t NM1, NM2;
		} __attribute__((packed));
	};
	int log2P;

	int refclk;
};

/* these match types in pll limits table version 0x40,
 * nvkm uses them on all chipsets internally where a
 * specific pll needs to be referenced, but the exact
 * register isn't known.
 */
enum nvbios_pll_type {
	PLL_CORE   = 0x01,
	PLL_SHADER = 0x02,
	PLL_UNK03  = 0x03,
	PLL_MEMORY = 0x04,
	PLL_VDEC   = 0x05,
	PLL_UNK40  = 0x40,
	PLL_UNK41  = 0x41,
	PLL_UNK42  = 0x42,
	PLL_VPLL0  = 0x80,
	PLL_VPLL1  = 0x81,
	PLL_VPLL2  = 0x82,
	PLL_VPLL3  = 0x83,
	PLL_MAX    = 0xff
};

struct nvbios_pll {
	enum nvbios_pll_type type;
	u32 reg;
	u32 refclk;

	u8 min_p;
	u8 max_p;
	u8 bias_p;

	/*
	 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
	 * value) is no different to 6 (at least for vplls) so allowing the MNP
	 * calc to use 7 causes the generated clock to be out by a factor of 2.
	 * however, max_log2p cannot be fixed-up during parsing as the
	 * unmodified max_log2p value is still needed for setting mplls, hence
	 * an additional max_usable_log2p member
	 */
	u8 max_p_usable;

	struct {
		u32 min_freq;
		u32 max_freq;
		u32 min_inputfreq;
		u32 max_inputfreq;
		u8  min_m;
		u8  max_m;
		u8  min_n;
		u8  max_n;
	} vco1, vco2;
};

int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
70790f4f BS	2	#ifndef __NVBIOS_PLL_H__
70790f4f BS	3	#define __NVBIOS_PLL_H__
70790f4f	4	/XXX: kill me /
d390b480	5	struct nvkm_pll_vals {
70790f4f BS	6	union {
	7	struct {
	8	#ifdef __BIG_ENDIAN
	9	uint8_t N1, M1, N2, M2;
	10	#else
	11	uint8_t M1, N1, M2, N2;
	12	#endif
	13	};
	14	struct {
	15	uint16_t NM1, NM2;
	16	} __attribute__((packed));
	17	};
	18	int log2P;
	19
	20	int refclk;
	21	};
	22
70790f4f	23	/* these match types in pll limits table version 0x40,
d390b480	24	* nvkm uses them on all chipsets internally where a
70790f4f BS	25	* specific pll needs to be referenced, but the exact
	26	* register isn't known.
	27	*/
	28	enum nvbios_pll_type {
	29	PLL_CORE = 0x01,
	30	PLL_SHADER = 0x02,
	31	PLL_UNK03 = 0x03,
	32	PLL_MEMORY = 0x04,
	33	PLL_VDEC = 0x05,
	34	PLL_UNK40 = 0x40,
	35	PLL_UNK41 = 0x41,
	36	PLL_UNK42 = 0x42,
	37	PLL_VPLL0 = 0x80,
	38	PLL_VPLL1 = 0x81,
d19528a9 AT	39	PLL_VPLL2 = 0x82,
d19528a9 AT	40	PLL_VPLL3 = 0x83,
70790f4f BS	41	PLL_MAX = 0xff
	42	};
	43
	44	struct nvbios_pll {
	45	enum nvbios_pll_type type;
	46	u32 reg;
	47	u32 refclk;
	48
	49	u8 min_p;
	50	u8 max_p;
	51	u8 bias_p;
	52
	53	/*
	54	* for most pre nv50 cards setting a log2P of 7 (the common max_log2p
	55	* value) is no different to 6 (at least for vplls) so allowing the MNP
	56	* calc to use 7 causes the generated clock to be out by a factor of 2.
	57	* however, max_log2p cannot be fixed-up during parsing as the
	58	* unmodified max_log2p value is still needed for setting mplls, hence
	59	* an additional max_usable_log2p member
	60	*/
	61	u8 max_p_usable;
	62
	63	struct {
	64	u32 min_freq;
	65	u32 max_freq;
	66	u32 min_inputfreq;
	67	u32 max_inputfreq;
	68	u8 min_m;
	69	u8 max_m;
	70	u8 min_n;
	71	u8 max_n;
	72	} vco1, vco2;
	73	};
	74
d390b480	75	int nvbios_pll_parse(struct nvkm_bios , u32 type, struct nvbios_pll );
70790f4f	76	#endif