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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | ||
32 | #include "nouveau_drm.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_dma.h" | |
35 | ||
a510604d | 36 | #include <linux/log2.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
a510604d | 38 | |
415e6186 BS |
39 | int |
40 | nouveau_bo_sync_gpu(struct nouveau_bo *nvbo, struct nouveau_channel *chan) | |
41 | { | |
42 | struct nouveau_fence *prev_fence = nvbo->bo.sync_obj; | |
43 | int ret; | |
44 | ||
45 | if (!prev_fence || nouveau_fence_channel(prev_fence) == chan) | |
46 | return 0; | |
47 | ||
48 | spin_lock(&nvbo->bo.lock); | |
49 | ret = ttm_bo_wait(&nvbo->bo, false, false, false); | |
50 | spin_unlock(&nvbo->bo.lock); | |
51 | return ret; | |
52 | } | |
53 | ||
6ee73861 BS |
54 | static void |
55 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
56 | { | |
57 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 58 | struct drm_device *dev = dev_priv->dev; |
6ee73861 BS |
59 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
60 | ||
61 | ttm_bo_kunmap(&nvbo->kmap); | |
62 | ||
63 | if (unlikely(nvbo->gem)) | |
64 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
65 | ||
a0af9add FJ |
66 | if (nvbo->tile) |
67 | nv10_mem_expire_tiling(dev, nvbo->tile, NULL); | |
68 | ||
6ee73861 BS |
69 | kfree(nvbo); |
70 | } | |
71 | ||
a0af9add FJ |
72 | static void |
73 | nouveau_bo_fixup_align(struct drm_device *dev, | |
74 | uint32_t tile_mode, uint32_t tile_flags, | |
75 | int *align, int *size) | |
76 | { | |
77 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
78 | ||
79 | /* | |
80 | * Some of the tile_flags have a periodic structure of N*4096 bytes, | |
eb1dba0e MM |
81 | * align to to that as well as the page size. Align the size to the |
82 | * appropriate boundaries. This does imply that sizes are rounded up | |
83 | * 3-7 pages, so be aware of this and do not waste memory by allocating | |
84 | * many small buffers. | |
a0af9add FJ |
85 | */ |
86 | if (dev_priv->card_type == NV_50) { | |
a76fb4e8 | 87 | uint32_t block_size = dev_priv->vram_size >> 15; |
a510604d MM |
88 | int i; |
89 | ||
a0af9add FJ |
90 | switch (tile_flags) { |
91 | case 0x1800: | |
92 | case 0x2800: | |
93 | case 0x4800: | |
94 | case 0x7a00: | |
a510604d | 95 | if (is_power_of_2(block_size)) { |
a510604d MM |
96 | for (i = 1; i < 10; i++) { |
97 | *align = 12 * i * block_size; | |
98 | if (!(*align % 65536)) | |
99 | break; | |
100 | } | |
a0af9add | 101 | } else { |
a510604d MM |
102 | for (i = 1; i < 10; i++) { |
103 | *align = 8 * i * block_size; | |
104 | if (!(*align % 65536)) | |
105 | break; | |
106 | } | |
a0af9add | 107 | } |
eb1dba0e | 108 | *size = roundup(*size, *align); |
a0af9add FJ |
109 | break; |
110 | default: | |
111 | break; | |
112 | } | |
113 | ||
114 | } else { | |
115 | if (tile_mode) { | |
116 | if (dev_priv->chipset >= 0x40) { | |
117 | *align = 65536; | |
118 | *size = roundup(*size, 64 * tile_mode); | |
119 | ||
120 | } else if (dev_priv->chipset >= 0x30) { | |
121 | *align = 32768; | |
122 | *size = roundup(*size, 64 * tile_mode); | |
123 | ||
124 | } else if (dev_priv->chipset >= 0x20) { | |
125 | *align = 16384; | |
126 | *size = roundup(*size, 64 * tile_mode); | |
127 | ||
128 | } else if (dev_priv->chipset >= 0x10) { | |
129 | *align = 16384; | |
130 | *size = roundup(*size, 32 * tile_mode); | |
131 | } | |
132 | } | |
133 | } | |
134 | ||
1c7059e4 MM |
135 | /* ALIGN works only on powers of two. */ |
136 | *size = roundup(*size, PAGE_SIZE); | |
a0af9add FJ |
137 | |
138 | if (dev_priv->card_type == NV_50) { | |
1c7059e4 | 139 | *size = roundup(*size, 65536); |
a0af9add FJ |
140 | *align = max(65536, *align); |
141 | } | |
142 | } | |
143 | ||
6ee73861 BS |
144 | int |
145 | nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |
146 | int size, int align, uint32_t flags, uint32_t tile_mode, | |
147 | uint32_t tile_flags, bool no_vm, bool mappable, | |
148 | struct nouveau_bo **pnvbo) | |
149 | { | |
150 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
151 | struct nouveau_bo *nvbo; | |
8dea4a19 | 152 | int ret = 0; |
6ee73861 BS |
153 | |
154 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
155 | if (!nvbo) | |
156 | return -ENOMEM; | |
157 | INIT_LIST_HEAD(&nvbo->head); | |
158 | INIT_LIST_HEAD(&nvbo->entry); | |
159 | nvbo->mappable = mappable; | |
160 | nvbo->no_vm = no_vm; | |
161 | nvbo->tile_mode = tile_mode; | |
162 | nvbo->tile_flags = tile_flags; | |
163 | ||
a0af9add | 164 | nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); |
6ee73861 BS |
165 | align >>= PAGE_SHIFT; |
166 | ||
6ee73861 BS |
167 | nvbo->placement.fpfn = 0; |
168 | nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; | |
78ad0f7b | 169 | nouveau_bo_placement_set(nvbo, flags, 0); |
6ee73861 BS |
170 | |
171 | nvbo->channel = chan; | |
6ee73861 BS |
172 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, |
173 | ttm_bo_type_device, &nvbo->placement, align, 0, | |
174 | false, NULL, size, nouveau_bo_del_ttm); | |
6ee73861 BS |
175 | if (ret) { |
176 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
177 | return ret; | |
178 | } | |
90af89b9 | 179 | nvbo->channel = NULL; |
6ee73861 | 180 | |
6ee73861 BS |
181 | *pnvbo = nvbo; |
182 | return 0; | |
183 | } | |
184 | ||
78ad0f7b FJ |
185 | static void |
186 | set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) | |
187 | { | |
188 | *n = 0; | |
189 | ||
190 | if (type & TTM_PL_FLAG_VRAM) | |
191 | pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; | |
192 | if (type & TTM_PL_FLAG_TT) | |
193 | pl[(*n)++] = TTM_PL_FLAG_TT | flags; | |
194 | if (type & TTM_PL_FLAG_SYSTEM) | |
195 | pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; | |
196 | } | |
197 | ||
6ee73861 | 198 | void |
78ad0f7b | 199 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 200 | { |
78ad0f7b FJ |
201 | struct ttm_placement *pl = &nvbo->placement; |
202 | uint32_t flags = TTM_PL_MASK_CACHING | | |
203 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
204 | ||
205 | pl->placement = nvbo->placements; | |
206 | set_placement_list(nvbo->placements, &pl->num_placement, | |
207 | type, flags); | |
208 | ||
209 | pl->busy_placement = nvbo->busy_placements; | |
210 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
211 | type | busy, flags); | |
6ee73861 BS |
212 | } |
213 | ||
214 | int | |
215 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
216 | { | |
217 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
218 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 219 | int ret; |
6ee73861 BS |
220 | |
221 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | |
222 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | |
223 | "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, | |
224 | 1 << bo->mem.mem_type, memtype); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | if (nvbo->pin_refcnt++) | |
229 | return 0; | |
230 | ||
231 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
232 | if (ret) | |
233 | goto out; | |
234 | ||
78ad0f7b | 235 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 236 | |
9d87fa21 | 237 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
238 | if (ret == 0) { |
239 | switch (bo->mem.mem_type) { | |
240 | case TTM_PL_VRAM: | |
241 | dev_priv->fb_aper_free -= bo->mem.size; | |
242 | break; | |
243 | case TTM_PL_TT: | |
244 | dev_priv->gart_info.aper_free -= bo->mem.size; | |
245 | break; | |
246 | default: | |
247 | break; | |
248 | } | |
249 | } | |
250 | ttm_bo_unreserve(bo); | |
251 | out: | |
252 | if (unlikely(ret)) | |
253 | nvbo->pin_refcnt--; | |
254 | return ret; | |
255 | } | |
256 | ||
257 | int | |
258 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
259 | { | |
260 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
261 | struct ttm_buffer_object *bo = &nvbo->bo; | |
78ad0f7b | 262 | int ret; |
6ee73861 BS |
263 | |
264 | if (--nvbo->pin_refcnt) | |
265 | return 0; | |
266 | ||
267 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
78ad0f7b | 271 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 272 | |
9d87fa21 | 273 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false); |
6ee73861 BS |
274 | if (ret == 0) { |
275 | switch (bo->mem.mem_type) { | |
276 | case TTM_PL_VRAM: | |
277 | dev_priv->fb_aper_free += bo->mem.size; | |
278 | break; | |
279 | case TTM_PL_TT: | |
280 | dev_priv->gart_info.aper_free += bo->mem.size; | |
281 | break; | |
282 | default: | |
283 | break; | |
284 | } | |
285 | } | |
286 | ||
287 | ttm_bo_unreserve(bo); | |
288 | return ret; | |
289 | } | |
290 | ||
291 | int | |
292 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
293 | { | |
294 | int ret; | |
295 | ||
296 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
297 | if (ret) | |
298 | return ret; | |
299 | ||
300 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
301 | ttm_bo_unreserve(&nvbo->bo); | |
302 | return ret; | |
303 | } | |
304 | ||
305 | void | |
306 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
307 | { | |
308 | ttm_bo_kunmap(&nvbo->kmap); | |
309 | } | |
310 | ||
311 | u16 | |
312 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
313 | { | |
314 | bool is_iomem; | |
315 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
316 | mem = &mem[index]; | |
317 | if (is_iomem) | |
318 | return ioread16_native((void __force __iomem *)mem); | |
319 | else | |
320 | return *mem; | |
321 | } | |
322 | ||
323 | void | |
324 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
325 | { | |
326 | bool is_iomem; | |
327 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
328 | mem = &mem[index]; | |
329 | if (is_iomem) | |
330 | iowrite16_native(val, (void __force __iomem *)mem); | |
331 | else | |
332 | *mem = val; | |
333 | } | |
334 | ||
335 | u32 | |
336 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
337 | { | |
338 | bool is_iomem; | |
339 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
340 | mem = &mem[index]; | |
341 | if (is_iomem) | |
342 | return ioread32_native((void __force __iomem *)mem); | |
343 | else | |
344 | return *mem; | |
345 | } | |
346 | ||
347 | void | |
348 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
349 | { | |
350 | bool is_iomem; | |
351 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
352 | mem = &mem[index]; | |
353 | if (is_iomem) | |
354 | iowrite32_native(val, (void __force __iomem *)mem); | |
355 | else | |
356 | *mem = val; | |
357 | } | |
358 | ||
359 | static struct ttm_backend * | |
360 | nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
361 | { | |
362 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
363 | struct drm_device *dev = dev_priv->dev; | |
364 | ||
365 | switch (dev_priv->gart_info.type) { | |
b694dfb2 | 366 | #if __OS_HAS_AGP |
6ee73861 BS |
367 | case NOUVEAU_GART_AGP: |
368 | return ttm_agp_backend_init(bdev, dev->agp->bridge); | |
b694dfb2 | 369 | #endif |
6ee73861 BS |
370 | case NOUVEAU_GART_SGDMA: |
371 | return nouveau_sgdma_init_ttm(dev); | |
372 | default: | |
373 | NV_ERROR(dev, "Unknown GART type %d\n", | |
374 | dev_priv->gart_info.type); | |
375 | break; | |
376 | } | |
377 | ||
378 | return NULL; | |
379 | } | |
380 | ||
381 | static int | |
382 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
383 | { | |
384 | /* We'll do this from user space. */ | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static int | |
389 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
390 | struct ttm_mem_type_manager *man) | |
391 | { | |
392 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
393 | struct drm_device *dev = dev_priv->dev; | |
394 | ||
395 | switch (type) { | |
396 | case TTM_PL_SYSTEM: | |
397 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
398 | man->available_caching = TTM_PL_MASK_CACHING; | |
399 | man->default_caching = TTM_PL_FLAG_CACHED; | |
400 | break; | |
401 | case TTM_PL_VRAM: | |
402 | man->flags = TTM_MEMTYPE_FLAG_FIXED | | |
f32f02fd | 403 | TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
404 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
405 | TTM_PL_FLAG_WC; | |
406 | man->default_caching = TTM_PL_FLAG_WC; | |
6ee73861 BS |
407 | man->gpu_offset = dev_priv->vm_vram_base; |
408 | break; | |
409 | case TTM_PL_TT: | |
410 | switch (dev_priv->gart_info.type) { | |
411 | case NOUVEAU_GART_AGP: | |
f32f02fd | 412 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
413 | man->available_caching = TTM_PL_FLAG_UNCACHED; |
414 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
415 | break; | |
416 | case NOUVEAU_GART_SGDMA: | |
417 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
418 | TTM_MEMTYPE_FLAG_CMA; | |
419 | man->available_caching = TTM_PL_MASK_CACHING; | |
420 | man->default_caching = TTM_PL_FLAG_CACHED; | |
421 | break; | |
422 | default: | |
423 | NV_ERROR(dev, "Unknown GART type: %d\n", | |
424 | dev_priv->gart_info.type); | |
425 | return -EINVAL; | |
426 | } | |
6ee73861 BS |
427 | man->gpu_offset = dev_priv->vm_gart_base; |
428 | break; | |
429 | default: | |
430 | NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); | |
431 | return -EINVAL; | |
432 | } | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static void | |
437 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
438 | { | |
439 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
440 | ||
441 | switch (bo->mem.mem_type) { | |
22fbd538 | 442 | case TTM_PL_VRAM: |
78ad0f7b FJ |
443 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
444 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 445 | break; |
6ee73861 | 446 | default: |
78ad0f7b | 447 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
448 | break; |
449 | } | |
22fbd538 FJ |
450 | |
451 | *pl = nvbo->placement; | |
6ee73861 BS |
452 | } |
453 | ||
454 | ||
455 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
456 | * TTM_PL_{VRAM,TT} directly. | |
457 | */ | |
a0af9add | 458 | |
6ee73861 BS |
459 | static int |
460 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
9d87fa21 JG |
461 | struct nouveau_bo *nvbo, bool evict, |
462 | bool no_wait_reserve, bool no_wait_gpu, | |
6ee73861 BS |
463 | struct ttm_mem_reg *new_mem) |
464 | { | |
465 | struct nouveau_fence *fence = NULL; | |
466 | int ret; | |
467 | ||
468 | ret = nouveau_fence_new(chan, &fence, true); | |
469 | if (ret) | |
470 | return ret; | |
471 | ||
472 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, | |
311ab694 FJ |
473 | evict || (nvbo->channel && |
474 | nvbo->channel != chan), | |
475 | no_wait_reserve, no_wait_gpu, new_mem); | |
6ee73861 BS |
476 | nouveau_fence_unref((void *)&fence); |
477 | return ret; | |
478 | } | |
479 | ||
480 | static inline uint32_t | |
f1ab0cc9 BS |
481 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, |
482 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) | |
6ee73861 | 483 | { |
f1ab0cc9 BS |
484 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
485 | ||
486 | if (nvbo->no_vm) { | |
6ee73861 BS |
487 | if (mem->mem_type == TTM_PL_TT) |
488 | return NvDmaGART; | |
489 | return NvDmaVRAM; | |
490 | } | |
491 | ||
492 | if (mem->mem_type == TTM_PL_TT) | |
493 | return chan->gart_handle; | |
494 | return chan->vram_handle; | |
495 | } | |
496 | ||
497 | static int | |
f1ab0cc9 BS |
498 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
499 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
6ee73861 | 500 | { |
6ee73861 | 501 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); |
f1ab0cc9 BS |
502 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
503 | u64 length = (new_mem->num_pages << PAGE_SHIFT); | |
504 | u64 src_offset, dst_offset; | |
6ee73861 BS |
505 | int ret; |
506 | ||
6ee73861 BS |
507 | src_offset = old_mem->mm_node->start << PAGE_SHIFT; |
508 | dst_offset = new_mem->mm_node->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
509 | if (!nvbo->no_vm) { |
510 | if (old_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 511 | src_offset += dev_priv->vm_vram_base; |
6ee73861 | 512 | else |
f1ab0cc9 BS |
513 | src_offset += dev_priv->vm_gart_base; |
514 | ||
515 | if (new_mem->mem_type == TTM_PL_VRAM) | |
6ee73861 | 516 | dst_offset += dev_priv->vm_vram_base; |
f1ab0cc9 BS |
517 | else |
518 | dst_offset += dev_priv->vm_gart_base; | |
6ee73861 BS |
519 | } |
520 | ||
521 | ret = RING_SPACE(chan, 3); | |
522 | if (ret) | |
523 | return ret; | |
6ee73861 | 524 | |
f1ab0cc9 BS |
525 | BEGIN_RING(chan, NvSubM2MF, 0x0184, 2); |
526 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
527 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
528 | ||
529 | while (length) { | |
530 | u32 amount, stride, height; | |
531 | ||
532 | amount = min(length, (u64)(16 * 1024 * 1024)); | |
533 | stride = 64 * 4; | |
534 | height = amount / stride; | |
535 | ||
536 | if (new_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) { | |
537 | ret = RING_SPACE(chan, 8); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 7); | |
542 | OUT_RING (chan, 0); | |
543 | OUT_RING (chan, 0x20); | |
544 | OUT_RING (chan, stride); | |
545 | OUT_RING (chan, height); | |
546 | OUT_RING (chan, 1); | |
547 | OUT_RING (chan, 0); | |
548 | OUT_RING (chan, 0); | |
549 | } else { | |
550 | ret = RING_SPACE(chan, 2); | |
551 | if (ret) | |
552 | return ret; | |
553 | ||
554 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | |
555 | OUT_RING (chan, 1); | |
556 | } | |
557 | if (old_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) { | |
558 | ret = RING_SPACE(chan, 8); | |
559 | if (ret) | |
560 | return ret; | |
561 | ||
562 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 7); | |
563 | OUT_RING (chan, 0); | |
564 | OUT_RING (chan, 0x20); | |
565 | OUT_RING (chan, stride); | |
566 | OUT_RING (chan, height); | |
567 | OUT_RING (chan, 1); | |
568 | OUT_RING (chan, 0); | |
569 | OUT_RING (chan, 0); | |
570 | } else { | |
571 | ret = RING_SPACE(chan, 2); | |
572 | if (ret) | |
573 | return ret; | |
574 | ||
575 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); | |
576 | OUT_RING (chan, 1); | |
577 | } | |
578 | ||
579 | ret = RING_SPACE(chan, 14); | |
6ee73861 BS |
580 | if (ret) |
581 | return ret; | |
f1ab0cc9 BS |
582 | |
583 | BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); | |
584 | OUT_RING (chan, upper_32_bits(src_offset)); | |
585 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
586 | BEGIN_RING(chan, NvSubM2MF, 0x030c, 8); | |
587 | OUT_RING (chan, lower_32_bits(src_offset)); | |
588 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
589 | OUT_RING (chan, stride); | |
590 | OUT_RING (chan, stride); | |
591 | OUT_RING (chan, stride); | |
592 | OUT_RING (chan, height); | |
593 | OUT_RING (chan, 0x00000101); | |
594 | OUT_RING (chan, 0x00000000); | |
595 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); | |
596 | OUT_RING (chan, 0); | |
597 | ||
598 | length -= amount; | |
599 | src_offset += amount; | |
600 | dst_offset += amount; | |
6ee73861 BS |
601 | } |
602 | ||
f1ab0cc9 BS |
603 | return 0; |
604 | } | |
605 | ||
606 | static int | |
607 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
608 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
609 | { | |
610 | u32 src_offset = old_mem->mm_node->start << PAGE_SHIFT; | |
611 | u32 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; | |
612 | u32 page_count = new_mem->num_pages; | |
613 | int ret; | |
614 | ||
615 | ret = RING_SPACE(chan, 3); | |
616 | if (ret) | |
617 | return ret; | |
618 | ||
619 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); | |
620 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); | |
621 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
622 | ||
6ee73861 BS |
623 | page_count = new_mem->num_pages; |
624 | while (page_count) { | |
625 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
626 | ||
6ee73861 BS |
627 | ret = RING_SPACE(chan, 11); |
628 | if (ret) | |
629 | return ret; | |
f1ab0cc9 | 630 | |
6ee73861 BS |
631 | BEGIN_RING(chan, NvSubM2MF, |
632 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
f1ab0cc9 BS |
633 | OUT_RING (chan, src_offset); |
634 | OUT_RING (chan, dst_offset); | |
635 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
636 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
637 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
638 | OUT_RING (chan, line_count); | |
639 | OUT_RING (chan, 0x00000101); | |
640 | OUT_RING (chan, 0x00000000); | |
6ee73861 | 641 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 642 | OUT_RING (chan, 0); |
6ee73861 BS |
643 | |
644 | page_count -= line_count; | |
645 | src_offset += (PAGE_SIZE * line_count); | |
646 | dst_offset += (PAGE_SIZE * line_count); | |
647 | } | |
648 | ||
f1ab0cc9 BS |
649 | return 0; |
650 | } | |
651 | ||
652 | static int | |
653 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
654 | bool no_wait_reserve, bool no_wait_gpu, | |
655 | struct ttm_mem_reg *new_mem) | |
656 | { | |
657 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
658 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
659 | struct nouveau_channel *chan; | |
660 | int ret; | |
661 | ||
662 | chan = nvbo->channel; | |
663 | if (!chan || nvbo->no_vm) | |
664 | chan = dev_priv->channel; | |
665 | ||
666 | if (dev_priv->card_type < NV_50) | |
667 | ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
668 | else | |
669 | ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem); | |
670 | if (ret) | |
671 | return ret; | |
672 | ||
9d87fa21 | 673 | return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 BS |
674 | } |
675 | ||
676 | static int | |
677 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
678 | bool no_wait_reserve, bool no_wait_gpu, |
679 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
680 | { |
681 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
682 | struct ttm_placement placement; | |
683 | struct ttm_mem_reg tmp_mem; | |
684 | int ret; | |
685 | ||
686 | placement.fpfn = placement.lpfn = 0; | |
687 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 688 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
689 | |
690 | tmp_mem = *new_mem; | |
691 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 692 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
693 | if (ret) |
694 | return ret; | |
695 | ||
696 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
697 | if (ret) | |
698 | goto out; | |
699 | ||
9d87fa21 | 700 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
701 | if (ret) |
702 | goto out; | |
703 | ||
9d87fa21 | 704 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 BS |
705 | out: |
706 | if (tmp_mem.mm_node) { | |
707 | spin_lock(&bo->bdev->glob->lru_lock); | |
708 | drm_mm_put_block(tmp_mem.mm_node); | |
709 | spin_unlock(&bo->bdev->glob->lru_lock); | |
710 | } | |
711 | ||
712 | return ret; | |
713 | } | |
714 | ||
715 | static int | |
716 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
717 | bool no_wait_reserve, bool no_wait_gpu, |
718 | struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
719 | { |
720 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
721 | struct ttm_placement placement; | |
722 | struct ttm_mem_reg tmp_mem; | |
723 | int ret; | |
724 | ||
725 | placement.fpfn = placement.lpfn = 0; | |
726 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 727 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
728 | |
729 | tmp_mem = *new_mem; | |
730 | tmp_mem.mm_node = NULL; | |
9d87fa21 | 731 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu); |
6ee73861 BS |
732 | if (ret) |
733 | return ret; | |
734 | ||
9d87fa21 | 735 | ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
736 | if (ret) |
737 | goto out; | |
738 | ||
9d87fa21 | 739 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 BS |
740 | if (ret) |
741 | goto out; | |
742 | ||
743 | out: | |
744 | if (tmp_mem.mm_node) { | |
745 | spin_lock(&bo->bdev->glob->lru_lock); | |
746 | drm_mm_put_block(tmp_mem.mm_node); | |
747 | spin_unlock(&bo->bdev->glob->lru_lock); | |
748 | } | |
749 | ||
750 | return ret; | |
751 | } | |
752 | ||
753 | static int | |
a0af9add FJ |
754 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
755 | struct nouveau_tile_reg **new_tile) | |
6ee73861 BS |
756 | { |
757 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
6ee73861 | 758 | struct drm_device *dev = dev_priv->dev; |
a0af9add FJ |
759 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
760 | uint64_t offset; | |
6ee73861 BS |
761 | int ret; |
762 | ||
a0af9add FJ |
763 | if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { |
764 | /* Nothing to do. */ | |
765 | *new_tile = NULL; | |
766 | return 0; | |
767 | } | |
768 | ||
769 | offset = new_mem->mm_node->start << PAGE_SHIFT; | |
6ee73861 | 770 | |
a0af9add | 771 | if (dev_priv->card_type == NV_50) { |
6ee73861 BS |
772 | ret = nv50_mem_vm_bind_linear(dev, |
773 | offset + dev_priv->vm_vram_base, | |
774 | new_mem->size, nvbo->tile_flags, | |
775 | offset); | |
776 | if (ret) | |
777 | return ret; | |
a0af9add FJ |
778 | |
779 | } else if (dev_priv->card_type >= NV_10) { | |
780 | *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, | |
781 | nvbo->tile_mode); | |
6ee73861 BS |
782 | } |
783 | ||
a0af9add FJ |
784 | return 0; |
785 | } | |
786 | ||
787 | static void | |
788 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
789 | struct nouveau_tile_reg *new_tile, | |
790 | struct nouveau_tile_reg **old_tile) | |
791 | { | |
792 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
793 | struct drm_device *dev = dev_priv->dev; | |
794 | ||
795 | if (dev_priv->card_type >= NV_10 && | |
796 | dev_priv->card_type < NV_50) { | |
797 | if (*old_tile) | |
798 | nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); | |
799 | ||
800 | *old_tile = new_tile; | |
801 | } | |
802 | } | |
803 | ||
804 | static int | |
805 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
9d87fa21 JG |
806 | bool no_wait_reserve, bool no_wait_gpu, |
807 | struct ttm_mem_reg *new_mem) | |
a0af9add FJ |
808 | { |
809 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
810 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
811 | struct ttm_mem_reg *old_mem = &bo->mem; | |
812 | struct nouveau_tile_reg *new_tile = NULL; | |
813 | int ret = 0; | |
814 | ||
815 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); | |
816 | if (ret) | |
817 | return ret; | |
818 | ||
a0af9add | 819 | /* Fake bo copy. */ |
6ee73861 BS |
820 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
821 | BUG_ON(bo->mem.mm_node != NULL); | |
822 | bo->mem = *new_mem; | |
823 | new_mem->mm_node = NULL; | |
a0af9add | 824 | goto out; |
6ee73861 BS |
825 | } |
826 | ||
b8a6a804 BS |
827 | /* Software copy if the card isn't up and running yet. */ |
828 | if (!dev_priv->channel) { | |
829 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); | |
830 | goto out; | |
831 | } | |
832 | ||
a0af9add FJ |
833 | /* Hardware assisted copy. */ |
834 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
9d87fa21 | 835 | ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 836 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
9d87fa21 | 837 | ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add | 838 | else |
9d87fa21 | 839 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem); |
6ee73861 | 840 | |
a0af9add FJ |
841 | if (!ret) |
842 | goto out; | |
843 | ||
844 | /* Fallback to software copy. */ | |
9d87fa21 | 845 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem); |
a0af9add FJ |
846 | |
847 | out: | |
848 | if (ret) | |
849 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
850 | else | |
851 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
852 | ||
853 | return ret; | |
6ee73861 BS |
854 | } |
855 | ||
856 | static int | |
857 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
858 | { | |
859 | return 0; | |
860 | } | |
861 | ||
f32f02fd JG |
862 | static int |
863 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
864 | { | |
865 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
866 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
867 | struct drm_device *dev = dev_priv->dev; | |
868 | ||
869 | mem->bus.addr = NULL; | |
870 | mem->bus.offset = 0; | |
871 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
872 | mem->bus.base = 0; | |
873 | mem->bus.is_iomem = false; | |
874 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
875 | return -EINVAL; | |
876 | switch (mem->mem_type) { | |
877 | case TTM_PL_SYSTEM: | |
878 | /* System memory */ | |
879 | return 0; | |
880 | case TTM_PL_TT: | |
881 | #if __OS_HAS_AGP | |
882 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { | |
883 | mem->bus.offset = mem->mm_node->start << PAGE_SHIFT; | |
884 | mem->bus.base = dev_priv->gart_info.aper_base; | |
885 | mem->bus.is_iomem = true; | |
886 | } | |
887 | #endif | |
888 | break; | |
889 | case TTM_PL_VRAM: | |
890 | mem->bus.offset = mem->mm_node->start << PAGE_SHIFT; | |
01d73a69 | 891 | mem->bus.base = pci_resource_start(dev->pdev, 1); |
f32f02fd JG |
892 | mem->bus.is_iomem = true; |
893 | break; | |
894 | default: | |
895 | return -EINVAL; | |
896 | } | |
897 | return 0; | |
898 | } | |
899 | ||
900 | static void | |
901 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
902 | { | |
903 | } | |
904 | ||
905 | static int | |
906 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
907 | { | |
908 | return 0; | |
909 | } | |
910 | ||
6ee73861 BS |
911 | struct ttm_bo_driver nouveau_bo_driver = { |
912 | .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, | |
913 | .invalidate_caches = nouveau_bo_invalidate_caches, | |
914 | .init_mem_type = nouveau_bo_init_mem_type, | |
915 | .evict_flags = nouveau_bo_evict_flags, | |
916 | .move = nouveau_bo_move, | |
917 | .verify_access = nouveau_bo_verify_access, | |
918 | .sync_obj_signaled = nouveau_fence_signalled, | |
919 | .sync_obj_wait = nouveau_fence_wait, | |
920 | .sync_obj_flush = nouveau_fence_flush, | |
921 | .sync_obj_unref = nouveau_fence_unref, | |
922 | .sync_obj_ref = nouveau_fence_ref, | |
f32f02fd JG |
923 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
924 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
925 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
6ee73861 BS |
926 | }; |
927 |