[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_channel.c

/*
 * Copyright 2005-2006 Stephane Marchesin
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_ramht.h"
#include "nouveau_software.h"

static int
nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
{
	u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	/* allocate buffer object */
	ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
	if (ret)
		goto out;

	ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
	if (ret)
		goto out;

	ret = nouveau_bo_map(chan->pushbuf_bo);
	if (ret)
		goto out;

	/* create DMA object covering the entire memtype where the push
	 * buffer resides, userspace can submit its own push buffers from
	 * anywhere within the same memtype.
	 */
	chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
	if (dev_priv->card_type >= NV_50) {
		ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
					 &chan->pushbuf_vma);
		if (ret)
			goto out;

		if (dev_priv->card_type < NV_C0) {
			ret = nouveau_gpuobj_dma_new(chan,
						     NV_CLASS_DMA_IN_MEMORY, 0,
						     (1ULL << 40),
						     NV_MEM_ACCESS_RO,
						     NV_MEM_TARGET_VM,
						     &chan->pushbuf);
		}
		chan->pushbuf_base = chan->pushbuf_vma.offset;
	} else
	if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
					     dev_priv->gart_info.aper_size,
					     NV_MEM_ACCESS_RO,
					     NV_MEM_TARGET_GART,
					     &chan->pushbuf);
	} else
	if (dev_priv->card_type != NV_04) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
					     dev_priv->fb_available_size,
					     NV_MEM_ACCESS_RO,
					     NV_MEM_TARGET_VRAM,
					     &chan->pushbuf);
	} else {
		/* NV04 cmdbuf hack, from original ddx.. not sure of it's
		 * exact reason for existing :)  PCI access to cmdbuf in
		 * VRAM.
		 */
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     pci_resource_start(dev->pdev, 1),
					     dev_priv->fb_available_size,
					     NV_MEM_ACCESS_RO,
					     NV_MEM_TARGET_PCI,
					     &chan->pushbuf);
	}

out:
	if (ret) {
		NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
		nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
		nouveau_gpuobj_ref(NULL, &chan->pushbuf);
		if (chan->pushbuf_bo) {
			nouveau_bo_unmap(chan->pushbuf_bo);
			nouveau_bo_ref(NULL, &chan->pushbuf_bo);
		}
	}

	return 0;
}

/* allocates and initializes a fifo for user space consumption */
int
nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
		      struct drm_file *file_priv,
		      uint32_t vram_handle, uint32_t gart_handle)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
	struct nouveau_channel *chan;
	unsigned long flags;
	int ret, i;

	/* allocate and lock channel structure */
	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
	if (!chan)
		return -ENOMEM;
	chan->dev = dev;
	chan->file_priv = file_priv;
	chan->vram_handle = vram_handle;
	chan->gart_handle = gart_handle;

	kref_init(&chan->ref);
	atomic_set(&chan->users, 1);
	mutex_init(&chan->mutex);
	mutex_lock(&chan->mutex);

	/* allocate hw channel id */
	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
		if (!dev_priv->channels.ptr[chan->id]) {
			nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
			break;
		}
	}
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);

	if (chan->id == pfifo->channels) {
		mutex_unlock(&chan->mutex);
		kfree(chan);
		return -ENODEV;
	}

	NV_DEBUG(dev, "initialising channel %d\n", chan->id);
	INIT_LIST_HEAD(&chan->fence.pending);
	spin_lock_init(&chan->fence.lock);

	/* setup channel's memory and vm */
	ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
	if (ret) {
		NV_ERROR(dev, "gpuobj %d\n", ret);
		nouveau_channel_put(&chan);
		return ret;
	}

	/* Allocate space for per-channel fixed notifier memory */
	ret = nouveau_notifier_init_channel(chan);
	if (ret) {
		NV_ERROR(dev, "ntfy %d\n", ret);
		nouveau_channel_put(&chan);
		return ret;
	}

	/* Allocate DMA push buffer */
	ret = nouveau_channel_pushbuf_init(chan);
	if (ret) {
		NV_ERROR(dev, "pushbuf %d\n", ret);
		nouveau_channel_put(&chan);
		return ret;
	}

	nouveau_dma_init(chan);
	chan->user_put = 0x40;
	chan->user_get = 0x44;
	if (dev_priv->card_type >= NV_50)
                chan->user_get_hi = 0x60;

	/* disable the fifo caches */
	pfifo->reassign(dev, false);

	/* Construct initial RAMFC for new channel */
	ret = pfifo->create_context(chan);
	if (ret) {
		nouveau_channel_put(&chan);
		return ret;
	}

	pfifo->reassign(dev, true);

	/* Insert NOPs for NOUVEAU_DMA_SKIPS */
	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	if (ret) {
		nouveau_channel_put(&chan);
		return ret;
	}

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING  (chan, 0x00000000);
	FIRE_RING(chan);

	ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
	if (ret) {
		nouveau_channel_put(&chan);
		return ret;
	}

	ret = nouveau_fence_channel_init(chan);
	if (ret) {
		nouveau_channel_put(&chan);
		return ret;
	}

	nouveau_debugfs_channel_init(chan);

	NV_DEBUG(dev, "channel %d initialised\n", chan->id);
	if (fpriv) {
		spin_lock(&fpriv->lock);
		list_add(&chan->list, &fpriv->channels);
		spin_unlock(&fpriv->lock);
	}
	*chan_ret = chan;
	return 0;
}

struct nouveau_channel *
nouveau_channel_get_unlocked(struct nouveau_channel *ref)
{
	struct nouveau_channel *chan = NULL;

	if (likely(ref && atomic_inc_not_zero(&ref->users)))
		nouveau_channel_ref(ref, &chan);

	return chan;
}

struct nouveau_channel *
nouveau_channel_get(struct drm_file *file_priv, int id)
{
	struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
	struct nouveau_channel *chan;

	spin_lock(&fpriv->lock);
	list_for_each_entry(chan, &fpriv->channels, list) {
		if (chan->id == id) {
			chan = nouveau_channel_get_unlocked(chan);
			spin_unlock(&fpriv->lock);
			mutex_lock(&chan->mutex);
			return chan;
		}
	}
	spin_unlock(&fpriv->lock);

	return ERR_PTR(-EINVAL);
}

void
nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
{
	struct nouveau_channel *chan = *pchan;
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	unsigned long flags;
	int i;

	/* decrement the refcount, and we're done if there's still refs */
	if (likely(!atomic_dec_and_test(&chan->users))) {
		nouveau_channel_ref(NULL, pchan);
		return;
	}

	/* no one wants the channel anymore */
	NV_DEBUG(dev, "freeing channel %d\n", chan->id);
	nouveau_debugfs_channel_fini(chan);

	/* give it chance to idle */
	nouveau_channel_idle(chan);

	/* ensure all outstanding fences are signaled.  they should be if the
	 * above attempts at idling were OK, but if we failed this'll tell TTM
	 * we're done with the buffers.
	 */
	nouveau_fence_channel_fini(chan);

	/* boot it off the hardware */
	pfifo->reassign(dev, false);

	/* destroy the engine specific contexts */
	pfifo->destroy_context(chan);
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
		if (chan->engctx[i])
			dev_priv->eng[i]->context_del(chan, i);
	}

	pfifo->reassign(dev, true);

	/* aside from its resources, the channel should now be dead,
	 * remove it from the channel list
	 */
	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);

	/* destroy any resources the channel owned */
	nouveau_gpuobj_ref(NULL, &chan->pushbuf);
	if (chan->pushbuf_bo) {
		nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
		nouveau_bo_unmap(chan->pushbuf_bo);
		nouveau_bo_unpin(chan->pushbuf_bo);
		nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	}
	nouveau_ramht_ref(NULL, &chan->ramht, chan);
	nouveau_notifier_takedown_channel(chan);
	nouveau_gpuobj_channel_takedown(chan);

	nouveau_channel_ref(NULL, pchan);
}

void
nouveau_channel_put(struct nouveau_channel **pchan)
{
	mutex_unlock(&(*pchan)->mutex);
	nouveau_channel_put_unlocked(pchan);
}

static void
nouveau_channel_del(struct kref *ref)
{
	struct nouveau_channel *chan =
		container_of(ref, struct nouveau_channel, ref);

	kfree(chan);
}

void
nouveau_channel_ref(struct nouveau_channel *chan,
		    struct nouveau_channel **pchan)
{
	if (chan)
		kref_get(&chan->ref);

	if (*pchan)
		kref_put(&(*pchan)->ref, nouveau_channel_del);

	*pchan = chan;
}

void
nouveau_channel_idle(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct nouveau_fence *fence = NULL;
	int ret;

	nouveau_fence_update(chan);

	if (chan->fence.sequence != chan->fence.sequence_ack) {
		ret = nouveau_fence_new(chan, &fence, true);
		if (!ret) {
			ret = nouveau_fence_wait(fence, false, false);
			nouveau_fence_unref(&fence);
		}

		if (ret)
			NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	}
}

/* cleans up all the fifos from file_priv */
void
nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct nouveau_channel *chan;
	int i;

	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	for (i = 0; i < engine->fifo.channels; i++) {
		chan = nouveau_channel_get(file_priv, i);
		if (IS_ERR(chan))
			continue;

		list_del(&chan->list);
		atomic_dec(&chan->users);
		nouveau_channel_put(&chan);
	}
}


/***********************************
 * ioctls wrapping the functions
 ***********************************/

static int
nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_nouveau_channel_alloc *init = data;
	struct nouveau_channel *chan;
	int ret;

	if (!dev_priv->eng[NVOBJ_ENGINE_GR])
		return -ENODEV;

	if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
		return -EINVAL;

	ret = nouveau_channel_alloc(dev, &chan, file_priv,
				    init->fb_ctxdma_handle,
				    init->tt_ctxdma_handle);
	if (ret)
		return ret;
	init->channel  = chan->id;

	if (nouveau_vram_pushbuf == 0) {
		if (chan->dma.ib_max)
			init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
						NOUVEAU_GEM_DOMAIN_GART;
		else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
			init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
		else
			init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
	} else {
		init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
	}

	if (dev_priv->card_type < NV_C0) {
		init->subchan[0].handle = 0x00000000;
		init->subchan[0].grclass = 0x0000;
		init->subchan[1].handle = NvSw;
		init->subchan[1].grclass = NV_SW;
		init->nr_subchan = 2;
	}

	/* Named memory object area */
	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
				    &init->notifier_handle);

	if (ret == 0)
		atomic_inc(&chan->users); /* userspace reference */
	nouveau_channel_put(&chan);
	return ret;
}

static int
nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	struct drm_nouveau_channel_free *req = data;
	struct nouveau_channel *chan;

	chan = nouveau_channel_get(file_priv, req->channel);
	if (IS_ERR(chan))
		return PTR_ERR(chan);

	list_del(&chan->list);
	atomic_dec(&chan->users);
	nouveau_channel_put(&chan);
	return 0;
}

/***********************************
 * finally, the ioctl table
 ***********************************/

struct drm_ioctl_desc nouveau_ioctls[] = {
	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
};

int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005-2006 Stephane Marchesin
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include "drmP.h"
	26	#include "drm.h"
	27	#include "nouveau_drv.h"
	28	#include "nouveau_drm.h"
	29	#include "nouveau_dma.h"
b7cb6c01	30	#include "nouveau_ramht.h"
20abd163	31	#include "nouveau_software.h"
6ee73861 BS	32
6ee73861 BS	33	static int
dd6a46cc	34	nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
6ee73861	35	{
dd6a46cc	36	u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
6ee73861 BS	37	struct drm_device *dev = chan->dev;
6ee73861 BS	38	struct drm_nouveau_private *dev_priv = dev->dev_private;
dd6a46cc BS	39	int ret;
	40
	41	/* allocate buffer object */
22b33e8e	42	ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
dd6a46cc BS	43	if (ret)
	44	goto out;
	45
	46	ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
	47	if (ret)
	48	goto out;
6ee73861	49
dd6a46cc BS	50	ret = nouveau_bo_map(chan->pushbuf_bo);
	51	if (ret)
	52	goto out;
	53
	54	/* create DMA object covering the entire memtype where the push
	55	* buffer resides, userspace can submit its own push buffers from
	56	* anywhere within the same memtype.
	57	*/
180cc306	58	chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
d87897d4	59	if (dev_priv->card_type >= NV_50) {
ce163f69 BS	60	ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
	61	&chan->pushbuf_vma);
	62	if (ret)
	63	goto out;
	64
96545299 BS	65	if (dev_priv->card_type < NV_C0) {
	66	ret = nouveau_gpuobj_dma_new(chan,
	67	NV_CLASS_DMA_IN_MEMORY, 0,
	68	(1ULL << 40),
	69	NV_MEM_ACCESS_RO,
	70	NV_MEM_TARGET_VM,
dd6a46cc	71	&chan->pushbuf);
96545299	72	}
ce163f69	73	chan->pushbuf_base = chan->pushbuf_vma.offset;
d87897d4	74	} else
dd6a46cc	75	if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
7f4a195f BS	76	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
	77	dev_priv->gart_info.aper_size,
	78	NV_MEM_ACCESS_RO,
dd6a46cc BS	79	NV_MEM_TARGET_GART,
dd6a46cc BS	80	&chan->pushbuf);
6ee73861 BS	81	} else
	82	if (dev_priv->card_type != NV_04) {
	83	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
	84	dev_priv->fb_available_size,
7f4a195f	85	NV_MEM_ACCESS_RO,
dd6a46cc BS	86	NV_MEM_TARGET_VRAM,
dd6a46cc BS	87	&chan->pushbuf);
6ee73861 BS	88	} else {
	89	/* NV04 cmdbuf hack, from original ddx.. not sure of it's
	90	* exact reason for existing :) PCI access to cmdbuf in
	91	* VRAM.
	92	*/
	93	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
7f4a195f	94	pci_resource_start(dev->pdev, 1),
6ee73861	95	dev_priv->fb_available_size,
7f4a195f	96	NV_MEM_ACCESS_RO,
dd6a46cc BS	97	NV_MEM_TARGET_PCI,
dd6a46cc BS	98	&chan->pushbuf);
6ee73861 BS	99	}
6ee73861 BS	100
dd6a46cc	101	out:
6ee73861	102	if (ret) {
dd6a46cc	103	NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
ce163f69	104	nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
dd6a46cc BS	105	nouveau_gpuobj_ref(NULL, &chan->pushbuf);
	106	if (chan->pushbuf_bo) {
	107	nouveau_bo_unmap(chan->pushbuf_bo);
	108	nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	109	}
96545299 BS	110	}
96545299 BS	111
dd6a46cc	112	return 0;
6ee73861 BS	113	}
	114
	115	/* allocates and initializes a fifo for user space consumption */
	116	int
	117	nouveau_channel_alloc(struct drm_device dev, struct nouveau_channel *chan_ret,
	118	struct drm_file *file_priv,
cff5c133	119	uint32_t vram_handle, uint32_t gart_handle)
6ee73861 BS	120	{
6ee73861 BS	121	struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861	122	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
e8a863c1	123	struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
6ee73861	124	struct nouveau_channel *chan;
cff5c133	125	unsigned long flags;
48aca13f	126	int ret, i;
6ee73861	127
cff5c133 BS	128	/* allocate and lock channel structure */
	129	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
	130	if (!chan)
6ee73861	131	return -ENOMEM;
6ee73861	132	chan->dev = dev;
6ee73861 BS	133	chan->file_priv = file_priv;
6ee73861 BS	134	chan->vram_handle = vram_handle;
cff5c133 BS	135	chan->gart_handle = gart_handle;
cff5c133 BS	136
f091a3d4 FJ	137	kref_init(&chan->ref);
f091a3d4 FJ	138	atomic_set(&chan->users, 1);
6a6b73f2	139	mutex_init(&chan->mutex);
cff5c133	140	mutex_lock(&chan->mutex);
6ee73861	141
cff5c133 BS	142	/* allocate hw channel id */
	143	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	144	for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
	145	if (!dev_priv->channels.ptr[chan->id]) {
f091a3d4	146	nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
cff5c133 BS	147	break;
	148	}
	149	}
	150	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	151
	152	if (chan->id == pfifo->channels) {
	153	mutex_unlock(&chan->mutex);
	154	kfree(chan);
	155	return -ENODEV;
	156	}
	157
	158	NV_DEBUG(dev, "initialising channel %d\n", chan->id);
cff5c133	159	INIT_LIST_HEAD(&chan->fence.pending);
5e60ee78	160	spin_lock_init(&chan->fence.lock);
6ee73861	161
dd6a46cc BS	162	/* setup channel's memory and vm */
	163	ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
	164	if (ret) {
	165	NV_ERROR(dev, "gpuobj %d\n", ret);
cff5c133	166	nouveau_channel_put(&chan);
6ee73861 BS	167	return ret;
	168	}
	169
6ee73861 BS	170	/* Allocate space for per-channel fixed notifier memory */
	171	ret = nouveau_notifier_init_channel(chan);
	172	if (ret) {
	173	NV_ERROR(dev, "ntfy %d\n", ret);
cff5c133	174	nouveau_channel_put(&chan);
6ee73861 BS	175	return ret;
	176	}
	177
dd6a46cc BS	178	/* Allocate DMA push buffer */
dd6a46cc BS	179	ret = nouveau_channel_pushbuf_init(chan);
6ee73861	180	if (ret) {
dd6a46cc	181	NV_ERROR(dev, "pushbuf %d\n", ret);
cff5c133	182	nouveau_channel_put(&chan);
6ee73861 BS	183	return ret;
	184	}
	185
48aca13f	186	nouveau_dma_init(chan);
dd6a46cc BS	187	chan->user_put = 0x40;
dd6a46cc BS	188	chan->user_get = 0x44;
4e03b4af FJ	189	if (dev_priv->card_type >= NV_50)
4e03b4af FJ	190	chan->user_get_hi = 0x60;
6ee73861 BS	191
	192	/* disable the fifo caches */
	193	pfifo->reassign(dev, false);
	194
25985edc	195	/* Construct initial RAMFC for new channel */
6ee73861 BS	196	ret = pfifo->create_context(chan);
6ee73861 BS	197	if (ret) {
cff5c133	198	nouveau_channel_put(&chan);
6ee73861 BS	199	return ret;
	200	}
	201
	202	pfifo->reassign(dev, true);
	203
48aca13f BS	204	/* Insert NOPs for NOUVEAU_DMA_SKIPS */
	205	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	206	if (ret) {
	207	nouveau_channel_put(&chan);
	208	return ret;
	209	}
	210
	211	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	212	OUT_RING (chan, 0x00000000);
	213	FIRE_RING(chan);
	214
20abd163 BS	215	ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
	216	if (ret) {
	217	nouveau_channel_put(&chan);
	218	return ret;
	219	}
	220
48aca13f	221	ret = nouveau_fence_channel_init(chan);
6ee73861	222	if (ret) {
cff5c133	223	nouveau_channel_put(&chan);
6ee73861 BS	224	return ret;
	225	}
	226
	227	nouveau_debugfs_channel_init(chan);
	228
cff5c133	229	NV_DEBUG(dev, "channel %d initialised\n", chan->id);
e8a863c1 BS	230	if (fpriv) {
	231	spin_lock(&fpriv->lock);
	232	list_add(&chan->list, &fpriv->channels);
	233	spin_unlock(&fpriv->lock);
	234	}
6ee73861 BS	235	*chan_ret = chan;
	236	return 0;
	237	}
	238
feeb0aec FJ	239	struct nouveau_channel *
	240	nouveau_channel_get_unlocked(struct nouveau_channel *ref)
	241	{
f091a3d4	242	struct nouveau_channel *chan = NULL;
feeb0aec	243
f091a3d4 FJ	244	if (likely(ref && atomic_inc_not_zero(&ref->users)))
	245	nouveau_channel_ref(ref, &chan);
	246
	247	return chan;
feeb0aec FJ	248	}
feeb0aec FJ	249
cff5c133	250	struct nouveau_channel *
e8a863c1	251	nouveau_channel_get(struct drm_file *file_priv, int id)
cff5c133	252	{
e8a863c1	253	struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
feeb0aec	254	struct nouveau_channel *chan;
cff5c133	255
e8a863c1 BS	256	spin_lock(&fpriv->lock);
	257	list_for_each_entry(chan, &fpriv->channels, list) {
	258	if (chan->id == id) {
	259	chan = nouveau_channel_get_unlocked(chan);
	260	spin_unlock(&fpriv->lock);
	261	mutex_lock(&chan->mutex);
	262	return chan;
	263	}
cff5c133	264	}
e8a863c1	265	spin_unlock(&fpriv->lock);
cff5c133	266
e8a863c1	267	return ERR_PTR(-EINVAL);
cff5c133 BS	268	}
cff5c133 BS	269
6ee73861	270	void
feeb0aec	271	nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
6ee73861	272	{
cff5c133	273	struct nouveau_channel chan = pchan;
6ee73861 BS	274	struct drm_device *dev = chan->dev;
6ee73861 BS	275	struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861 BS	276	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
6ee73861 BS	277	unsigned long flags;
6dfdd7a6	278	int i;
6ee73861	279
cff5c133	280	/* decrement the refcount, and we're done if there's still refs */
f091a3d4 FJ	281	if (likely(!atomic_dec_and_test(&chan->users))) {
f091a3d4 FJ	282	nouveau_channel_ref(NULL, pchan);
cff5c133 BS	283	return;
cff5c133 BS	284	}
6ee73861	285
25985edc	286	/* no one wants the channel anymore */
cff5c133	287	NV_DEBUG(dev, "freeing channel %d\n", chan->id);
6ee73861 BS	288	nouveau_debugfs_channel_fini(chan);
6ee73861 BS	289
cff5c133	290	/* give it chance to idle */
6dccd311	291	nouveau_channel_idle(chan);
6ee73861	292
cff5c133	293	/* ensure all outstanding fences are signaled. they should be if the
6ee73861 BS	294	* above attempts at idling were OK, but if we failed this'll tell TTM
	295	* we're done with the buffers.
	296	*/
2730723b	297	nouveau_fence_channel_fini(chan);
6ee73861	298
cff5c133	299	/* boot it off the hardware */
6ee73861 BS	300	pfifo->reassign(dev, false);
6ee73861 BS	301
3945e475	302	/* destroy the engine specific contexts */
6ee73861	303	pfifo->destroy_context(chan);
6dfdd7a6 BS	304	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
	305	if (chan->engctx[i])
	306	dev_priv->eng[i]->context_del(chan, i);
	307	}
6ee73861 BS	308
	309	pfifo->reassign(dev, true);
	310
cff5c133 BS	311	/* aside from its resources, the channel should now be dead,
	312	* remove it from the channel list
	313	*/
	314	spin_lock_irqsave(&dev_priv->channels.lock, flags);
f091a3d4	315	nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
cff5c133 BS	316	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	317
	318	/* destroy any resources the channel owned */
a8eaebc6	319	nouveau_gpuobj_ref(NULL, &chan->pushbuf);
6ee73861	320	if (chan->pushbuf_bo) {
ce163f69	321	nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
9d59e8a1	322	nouveau_bo_unmap(chan->pushbuf_bo);
6ee73861 BS	323	nouveau_bo_unpin(chan->pushbuf_bo);
	324	nouveau_bo_ref(NULL, &chan->pushbuf_bo);
	325	}
b7cb6c01	326	nouveau_ramht_ref(NULL, &chan->ramht, chan);
6ee73861	327	nouveau_notifier_takedown_channel(chan);
b7cb6c01	328	nouveau_gpuobj_channel_takedown(chan);
6ee73861	329
f091a3d4	330	nouveau_channel_ref(NULL, pchan);
6ee73861 BS	331	}
6ee73861 BS	332
feeb0aec FJ	333	void
	334	nouveau_channel_put(struct nouveau_channel **pchan)
	335	{
	336	mutex_unlock(&(*pchan)->mutex);
	337	nouveau_channel_put_unlocked(pchan);
	338	}
	339
f091a3d4 FJ	340	static void
	341	nouveau_channel_del(struct kref *ref)
	342	{
	343	struct nouveau_channel *chan =
	344	container_of(ref, struct nouveau_channel, ref);
	345
f091a3d4 FJ	346	kfree(chan);
	347	}
	348
	349	void
	350	nouveau_channel_ref(struct nouveau_channel *chan,
	351	struct nouveau_channel **pchan)
	352	{
	353	if (chan)
	354	kref_get(&chan->ref);
	355
	356	if (*pchan)
	357	kref_put(&(*pchan)->ref, nouveau_channel_del);
	358
	359	*pchan = chan;
	360	}
	361
6dccd311 FJ	362	void
	363	nouveau_channel_idle(struct nouveau_channel *chan)
	364	{
	365	struct drm_device *dev = chan->dev;
	366	struct nouveau_fence *fence = NULL;
	367	int ret;
	368
	369	nouveau_fence_update(chan);
	370
	371	if (chan->fence.sequence != chan->fence.sequence_ack) {
	372	ret = nouveau_fence_new(chan, &fence, true);
	373	if (!ret) {
	374	ret = nouveau_fence_wait(fence, false, false);
	375	nouveau_fence_unref(&fence);
	376	}
	377
	378	if (ret)
	379	NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
	380	}
	381	}
	382
6ee73861 BS	383	/* cleans up all the fifos from file_priv */
	384	void
	385	nouveau_channel_cleanup(struct drm_device dev, struct drm_file file_priv)
	386	{
	387	struct drm_nouveau_private *dev_priv = dev->dev_private;
	388	struct nouveau_engine *engine = &dev_priv->engine;
cff5c133	389	struct nouveau_channel *chan;
6ee73861 BS	390	int i;
	391
	392	NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
	393	for (i = 0; i < engine->fifo.channels; i++) {
e8a863c1	394	chan = nouveau_channel_get(file_priv, i);
cff5c133 BS	395	if (IS_ERR(chan))
cff5c133 BS	396	continue;
6ee73861	397
e8a863c1	398	list_del(&chan->list);
f091a3d4	399	atomic_dec(&chan->users);
cff5c133	400	nouveau_channel_put(&chan);
6ee73861 BS	401	}
	402	}
	403
6ee73861 BS	404
	405	/***********************************
	406	* ioctls wrapping the functions
	407	***********************************/
	408
	409	static int
	410	nouveau_ioctl_fifo_alloc(struct drm_device dev, void data,
	411	struct drm_file *file_priv)
	412	{
	413	struct drm_nouveau_private *dev_priv = dev->dev_private;
	414	struct drm_nouveau_channel_alloc *init = data;
	415	struct nouveau_channel *chan;
	416	int ret;
	417
a82dd49f	418	if (!dev_priv->eng[NVOBJ_ENGINE_GR])
6ee73861 BS	419	return -ENODEV;
	420
	421	if (init->fb_ctxdma_handle == ~0 \|\| init->tt_ctxdma_handle == ~0)
	422	return -EINVAL;
	423
	424	ret = nouveau_channel_alloc(dev, &chan, file_priv,
	425	init->fb_ctxdma_handle,
	426	init->tt_ctxdma_handle);
	427	if (ret)
	428	return ret;
	429	init->channel = chan->id;
	430
8c06e60e BS	431	if (nouveau_vram_pushbuf == 0) {
	432	if (chan->dma.ib_max)
	433	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM \|
	434	NOUVEAU_GEM_DOMAIN_GART;
	435	else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
	436	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
	437	else
	438	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
	439	} else {
a1606a95	440	init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
8c06e60e	441	}
a1606a95	442
2a55c9a7	443	if (dev_priv->card_type < NV_C0) {
02bfc288 BS	444	init->subchan[0].handle = 0x00000000;
02bfc288 BS	445	init->subchan[0].grclass = 0x0000;
acde2d80 BS	446	init->subchan[1].handle = NvSw;
	447	init->subchan[1].grclass = NV_SW;
	448	init->nr_subchan = 2;
2a55c9a7	449	}
6ee73861 BS	450
	451	/* Named memory object area */
	452	ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
	453	&init->notifier_handle);
6ee73861	454
cff5c133	455	if (ret == 0)
f091a3d4	456	atomic_inc(&chan->users); /* userspace reference */
cff5c133 BS	457	nouveau_channel_put(&chan);
cff5c133 BS	458	return ret;
6ee73861 BS	459	}
	460
	461	static int
	462	nouveau_ioctl_fifo_free(struct drm_device dev, void data,
	463	struct drm_file *file_priv)
	464	{
cff5c133	465	struct drm_nouveau_channel_free *req = data;
6ee73861 BS	466	struct nouveau_channel *chan;
6ee73861 BS	467
e8a863c1	468	chan = nouveau_channel_get(file_priv, req->channel);
cff5c133 BS	469	if (IS_ERR(chan))
cff5c133 BS	470	return PTR_ERR(chan);
6ee73861	471
e8a863c1	472	list_del(&chan->list);
f091a3d4	473	atomic_dec(&chan->users);
cff5c133	474	nouveau_channel_put(&chan);
6ee73861 BS	475	return 0;
	476	}
	477
	478	/***********************************
	479	* finally, the ioctl table
	480	***********************************/
	481
	482	struct drm_ioctl_desc nouveau_ioctls[] = {
b12120a5 BS	483	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED\|DRM_AUTH),
	484	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED\|DRM_AUTH\|DRM_MASTER\|DRM_ROOT_ONLY),
	485	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED\|DRM_AUTH),
	486	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED\|DRM_AUTH),
	487	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED\|DRM_AUTH),
	488	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED\|DRM_AUTH),
	489	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED\|DRM_AUTH),
	490	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED\|DRM_AUTH),
	491	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED\|DRM_AUTH),
	492	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED\|DRM_AUTH),
	493	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED\|DRM_AUTH),
	494	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED\|DRM_AUTH),
6ee73861 BS	495	};
	496
	497	int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);