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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2008 Maarten Maathuis. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
77145f1c | 29 | |
fdb751ef BS |
30 | #include <nvif/class.h> |
31 | ||
6ee73861 | 32 | #include "nouveau_fbcon.h" |
1a646342 | 33 | #include "dispnv04/hw.h" |
332b242f FJ |
34 | #include "nouveau_crtc.h" |
35 | #include "nouveau_dma.h" | |
77145f1c | 36 | #include "nouveau_gem.h" |
de691855 | 37 | #include "nouveau_connector.h" |
45c4e0aa | 38 | #include "nv50_display.h" |
6ee73861 | 39 | |
ebb945a9 BS |
40 | #include "nouveau_fence.h" |
41 | ||
79ca2770 | 42 | #include <nvif/event.h> |
1d7c71a3 | 43 | |
51cb4b39 | 44 | static int |
79ca2770 | 45 | nouveau_display_vblank_handler(struct nvkm_notify *notify) |
51cb4b39 | 46 | { |
79ca2770 BS |
47 | struct nouveau_crtc *nv_crtc = |
48 | container_of(notify, typeof(*nv_crtc), vblank); | |
b12f0ae9 | 49 | drm_handle_vblank(nv_crtc->base.dev, nv_crtc->index); |
79ca2770 | 50 | return NVKM_NOTIFY_KEEP; |
51cb4b39 BS |
51 | } |
52 | ||
53 | int | |
54 | nouveau_display_vblank_enable(struct drm_device *dev, int head) | |
55 | { | |
b12f0ae9 BS |
56 | struct drm_crtc *crtc; |
57 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
58 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
59 | if (nv_crtc->index == head) { | |
79ca2770 | 60 | nvkm_notify_get(&nv_crtc->vblank); |
b12f0ae9 BS |
61 | return 0; |
62 | } | |
51cb4b39 | 63 | } |
b12f0ae9 | 64 | return -EINVAL; |
51cb4b39 BS |
65 | } |
66 | ||
67 | void | |
68 | nouveau_display_vblank_disable(struct drm_device *dev, int head) | |
69 | { | |
b12f0ae9 BS |
70 | struct drm_crtc *crtc; |
71 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
72 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
73 | if (nv_crtc->index == head) { | |
79ca2770 | 74 | nvkm_notify_put(&nv_crtc->vblank); |
b12f0ae9 BS |
75 | return; |
76 | } | |
77 | } | |
51cb4b39 BS |
78 | } |
79 | ||
d83ef853 BS |
80 | static inline int |
81 | calc(int blanks, int blanke, int total, int line) | |
82 | { | |
83 | if (blanke >= blanks) { | |
84 | if (line >= blanks) | |
85 | line -= total; | |
86 | } else { | |
87 | if (line >= blanks) | |
88 | line -= total; | |
89 | line -= blanke + 1; | |
90 | } | |
91 | return line; | |
92 | } | |
93 | ||
94 | int | |
95 | nouveau_display_scanoutpos_head(struct drm_crtc *crtc, int *vpos, int *hpos, | |
96 | ktime_t *stime, ktime_t *etime) | |
97 | { | |
98 | const u32 mthd = NV04_DISP_SCANOUTPOS + nouveau_crtc(crtc)->index; | |
99 | struct nouveau_display *disp = nouveau_display(crtc->dev); | |
100 | struct nv04_display_scanoutpos args; | |
101 | int ret, retry = 1; | |
102 | ||
103 | do { | |
0ad72863 | 104 | ret = nvif_exec(&disp->disp, mthd, &args, sizeof(args)); |
d83ef853 BS |
105 | if (ret != 0) |
106 | return 0; | |
107 | ||
108 | if (args.vline) { | |
109 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
110 | ret |= DRM_SCANOUTPOS_VALID; | |
111 | break; | |
112 | } | |
113 | ||
114 | if (retry) ndelay(crtc->linedur_ns); | |
115 | } while (retry--); | |
116 | ||
6c3252bc | 117 | *hpos = args.hline; |
d83ef853 BS |
118 | *vpos = calc(args.vblanks, args.vblanke, args.vtotal, args.vline); |
119 | if (stime) *stime = ns_to_ktime(args.time[0]); | |
120 | if (etime) *etime = ns_to_ktime(args.time[1]); | |
121 | ||
122 | if (*vpos < 0) | |
123 | ret |= DRM_SCANOUTPOS_INVBL; | |
124 | return ret; | |
125 | } | |
126 | ||
127 | int | |
128 | nouveau_display_scanoutpos(struct drm_device *dev, int head, unsigned int flags, | |
129 | int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) | |
130 | { | |
131 | struct drm_crtc *crtc; | |
132 | ||
133 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
134 | if (nouveau_crtc(crtc)->index == head) { | |
135 | return nouveau_display_scanoutpos_head(crtc, vpos, hpos, | |
136 | stime, etime); | |
137 | } | |
138 | } | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | int | |
144 | nouveau_display_vblstamp(struct drm_device *dev, int head, int *max_error, | |
145 | struct timeval *time, unsigned flags) | |
146 | { | |
147 | struct drm_crtc *crtc; | |
148 | ||
149 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
150 | if (nouveau_crtc(crtc)->index == head) { | |
151 | return drm_calc_vbltimestamp_from_scanoutpos(dev, | |
152 | head, max_error, time, flags, crtc, | |
153 | &crtc->hwmode); | |
154 | } | |
155 | } | |
156 | ||
157 | return -EINVAL; | |
158 | } | |
159 | ||
51cb4b39 BS |
160 | static void |
161 | nouveau_display_vblank_fini(struct drm_device *dev) | |
162 | { | |
b12f0ae9 | 163 | struct drm_crtc *crtc; |
51cb4b39 | 164 | |
1139ffb9 BS |
165 | drm_vblank_cleanup(dev); |
166 | ||
b12f0ae9 BS |
167 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
168 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
79ca2770 | 169 | nvkm_notify_fini(&nv_crtc->vblank); |
51cb4b39 | 170 | } |
51cb4b39 BS |
171 | } |
172 | ||
173 | static int | |
174 | nouveau_display_vblank_init(struct drm_device *dev) | |
175 | { | |
51cb4b39 | 176 | struct nouveau_drm *drm = nouveau_drm(dev); |
967e7bde | 177 | struct nouveau_disp *pdisp = nvkm_disp(&drm->device); |
b12f0ae9 BS |
178 | struct drm_crtc *crtc; |
179 | int ret; | |
51cb4b39 | 180 | |
b12f0ae9 BS |
181 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
182 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
79ca2770 BS |
183 | ret = nvkm_notify_init(&pdisp->vblank, |
184 | nouveau_display_vblank_handler, false, | |
185 | &(struct nvif_notify_head_req_v0) { | |
186 | .head = nv_crtc->index, | |
187 | }, | |
188 | sizeof(struct nvif_notify_head_req_v0), | |
189 | sizeof(struct nvif_notify_head_rep_v0), | |
190 | &nv_crtc->vblank); | |
51cb4b39 BS |
191 | if (ret) { |
192 | nouveau_display_vblank_fini(dev); | |
193 | return ret; | |
194 | } | |
195 | } | |
196 | ||
197 | ret = drm_vblank_init(dev, dev->mode_config.num_crtc); | |
198 | if (ret) { | |
199 | nouveau_display_vblank_fini(dev); | |
200 | return ret; | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
6ee73861 BS |
206 | static void |
207 | nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb) | |
208 | { | |
209 | struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); | |
ab0af559 BS |
210 | struct nouveau_display *disp = nouveau_display(drm_fb->dev); |
211 | ||
212 | if (disp->fb_dtor) | |
213 | disp->fb_dtor(drm_fb); | |
6ee73861 | 214 | |
bc9025bd | 215 | if (fb->nvbo) |
55fb74ad | 216 | drm_gem_object_unreference_unlocked(&fb->nvbo->gem); |
6ee73861 BS |
217 | |
218 | drm_framebuffer_cleanup(drm_fb); | |
219 | kfree(fb); | |
220 | } | |
221 | ||
222 | static int | |
223 | nouveau_user_framebuffer_create_handle(struct drm_framebuffer *drm_fb, | |
224 | struct drm_file *file_priv, | |
225 | unsigned int *handle) | |
226 | { | |
227 | struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); | |
228 | ||
55fb74ad | 229 | return drm_gem_handle_create(file_priv, &fb->nvbo->gem, handle); |
6ee73861 BS |
230 | } |
231 | ||
232 | static const struct drm_framebuffer_funcs nouveau_framebuffer_funcs = { | |
233 | .destroy = nouveau_user_framebuffer_destroy, | |
234 | .create_handle = nouveau_user_framebuffer_create_handle, | |
235 | }; | |
236 | ||
38651674 | 237 | int |
45c4e0aa BS |
238 | nouveau_framebuffer_init(struct drm_device *dev, |
239 | struct nouveau_framebuffer *nv_fb, | |
308e5bcb | 240 | struct drm_mode_fb_cmd2 *mode_cmd, |
45c4e0aa | 241 | struct nouveau_bo *nvbo) |
6ee73861 | 242 | { |
ab0af559 | 243 | struct nouveau_display *disp = nouveau_display(dev); |
45c4e0aa | 244 | struct drm_framebuffer *fb = &nv_fb->base; |
6ee73861 BS |
245 | int ret; |
246 | ||
45c4e0aa BS |
247 | drm_helper_mode_fill_fb_struct(fb, mode_cmd); |
248 | nv_fb->nvbo = nvbo; | |
249 | ||
c7d73f6a | 250 | ret = drm_framebuffer_init(dev, fb, &nouveau_framebuffer_funcs); |
ab0af559 | 251 | if (ret) |
c7d73f6a | 252 | return ret; |
ab0af559 BS |
253 | |
254 | if (disp->fb_ctor) { | |
255 | ret = disp->fb_ctor(fb); | |
256 | if (ret) | |
257 | disp->fb_dtor(fb); | |
c7d73f6a DV |
258 | } |
259 | ||
ab0af559 | 260 | return ret; |
6ee73861 BS |
261 | } |
262 | ||
263 | static struct drm_framebuffer * | |
264 | nouveau_user_framebuffer_create(struct drm_device *dev, | |
265 | struct drm_file *file_priv, | |
308e5bcb | 266 | struct drm_mode_fb_cmd2 *mode_cmd) |
6ee73861 | 267 | { |
38651674 | 268 | struct nouveau_framebuffer *nouveau_fb; |
6ee73861 | 269 | struct drm_gem_object *gem; |
fdfb8332 | 270 | int ret = -ENOMEM; |
6ee73861 | 271 | |
308e5bcb | 272 | gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); |
6ee73861 | 273 | if (!gem) |
cce13ff7 | 274 | return ERR_PTR(-ENOENT); |
6ee73861 | 275 | |
38651674 DA |
276 | nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL); |
277 | if (!nouveau_fb) | |
fdfb8332 | 278 | goto err_unref; |
38651674 DA |
279 | |
280 | ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem)); | |
fdfb8332 ML |
281 | if (ret) |
282 | goto err; | |
6ee73861 | 283 | |
38651674 | 284 | return &nouveau_fb->base; |
fdfb8332 ML |
285 | |
286 | err: | |
287 | kfree(nouveau_fb); | |
288 | err_unref: | |
289 | drm_gem_object_unreference(gem); | |
290 | return ERR_PTR(ret); | |
6ee73861 BS |
291 | } |
292 | ||
27d5030a | 293 | static const struct drm_mode_config_funcs nouveau_mode_config_funcs = { |
6ee73861 | 294 | .fb_create = nouveau_user_framebuffer_create, |
eb1f8e4f | 295 | .output_poll_changed = nouveau_fbcon_output_poll_changed, |
6ee73861 BS |
296 | }; |
297 | ||
b29caa58 | 298 | |
4a67d391 | 299 | struct nouveau_drm_prop_enum_list { |
de691855 | 300 | u8 gen_mask; |
b29caa58 BS |
301 | int type; |
302 | char *name; | |
303 | }; | |
304 | ||
4a67d391 | 305 | static struct nouveau_drm_prop_enum_list underscan[] = { |
92854622 BS |
306 | { 6, UNDERSCAN_AUTO, "auto" }, |
307 | { 6, UNDERSCAN_OFF, "off" }, | |
308 | { 6, UNDERSCAN_ON, "on" }, | |
de691855 | 309 | {} |
b29caa58 BS |
310 | }; |
311 | ||
4a67d391 | 312 | static struct nouveau_drm_prop_enum_list dither_mode[] = { |
de691855 BS |
313 | { 7, DITHERING_MODE_AUTO, "auto" }, |
314 | { 7, DITHERING_MODE_OFF, "off" }, | |
315 | { 1, DITHERING_MODE_ON, "on" }, | |
316 | { 6, DITHERING_MODE_STATIC2X2, "static 2x2" }, | |
317 | { 6, DITHERING_MODE_DYNAMIC2X2, "dynamic 2x2" }, | |
318 | { 4, DITHERING_MODE_TEMPORAL, "temporal" }, | |
319 | {} | |
320 | }; | |
321 | ||
4a67d391 | 322 | static struct nouveau_drm_prop_enum_list dither_depth[] = { |
de691855 BS |
323 | { 6, DITHERING_DEPTH_AUTO, "auto" }, |
324 | { 6, DITHERING_DEPTH_6BPC, "6 bpc" }, | |
325 | { 6, DITHERING_DEPTH_8BPC, "8 bpc" }, | |
326 | {} | |
327 | }; | |
328 | ||
329 | #define PROP_ENUM(p,gen,n,list) do { \ | |
4a67d391 | 330 | struct nouveau_drm_prop_enum_list *l = (list); \ |
de691855 BS |
331 | int c = 0; \ |
332 | while (l->gen_mask) { \ | |
333 | if (l->gen_mask & (1 << (gen))) \ | |
334 | c++; \ | |
335 | l++; \ | |
336 | } \ | |
337 | if (c) { \ | |
338 | p = drm_property_create(dev, DRM_MODE_PROP_ENUM, n, c); \ | |
339 | l = (list); \ | |
340 | c = 0; \ | |
341 | while (p && l->gen_mask) { \ | |
342 | if (l->gen_mask & (1 << (gen))) { \ | |
343 | drm_property_add_enum(p, c, l->type, l->name); \ | |
344 | c++; \ | |
345 | } \ | |
346 | l++; \ | |
347 | } \ | |
348 | } \ | |
349 | } while(0) | |
350 | ||
f62b27db BS |
351 | int |
352 | nouveau_display_init(struct drm_device *dev) | |
353 | { | |
77145f1c | 354 | struct nouveau_display *disp = nouveau_display(dev); |
52c4d767 | 355 | struct drm_connector *connector; |
f62b27db BS |
356 | int ret; |
357 | ||
358 | ret = disp->init(dev); | |
52c4d767 BS |
359 | if (ret) |
360 | return ret; | |
361 | ||
7df898b1 | 362 | /* enable polling for external displays */ |
52c4d767 BS |
363 | drm_kms_helper_poll_enable(dev); |
364 | ||
365 | /* enable hotplug interrupts */ | |
366 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
367 | struct nouveau_connector *conn = nouveau_connector(connector); | |
79ca2770 | 368 | nvkm_notify_get(&conn->hpd); |
f62b27db BS |
369 | } |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
374 | void | |
375 | nouveau_display_fini(struct drm_device *dev) | |
376 | { | |
77145f1c | 377 | struct nouveau_display *disp = nouveau_display(dev); |
52c4d767 | 378 | struct drm_connector *connector; |
9cba5efa MK |
379 | int head; |
380 | ||
381 | /* Make sure that drm and hw vblank irqs get properly disabled. */ | |
382 | for (head = 0; head < dev->mode_config.num_crtc; head++) | |
383 | drm_vblank_off(dev, head); | |
52c4d767 BS |
384 | |
385 | /* disable hotplug interrupts */ | |
386 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
387 | struct nouveau_connector *conn = nouveau_connector(connector); | |
79ca2770 | 388 | nvkm_notify_put(&conn->hpd); |
52c4d767 | 389 | } |
f62b27db BS |
390 | |
391 | drm_kms_helper_poll_disable(dev); | |
392 | disp->fini(dev); | |
393 | } | |
394 | ||
9c210f37 BS |
395 | static void |
396 | nouveau_display_create_properties(struct drm_device *dev) | |
27d5030a | 397 | { |
9c210f37 BS |
398 | struct nouveau_display *disp = nouveau_display(dev); |
399 | int gen; | |
de691855 | 400 | |
0ad72863 | 401 | if (disp->disp.oclass < NV50_DISP_CLASS) |
de691855 BS |
402 | gen = 0; |
403 | else | |
0ad72863 | 404 | if (disp->disp.oclass < NVD0_DISP_CLASS) |
de691855 BS |
405 | gen = 1; |
406 | else | |
407 | gen = 2; | |
408 | ||
409 | PROP_ENUM(disp->dithering_mode, gen, "dithering mode", dither_mode); | |
410 | PROP_ENUM(disp->dithering_depth, gen, "dithering depth", dither_depth); | |
411 | PROP_ENUM(disp->underscan_property, gen, "underscan", underscan); | |
b29caa58 BS |
412 | |
413 | disp->underscan_hborder_property = | |
d9bc3c02 | 414 | drm_property_create_range(dev, 0, "underscan hborder", 0, 128); |
b29caa58 BS |
415 | |
416 | disp->underscan_vborder_property = | |
d9bc3c02 | 417 | drm_property_create_range(dev, 0, "underscan vborder", 0, 128); |
b29caa58 | 418 | |
9c210f37 BS |
419 | if (gen < 1) |
420 | return; | |
df26bc9c | 421 | |
9c210f37 BS |
422 | /* -90..+90 */ |
423 | disp->vibrant_hue_property = | |
424 | drm_property_create_range(dev, 0, "vibrant hue", 0, 180); | |
425 | ||
426 | /* -100..+100 */ | |
427 | disp->color_vibrance_property = | |
428 | drm_property_create_range(dev, 0, "color vibrance", 0, 200); | |
429 | } | |
430 | ||
431 | int | |
432 | nouveau_display_create(struct drm_device *dev) | |
433 | { | |
434 | struct nouveau_drm *drm = nouveau_drm(dev); | |
9c210f37 BS |
435 | struct nouveau_display *disp; |
436 | int ret; | |
437 | ||
438 | disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL); | |
439 | if (!disp) | |
440 | return -ENOMEM; | |
441 | ||
442 | drm_mode_config_init(dev); | |
443 | drm_mode_create_scaling_mode_property(dev); | |
444 | drm_mode_create_dvi_i_properties(dev); | |
df26bc9c | 445 | |
e6ecefaa | 446 | dev->mode_config.funcs = &nouveau_mode_config_funcs; |
967e7bde | 447 | dev->mode_config.fb_base = nv_device_resource_start(nvkm_device(&drm->device), 1); |
27d5030a BS |
448 | |
449 | dev->mode_config.min_width = 0; | |
450 | dev->mode_config.min_height = 0; | |
967e7bde | 451 | if (drm->device.info.family < NV_DEVICE_INFO_V0_CELSIUS) { |
27d5030a BS |
452 | dev->mode_config.max_width = 2048; |
453 | dev->mode_config.max_height = 2048; | |
454 | } else | |
967e7bde | 455 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
27d5030a BS |
456 | dev->mode_config.max_width = 4096; |
457 | dev->mode_config.max_height = 4096; | |
458 | } else { | |
459 | dev->mode_config.max_width = 8192; | |
460 | dev->mode_config.max_height = 8192; | |
461 | } | |
462 | ||
f1377998 DA |
463 | dev->mode_config.preferred_depth = 24; |
464 | dev->mode_config.prefer_shadow = 1; | |
465 | ||
967e7bde | 466 | if (drm->device.info.chipset < 0x11) |
b9d9dcda BS |
467 | dev->mode_config.async_page_flip = false; |
468 | else | |
469 | dev->mode_config.async_page_flip = true; | |
470 | ||
f62b27db BS |
471 | drm_kms_helper_poll_init(dev); |
472 | drm_kms_helper_poll_disable(dev); | |
473 | ||
fc162088 | 474 | if (drm->vbios.dcb.entries) { |
2332b311 | 475 | static const u16 oclass[] = { |
0b681687 | 476 | GM107_DISP_CLASS, |
2332b311 BS |
477 | NVF0_DISP_CLASS, |
478 | NVE0_DISP_CLASS, | |
479 | NVD0_DISP_CLASS, | |
480 | NVA3_DISP_CLASS, | |
481 | NV94_DISP_CLASS, | |
482 | NVA0_DISP_CLASS, | |
483 | NV84_DISP_CLASS, | |
484 | NV50_DISP_CLASS, | |
485 | NV04_DISP_CLASS, | |
486 | }; | |
487 | int i; | |
488 | ||
489 | for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { | |
0ad72863 BS |
490 | ret = nvif_object_init(nvif_object(&drm->device), NULL, |
491 | NVDRM_DISPLAY, oclass[i], | |
492 | NULL, 0, &disp->disp); | |
2332b311 BS |
493 | } |
494 | ||
495 | if (ret == 0) { | |
9c210f37 | 496 | nouveau_display_create_properties(dev); |
0ad72863 | 497 | if (disp->disp.oclass < NV50_DISP_CLASS) |
2332b311 BS |
498 | ret = nv04_display_create(dev); |
499 | else | |
500 | ret = nv50_display_create(dev); | |
501 | } | |
fc162088 BS |
502 | } else { |
503 | ret = 0; | |
504 | } | |
9430738d | 505 | |
fc162088 BS |
506 | if (ret) |
507 | goto disp_create_err; | |
9430738d | 508 | |
fc162088 | 509 | if (dev->mode_config.num_crtc) { |
51cb4b39 | 510 | ret = nouveau_display_vblank_init(dev); |
fc162088 BS |
511 | if (ret) |
512 | goto vblank_err; | |
f62b27db BS |
513 | } |
514 | ||
fc162088 | 515 | nouveau_backlight_init(dev); |
5ace2c9d MS |
516 | return 0; |
517 | ||
518 | vblank_err: | |
77145f1c | 519 | disp->dtor(dev); |
5ace2c9d MS |
520 | disp_create_err: |
521 | drm_kms_helper_poll_fini(dev); | |
522 | drm_mode_config_cleanup(dev); | |
2a44e499 | 523 | return ret; |
27d5030a BS |
524 | } |
525 | ||
526 | void | |
527 | nouveau_display_destroy(struct drm_device *dev) | |
528 | { | |
77145f1c | 529 | struct nouveau_display *disp = nouveau_display(dev); |
27d5030a | 530 | |
77145f1c | 531 | nouveau_backlight_exit(dev); |
51cb4b39 | 532 | nouveau_display_vblank_fini(dev); |
f62b27db | 533 | |
d6bf2f37 BS |
534 | drm_kms_helper_poll_fini(dev); |
535 | drm_mode_config_cleanup(dev); | |
536 | ||
9430738d BS |
537 | if (disp->dtor) |
538 | disp->dtor(dev); | |
f62b27db | 539 | |
0ad72863 | 540 | nvif_object_fini(&disp->disp); |
2332b311 | 541 | |
77145f1c BS |
542 | nouveau_drm(dev)->display = NULL; |
543 | kfree(disp); | |
544 | } | |
545 | ||
546 | int | |
547 | nouveau_display_suspend(struct drm_device *dev) | |
548 | { | |
549 | struct nouveau_drm *drm = nouveau_drm(dev); | |
550 | struct drm_crtc *crtc; | |
551 | ||
552 | nouveau_display_fini(dev); | |
553 | ||
c52f4fa6 | 554 | NV_INFO(drm, "unpinning framebuffer(s)...\n"); |
77145f1c BS |
555 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
556 | struct nouveau_framebuffer *nouveau_fb; | |
557 | ||
f4510a27 | 558 | nouveau_fb = nouveau_framebuffer(crtc->primary->fb); |
77145f1c BS |
559 | if (!nouveau_fb || !nouveau_fb->nvbo) |
560 | continue; | |
561 | ||
562 | nouveau_bo_unpin(nouveau_fb->nvbo); | |
563 | } | |
564 | ||
565 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
566 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
567 | ||
568 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); | |
569 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
570 | } | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | void | |
5addcf0a | 576 | nouveau_display_repin(struct drm_device *dev) |
77145f1c BS |
577 | { |
578 | struct nouveau_drm *drm = nouveau_drm(dev); | |
579 | struct drm_crtc *crtc; | |
580 | int ret; | |
581 | ||
582 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
583 | struct nouveau_framebuffer *nouveau_fb; | |
584 | ||
f4510a27 | 585 | nouveau_fb = nouveau_framebuffer(crtc->primary->fb); |
77145f1c BS |
586 | if (!nouveau_fb || !nouveau_fb->nvbo) |
587 | continue; | |
588 | ||
589 | nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM); | |
590 | } | |
591 | ||
592 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
593 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
594 | ||
595 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
596 | if (!ret) | |
597 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
598 | if (ret) | |
599 | NV_ERROR(drm, "Could not pin/map cursor.\n"); | |
600 | } | |
5addcf0a | 601 | } |
77145f1c | 602 | |
5addcf0a DA |
603 | void |
604 | nouveau_display_resume(struct drm_device *dev) | |
605 | { | |
606 | struct drm_crtc *crtc; | |
9cba5efa MK |
607 | int head; |
608 | ||
77145f1c BS |
609 | nouveau_display_init(dev); |
610 | ||
611 | /* Force CLUT to get re-loaded during modeset */ | |
612 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
613 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
614 | ||
615 | nv_crtc->lut.depth = 0; | |
616 | } | |
617 | ||
9cba5efa MK |
618 | /* Make sure that drm and hw vblank irqs get resumed if needed. */ |
619 | for (head = 0; head < dev->mode_config.num_crtc; head++) | |
620 | drm_vblank_on(dev, head); | |
621 | ||
77145f1c BS |
622 | drm_helper_resume_force_mode(dev); |
623 | ||
624 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
625 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
626 | u32 offset = nv_crtc->cursor.nvbo->bo.offset; | |
627 | ||
628 | nv_crtc->cursor.set_offset(nv_crtc, offset); | |
629 | nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, | |
630 | nv_crtc->cursor_saved_y); | |
631 | } | |
27d5030a BS |
632 | } |
633 | ||
332b242f FJ |
634 | static int |
635 | nouveau_page_flip_emit(struct nouveau_channel *chan, | |
636 | struct nouveau_bo *old_bo, | |
637 | struct nouveau_bo *new_bo, | |
638 | struct nouveau_page_flip_state *s, | |
639 | struct nouveau_fence **pfence) | |
640 | { | |
f589be88 | 641 | struct nouveau_fence_chan *fctx = chan->fence; |
77145f1c BS |
642 | struct nouveau_drm *drm = chan->drm; |
643 | struct drm_device *dev = drm->dev; | |
332b242f FJ |
644 | unsigned long flags; |
645 | int ret; | |
646 | ||
647 | /* Queue it to the pending list */ | |
648 | spin_lock_irqsave(&dev->event_lock, flags); | |
f589be88 | 649 | list_add_tail(&s->head, &fctx->flip); |
332b242f FJ |
650 | spin_unlock_irqrestore(&dev->event_lock, flags); |
651 | ||
652 | /* Synchronize with the old framebuffer */ | |
653 | ret = nouveau_fence_sync(old_bo->bo.sync_obj, chan); | |
654 | if (ret) | |
655 | goto fail; | |
656 | ||
657 | /* Emit the pageflip */ | |
1e303c03 | 658 | ret = RING_SPACE(chan, 2); |
332b242f FJ |
659 | if (ret) |
660 | goto fail; | |
661 | ||
967e7bde | 662 | if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) |
6d597027 | 663 | BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); |
1e303c03 BS |
664 | else |
665 | BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1); | |
666 | OUT_RING (chan, 0x00000000); | |
bd2f2037 | 667 | FIRE_RING (chan); |
332b242f | 668 | |
264ce192 | 669 | ret = nouveau_fence_new(chan, false, pfence); |
332b242f FJ |
670 | if (ret) |
671 | goto fail; | |
672 | ||
673 | return 0; | |
674 | fail: | |
675 | spin_lock_irqsave(&dev->event_lock, flags); | |
676 | list_del(&s->head); | |
677 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
678 | return ret; | |
679 | } | |
680 | ||
681 | int | |
682 | nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
b9d9dcda | 683 | struct drm_pending_vblank_event *event, u32 flags) |
332b242f | 684 | { |
b9d9dcda | 685 | const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; |
332b242f | 686 | struct drm_device *dev = crtc->dev; |
77145f1c | 687 | struct nouveau_drm *drm = nouveau_drm(dev); |
f4510a27 | 688 | struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; |
332b242f FJ |
689 | struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; |
690 | struct nouveau_page_flip_state *s; | |
0ad72863 BS |
691 | struct nouveau_channel *chan; |
692 | struct nouveau_cli *cli; | |
332b242f FJ |
693 | struct nouveau_fence *fence; |
694 | int ret; | |
695 | ||
0ad72863 BS |
696 | chan = drm->channel; |
697 | if (!chan) | |
332b242f | 698 | return -ENODEV; |
0ad72863 | 699 | cli = (void *)nvif_client(&chan->device->base); |
332b242f FJ |
700 | |
701 | s = kzalloc(sizeof(*s), GFP_KERNEL); | |
702 | if (!s) | |
703 | return -ENOMEM; | |
704 | ||
d5c1e84b ML |
705 | if (new_bo != old_bo) { |
706 | ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM); | |
707 | if (ret) | |
708 | goto fail_free; | |
709 | } | |
710 | ||
0ad72863 | 711 | mutex_lock(&cli->mutex); |
d5c1e84b | 712 | |
eae389f9 BS |
713 | /* synchronise rendering channel with the kernel's channel */ |
714 | spin_lock(&new_bo->bo.bdev->fence_lock); | |
715 | fence = nouveau_fence_ref(new_bo->bo.sync_obj); | |
716 | spin_unlock(&new_bo->bo.bdev->fence_lock); | |
717 | ret = nouveau_fence_sync(fence, chan); | |
2fd04c81 | 718 | nouveau_fence_unref(&fence); |
eae389f9 | 719 | if (ret) |
09c3de13 | 720 | goto fail_unpin; |
b580c9e2 | 721 | |
07ad6ca0 | 722 | ret = ttm_bo_reserve(&old_bo->bo, true, false, false, NULL); |
060810d7 BS |
723 | if (ret) |
724 | goto fail_unpin; | |
b580c9e2 ML |
725 | |
726 | /* Initialize a page flip struct */ | |
727 | *s = (struct nouveau_page_flip_state) | |
728 | { { }, event, nouveau_crtc(crtc)->index, | |
729 | fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, | |
730 | new_bo->bo.offset }; | |
731 | ||
ba124a41 MK |
732 | /* Keep vblanks on during flip, for the target crtc of this flip */ |
733 | drm_vblank_get(dev, nouveau_crtc(crtc)->index); | |
734 | ||
332b242f | 735 | /* Emit a page flip */ |
967e7bde | 736 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { |
b9d9dcda | 737 | ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); |
060810d7 | 738 | if (ret) |
d7117e0d | 739 | goto fail_unreserve; |
78ae0ad4 BS |
740 | } else { |
741 | struct nv04_display *dispnv04 = nv04_display(dev); | |
b9d9dcda BS |
742 | int head = nouveau_crtc(crtc)->index; |
743 | ||
744 | if (swap_interval) { | |
745 | ret = RING_SPACE(chan, 8); | |
746 | if (ret) | |
747 | goto fail_unreserve; | |
748 | ||
749 | BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); | |
750 | OUT_RING (chan, 0); | |
751 | BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); | |
752 | OUT_RING (chan, head); | |
753 | BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); | |
754 | OUT_RING (chan, 0); | |
755 | BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); | |
756 | OUT_RING (chan, 0); | |
757 | } | |
758 | ||
759 | nouveau_bo_ref(new_bo, &dispnv04->image[head]); | |
d7117e0d BS |
760 | } |
761 | ||
332b242f | 762 | ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence); |
332b242f FJ |
763 | if (ret) |
764 | goto fail_unreserve; | |
0ad72863 | 765 | mutex_unlock(&cli->mutex); |
332b242f FJ |
766 | |
767 | /* Update the crtc struct and cleanup */ | |
f4510a27 | 768 | crtc->primary->fb = fb; |
332b242f | 769 | |
07ad6ca0 BS |
770 | nouveau_bo_fence(old_bo, fence); |
771 | ttm_bo_unreserve(&old_bo->bo); | |
060810d7 | 772 | if (old_bo != new_bo) |
b580c9e2 | 773 | nouveau_bo_unpin(old_bo); |
332b242f FJ |
774 | nouveau_fence_unref(&fence); |
775 | return 0; | |
776 | ||
777 | fail_unreserve: | |
ba124a41 | 778 | drm_vblank_put(dev, nouveau_crtc(crtc)->index); |
07ad6ca0 | 779 | ttm_bo_unreserve(&old_bo->bo); |
060810d7 | 780 | fail_unpin: |
0ad72863 | 781 | mutex_unlock(&cli->mutex); |
060810d7 | 782 | if (old_bo != new_bo) |
b580c9e2 | 783 | nouveau_bo_unpin(new_bo); |
332b242f FJ |
784 | fail_free: |
785 | kfree(s); | |
786 | return ret; | |
787 | } | |
788 | ||
789 | int | |
790 | nouveau_finish_page_flip(struct nouveau_channel *chan, | |
791 | struct nouveau_page_flip_state *ps) | |
792 | { | |
f589be88 | 793 | struct nouveau_fence_chan *fctx = chan->fence; |
77145f1c BS |
794 | struct nouveau_drm *drm = chan->drm; |
795 | struct drm_device *dev = drm->dev; | |
332b242f FJ |
796 | struct nouveau_page_flip_state *s; |
797 | unsigned long flags; | |
af4870e4 | 798 | int crtcid = -1; |
332b242f FJ |
799 | |
800 | spin_lock_irqsave(&dev->event_lock, flags); | |
801 | ||
f589be88 | 802 | if (list_empty(&fctx->flip)) { |
77145f1c | 803 | NV_ERROR(drm, "unexpected pageflip\n"); |
332b242f FJ |
804 | spin_unlock_irqrestore(&dev->event_lock, flags); |
805 | return -EINVAL; | |
806 | } | |
807 | ||
f589be88 | 808 | s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); |
af4870e4 MK |
809 | if (s->event) { |
810 | /* Vblank timestamps/counts are only correct on >= NV-50 */ | |
967e7bde | 811 | if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) |
af4870e4 MK |
812 | crtcid = s->crtc; |
813 | ||
814 | drm_send_vblank_event(dev, crtcid, s->event); | |
815 | } | |
332b242f | 816 | |
ba124a41 MK |
817 | /* Give up ownership of vblank for page-flipped crtc */ |
818 | drm_vblank_put(dev, s->crtc); | |
819 | ||
332b242f | 820 | list_del(&s->head); |
d7117e0d BS |
821 | if (ps) |
822 | *ps = *s; | |
332b242f FJ |
823 | kfree(s); |
824 | ||
825 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
826 | return 0; | |
827 | } | |
33dbc27f | 828 | |
f589be88 BS |
829 | int |
830 | nouveau_flip_complete(void *data) | |
831 | { | |
832 | struct nouveau_channel *chan = data; | |
77145f1c | 833 | struct nouveau_drm *drm = chan->drm; |
f589be88 BS |
834 | struct nouveau_page_flip_state state; |
835 | ||
836 | if (!nouveau_finish_page_flip(chan, &state)) { | |
967e7bde | 837 | if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { |
77145f1c | 838 | nv_set_crtc_base(drm->dev, state.crtc, state.offset + |
f589be88 BS |
839 | state.y * state.pitch + |
840 | state.x * state.bpp / 8); | |
841 | } | |
842 | } | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
33dbc27f BS |
847 | int |
848 | nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, | |
849 | struct drm_mode_create_dumb *args) | |
850 | { | |
851 | struct nouveau_bo *bo; | |
852 | int ret; | |
853 | ||
854 | args->pitch = roundup(args->width * (args->bpp / 8), 256); | |
855 | args->size = args->pitch * args->height; | |
856 | args->size = roundup(args->size, PAGE_SIZE); | |
857 | ||
610bd7da | 858 | ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo); |
33dbc27f BS |
859 | if (ret) |
860 | return ret; | |
861 | ||
55fb74ad DH |
862 | ret = drm_gem_handle_create(file_priv, &bo->gem, &args->handle); |
863 | drm_gem_object_unreference_unlocked(&bo->gem); | |
33dbc27f BS |
864 | return ret; |
865 | } | |
866 | ||
33dbc27f BS |
867 | int |
868 | nouveau_display_dumb_map_offset(struct drm_file *file_priv, | |
869 | struct drm_device *dev, | |
870 | uint32_t handle, uint64_t *poffset) | |
871 | { | |
872 | struct drm_gem_object *gem; | |
873 | ||
874 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
875 | if (gem) { | |
55fb74ad | 876 | struct nouveau_bo *bo = nouveau_gem_object(gem); |
72525b3f | 877 | *poffset = drm_vma_node_offset_addr(&bo->bo.vma_node); |
33dbc27f BS |
878 | drm_gem_object_unreference_unlocked(gem); |
879 | return 0; | |
880 | } | |
881 | ||
882 | return -ENOENT; | |
883 | } |