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94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
94580299 BS |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> | |
28 | ||
29 | #include <core/device.h> | |
30 | #include <core/client.h> | |
ebb945a9 | 31 | #include <core/gpuobj.h> |
94580299 BS |
32 | #include <core/class.h> |
33 | ||
dded35de | 34 | #include <engine/device.h> |
1d7c71a3 | 35 | #include <engine/disp.h> |
9fe72f9e | 36 | #include <engine/fifo.h> |
1d7c71a3 | 37 | |
dded35de BS |
38 | #include <subdev/vm.h> |
39 | ||
94580299 | 40 | #include "nouveau_drm.h" |
ebb945a9 | 41 | #include "nouveau_dma.h" |
77145f1c BS |
42 | #include "nouveau_ttm.h" |
43 | #include "nouveau_gem.h" | |
cb75d97e | 44 | #include "nouveau_agp.h" |
77145f1c BS |
45 | #include "nouveau_vga.h" |
46 | #include "nouveau_pm.h" | |
47 | #include "nouveau_acpi.h" | |
48 | #include "nouveau_bios.h" | |
49 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
50 | #include "nouveau_abi16.h" |
51 | #include "nouveau_fbcon.h" | |
52 | #include "nouveau_fence.h" | |
33b903e8 | 53 | #include "nouveau_debugfs.h" |
ebb945a9 | 54 | |
94580299 BS |
55 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
56 | static char *nouveau_config; | |
57 | module_param_named(config, nouveau_config, charp, 0400); | |
58 | ||
59 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
60 | static char *nouveau_debug; | |
61 | module_param_named(debug, nouveau_debug, charp, 0400); | |
62 | ||
ebb945a9 BS |
63 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
64 | static int nouveau_noaccel = 0; | |
65 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
66 | ||
9430738d BS |
67 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
68 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
69 | int nouveau_modeset = -1; | |
77145f1c BS |
70 | module_param_named(modeset, nouveau_modeset, int, 0400); |
71 | ||
72 | static struct drm_driver driver; | |
73 | ||
e4604d8f ML |
74 | static int |
75 | nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head) | |
76 | { | |
77 | struct nouveau_drm *drm = | |
78 | container_of(event, struct nouveau_drm, vblank[head]); | |
79 | drm_handle_vblank(drm->dev, head); | |
80 | return NVKM_EVENT_KEEP; | |
81 | } | |
82 | ||
1d7c71a3 BS |
83 | static int |
84 | nouveau_drm_vblank_enable(struct drm_device *dev, int head) | |
85 | { | |
86 | struct nouveau_drm *drm = nouveau_drm(dev); | |
87 | struct nouveau_disp *pdisp = nouveau_disp(drm->device); | |
e4604d8f ML |
88 | |
89 | if (WARN_ON_ONCE(head > ARRAY_SIZE(drm->vblank))) | |
90 | return -EIO; | |
91 | WARN_ON_ONCE(drm->vblank[head].func); | |
92 | drm->vblank[head].func = nouveau_drm_vblank_handler; | |
93 | nouveau_event_get(pdisp->vblank, head, &drm->vblank[head]); | |
1d7c71a3 BS |
94 | return 0; |
95 | } | |
96 | ||
97 | static void | |
98 | nouveau_drm_vblank_disable(struct drm_device *dev, int head) | |
99 | { | |
100 | struct nouveau_drm *drm = nouveau_drm(dev); | |
101 | struct nouveau_disp *pdisp = nouveau_disp(drm->device); | |
e4604d8f ML |
102 | if (drm->vblank[head].func) |
103 | nouveau_event_put(pdisp->vblank, head, &drm->vblank[head]); | |
104 | else | |
105 | WARN_ON_ONCE(1); | |
106 | drm->vblank[head].func = NULL; | |
1d7c71a3 BS |
107 | } |
108 | ||
94580299 BS |
109 | static u64 |
110 | nouveau_name(struct pci_dev *pdev) | |
111 | { | |
112 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
113 | name |= pdev->bus->number << 16; | |
114 | name |= PCI_SLOT(pdev->devfn) << 8; | |
115 | return name | PCI_FUNC(pdev->devfn); | |
116 | } | |
117 | ||
118 | static int | |
fa6df8c1 BS |
119 | nouveau_cli_create(struct pci_dev *pdev, const char *name, |
120 | int size, void **pcli) | |
94580299 BS |
121 | { |
122 | struct nouveau_cli *cli; | |
123 | int ret; | |
124 | ||
dd5700ea | 125 | *pcli = NULL; |
94580299 BS |
126 | ret = nouveau_client_create_(name, nouveau_name(pdev), nouveau_config, |
127 | nouveau_debug, size, pcli); | |
128 | cli = *pcli; | |
dd5700ea MS |
129 | if (ret) { |
130 | if (cli) | |
131 | nouveau_client_destroy(&cli->base); | |
132 | *pcli = NULL; | |
94580299 | 133 | return ret; |
dd5700ea | 134 | } |
94580299 BS |
135 | |
136 | mutex_init(&cli->mutex); | |
137 | return 0; | |
138 | } | |
139 | ||
140 | static void | |
141 | nouveau_cli_destroy(struct nouveau_cli *cli) | |
142 | { | |
143 | struct nouveau_object *client = nv_object(cli); | |
ebb945a9 | 144 | nouveau_vm_ref(NULL, &cli->base.vm, NULL); |
94580299 BS |
145 | nouveau_client_fini(&cli->base, false); |
146 | atomic_set(&client->refcount, 1); | |
147 | nouveau_object_ref(NULL, &client); | |
148 | } | |
149 | ||
ebb945a9 BS |
150 | static void |
151 | nouveau_accel_fini(struct nouveau_drm *drm) | |
152 | { | |
153 | nouveau_gpuobj_ref(NULL, &drm->notify); | |
154 | nouveau_channel_del(&drm->channel); | |
49981046 | 155 | nouveau_channel_del(&drm->cechan); |
ebb945a9 BS |
156 | if (drm->fence) |
157 | nouveau_fence(drm)->dtor(drm); | |
158 | } | |
159 | ||
160 | static void | |
161 | nouveau_accel_init(struct nouveau_drm *drm) | |
162 | { | |
163 | struct nouveau_device *device = nv_device(drm->device); | |
164 | struct nouveau_object *object; | |
49981046 | 165 | u32 arg0, arg1; |
ebb945a9 BS |
166 | int ret; |
167 | ||
9fe72f9e | 168 | if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/) |
ebb945a9 BS |
169 | return; |
170 | ||
171 | /* initialise synchronisation routines */ | |
172 | if (device->card_type < NV_10) ret = nv04_fence_create(drm); | |
60e5cb79 BS |
173 | else if (device->chipset < 0x17) ret = nv10_fence_create(drm); |
174 | else if (device->card_type < NV_50) ret = nv17_fence_create(drm); | |
ace5a9b8 | 175 | else if (device->chipset < 0x84) ret = nv50_fence_create(drm); |
ebb945a9 BS |
176 | else if (device->card_type < NV_C0) ret = nv84_fence_create(drm); |
177 | else ret = nvc0_fence_create(drm); | |
178 | if (ret) { | |
179 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
180 | nouveau_accel_fini(drm); | |
181 | return; | |
182 | } | |
183 | ||
49981046 BS |
184 | if (device->card_type >= NV_E0) { |
185 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, | |
186 | NVDRM_CHAN + 1, | |
187 | NVE0_CHANNEL_IND_ENGINE_CE0 | | |
188 | NVE0_CHANNEL_IND_ENGINE_CE1, 0, | |
189 | &drm->cechan); | |
190 | if (ret) | |
191 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
192 | ||
193 | arg0 = NVE0_CHANNEL_IND_ENGINE_GR; | |
49469800 | 194 | arg1 = 1; |
00fc6f6f BS |
195 | } else |
196 | if (device->chipset >= 0xa3 && | |
197 | device->chipset != 0xaa && | |
198 | device->chipset != 0xac) { | |
199 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, | |
200 | NVDRM_CHAN + 1, NvDmaFB, NvDmaTT, | |
201 | &drm->cechan); | |
202 | if (ret) | |
203 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
204 | ||
205 | arg0 = NvDmaFB; | |
206 | arg1 = NvDmaTT; | |
49981046 BS |
207 | } else { |
208 | arg0 = NvDmaFB; | |
209 | arg1 = NvDmaTT; | |
210 | } | |
211 | ||
ebb945a9 | 212 | ret = nouveau_channel_new(drm, &drm->client, NVDRM_DEVICE, NVDRM_CHAN, |
49981046 | 213 | arg0, arg1, &drm->channel); |
ebb945a9 BS |
214 | if (ret) { |
215 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
216 | nouveau_accel_fini(drm); | |
217 | return; | |
218 | } | |
219 | ||
220 | if (device->card_type < NV_C0) { | |
221 | ret = nouveau_gpuobj_new(drm->device, NULL, 32, 0, 0, | |
222 | &drm->notify); | |
223 | if (ret) { | |
224 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
225 | nouveau_accel_fini(drm); | |
226 | return; | |
227 | } | |
228 | ||
229 | ret = nouveau_object_new(nv_object(drm), | |
230 | drm->channel->handle, NvNotify0, | |
231 | 0x003d, &(struct nv_dma_class) { | |
232 | .flags = NV_DMA_TARGET_VRAM | | |
233 | NV_DMA_ACCESS_RDWR, | |
234 | .start = drm->notify->addr, | |
235 | .limit = drm->notify->addr + 31 | |
236 | }, sizeof(struct nv_dma_class), | |
237 | &object); | |
238 | if (ret) { | |
239 | nouveau_accel_fini(drm); | |
240 | return; | |
241 | } | |
242 | } | |
243 | ||
244 | ||
49981046 | 245 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
246 | } |
247 | ||
56550d94 GKH |
248 | static int nouveau_drm_probe(struct pci_dev *pdev, |
249 | const struct pci_device_id *pent) | |
94580299 BS |
250 | { |
251 | struct nouveau_device *device; | |
ebb945a9 BS |
252 | struct apertures_struct *aper; |
253 | bool boot = false; | |
94580299 BS |
254 | int ret; |
255 | ||
ebb945a9 BS |
256 | /* remove conflicting drivers (vesafb, efifb etc) */ |
257 | aper = alloc_apertures(3); | |
258 | if (!aper) | |
259 | return -ENOMEM; | |
260 | ||
261 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
262 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
263 | aper->count = 1; | |
264 | ||
265 | if (pci_resource_len(pdev, 2)) { | |
266 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
267 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
268 | aper->count++; | |
269 | } | |
270 | ||
271 | if (pci_resource_len(pdev, 3)) { | |
272 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
273 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
274 | aper->count++; | |
275 | } | |
276 | ||
277 | #ifdef CONFIG_X86 | |
278 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
279 | #endif | |
280 | remove_conflicting_framebuffers(aper, "nouveaufb", boot); | |
83ef7777 | 281 | kfree(aper); |
ebb945a9 | 282 | |
94580299 BS |
283 | ret = nouveau_device_create(pdev, nouveau_name(pdev), pci_name(pdev), |
284 | nouveau_config, nouveau_debug, &device); | |
285 | if (ret) | |
286 | return ret; | |
287 | ||
288 | pci_set_master(pdev); | |
289 | ||
77145f1c | 290 | ret = drm_get_pci_dev(pdev, pent, &driver); |
94580299 | 291 | if (ret) { |
ebb945a9 | 292 | nouveau_object_ref(NULL, (struct nouveau_object **)&device); |
94580299 BS |
293 | return ret; |
294 | } | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
5b8a43ae | 299 | static int |
94580299 BS |
300 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
301 | { | |
302 | struct pci_dev *pdev = dev->pdev; | |
ebb945a9 | 303 | struct nouveau_device *device; |
94580299 BS |
304 | struct nouveau_drm *drm; |
305 | int ret; | |
306 | ||
fa6df8c1 | 307 | ret = nouveau_cli_create(pdev, "DRM", sizeof(*drm), (void**)&drm); |
94580299 BS |
308 | if (ret) |
309 | return ret; | |
310 | ||
77145f1c BS |
311 | dev->dev_private = drm; |
312 | drm->dev = dev; | |
313 | ||
94580299 | 314 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 315 | spin_lock_init(&drm->tile.lock); |
94580299 | 316 | |
cb75d97e BS |
317 | /* make sure AGP controller is in a consistent state before we |
318 | * (possibly) execute vbios init tables (see nouveau_agp.h) | |
319 | */ | |
320 | if (drm_pci_device_is_agp(dev) && dev->agp) { | |
321 | /* dummy device object, doesn't init anything, but allows | |
322 | * agp code access to registers | |
323 | */ | |
324 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, | |
325 | NVDRM_DEVICE, 0x0080, | |
326 | &(struct nv_device_class) { | |
327 | .device = ~0, | |
328 | .disable = | |
329 | ~(NV_DEVICE_DISABLE_MMIO | | |
330 | NV_DEVICE_DISABLE_IDENTIFY), | |
331 | .debug0 = ~0, | |
332 | }, sizeof(struct nv_device_class), | |
333 | &drm->device); | |
334 | if (ret) | |
ebb945a9 | 335 | goto fail_device; |
cb75d97e BS |
336 | |
337 | nouveau_agp_reset(drm); | |
338 | nouveau_object_del(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE); | |
339 | } | |
340 | ||
94580299 BS |
341 | ret = nouveau_object_new(nv_object(drm), NVDRM_CLIENT, NVDRM_DEVICE, |
342 | 0x0080, &(struct nv_device_class) { | |
343 | .device = ~0, | |
344 | .disable = 0, | |
345 | .debug0 = 0, | |
346 | }, sizeof(struct nv_device_class), | |
347 | &drm->device); | |
348 | if (ret) | |
349 | goto fail_device; | |
350 | ||
77145f1c BS |
351 | /* workaround an odd issue on nvc1 by disabling the device's |
352 | * nosnoop capability. hopefully won't cause issues until a | |
353 | * better fix is found - assuming there is one... | |
354 | */ | |
ebb945a9 | 355 | device = nv_device(drm->device); |
77145f1c BS |
356 | if (nv_device(drm->device)->chipset == 0xc1) |
357 | nv_mask(device, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 358 | |
77145f1c | 359 | nouveau_vga_init(drm); |
cb75d97e BS |
360 | nouveau_agp_init(drm); |
361 | ||
ebb945a9 BS |
362 | if (device->card_type >= NV_50) { |
363 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
364 | 0x1000, &drm->client.base.vm); | |
365 | if (ret) | |
366 | goto fail_device; | |
367 | } | |
368 | ||
369 | ret = nouveau_ttm_init(drm); | |
94580299 | 370 | if (ret) |
77145f1c BS |
371 | goto fail_ttm; |
372 | ||
373 | ret = nouveau_bios_init(dev); | |
374 | if (ret) | |
375 | goto fail_bios; | |
376 | ||
77145f1c | 377 | ret = nouveau_display_create(dev); |
ebb945a9 | 378 | if (ret) |
77145f1c BS |
379 | goto fail_dispctor; |
380 | ||
381 | if (dev->mode_config.num_crtc) { | |
382 | ret = nouveau_display_init(dev); | |
383 | if (ret) | |
384 | goto fail_dispinit; | |
385 | } | |
386 | ||
387 | nouveau_pm_init(dev); | |
ebb945a9 BS |
388 | |
389 | nouveau_accel_init(drm); | |
390 | nouveau_fbcon_init(dev); | |
94580299 BS |
391 | return 0; |
392 | ||
77145f1c BS |
393 | fail_dispinit: |
394 | nouveau_display_destroy(dev); | |
395 | fail_dispctor: | |
77145f1c BS |
396 | nouveau_bios_takedown(dev); |
397 | fail_bios: | |
ebb945a9 | 398 | nouveau_ttm_fini(drm); |
77145f1c BS |
399 | fail_ttm: |
400 | nouveau_agp_fini(drm); | |
401 | nouveau_vga_fini(drm); | |
94580299 BS |
402 | fail_device: |
403 | nouveau_cli_destroy(&drm->client); | |
404 | return ret; | |
405 | } | |
406 | ||
5b8a43ae | 407 | static int |
94580299 BS |
408 | nouveau_drm_unload(struct drm_device *dev) |
409 | { | |
77145f1c | 410 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 411 | |
ebb945a9 BS |
412 | nouveau_fbcon_fini(dev); |
413 | nouveau_accel_fini(drm); | |
414 | ||
77145f1c BS |
415 | nouveau_pm_fini(dev); |
416 | ||
9430738d BS |
417 | if (dev->mode_config.num_crtc) |
418 | nouveau_display_fini(dev); | |
77145f1c BS |
419 | nouveau_display_destroy(dev); |
420 | ||
77145f1c | 421 | nouveau_bios_takedown(dev); |
94580299 | 422 | |
ebb945a9 | 423 | nouveau_ttm_fini(drm); |
cb75d97e | 424 | nouveau_agp_fini(drm); |
77145f1c | 425 | nouveau_vga_fini(drm); |
cb75d97e | 426 | |
94580299 BS |
427 | nouveau_cli_destroy(&drm->client); |
428 | return 0; | |
429 | } | |
430 | ||
431 | static void | |
432 | nouveau_drm_remove(struct pci_dev *pdev) | |
433 | { | |
77145f1c BS |
434 | struct drm_device *dev = pci_get_drvdata(pdev); |
435 | struct nouveau_drm *drm = nouveau_drm(dev); | |
ebb945a9 | 436 | struct nouveau_object *device; |
77145f1c BS |
437 | |
438 | device = drm->client.base.device; | |
439 | drm_put_dev(dev); | |
440 | ||
ebb945a9 BS |
441 | nouveau_object_ref(NULL, &device); |
442 | nouveau_object_debug(); | |
94580299 BS |
443 | } |
444 | ||
cd897837 | 445 | static int |
2d8b9ccb | 446 | nouveau_do_suspend(struct drm_device *dev) |
94580299 | 447 | { |
77145f1c | 448 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
449 | struct nouveau_cli *cli; |
450 | int ret; | |
451 | ||
9430738d BS |
452 | if (dev->mode_config.num_crtc) { |
453 | NV_INFO(drm, "suspending fbcon...\n"); | |
454 | nouveau_fbcon_set_suspend(dev, 1); | |
ebb945a9 | 455 | |
9430738d BS |
456 | NV_INFO(drm, "suspending display...\n"); |
457 | ret = nouveau_display_suspend(dev); | |
458 | if (ret) | |
459 | return ret; | |
460 | } | |
94580299 | 461 | |
ebb945a9 BS |
462 | NV_INFO(drm, "evicting buffers...\n"); |
463 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); | |
464 | ||
81dff21b BS |
465 | NV_INFO(drm, "waiting for kernel channels to go idle...\n"); |
466 | if (drm->cechan) { | |
467 | ret = nouveau_channel_idle(drm->cechan); | |
468 | if (ret) | |
469 | return ret; | |
470 | } | |
471 | ||
472 | if (drm->channel) { | |
473 | ret = nouveau_channel_idle(drm->channel); | |
474 | if (ret) | |
475 | return ret; | |
476 | } | |
477 | ||
478 | NV_INFO(drm, "suspending client object trees...\n"); | |
ebb945a9 BS |
479 | if (drm->fence && nouveau_fence(drm)->suspend) { |
480 | if (!nouveau_fence(drm)->suspend(drm)) | |
481 | return -ENOMEM; | |
482 | } | |
483 | ||
94580299 BS |
484 | list_for_each_entry(cli, &drm->clients, head) { |
485 | ret = nouveau_client_fini(&cli->base, true); | |
486 | if (ret) | |
487 | goto fail_client; | |
488 | } | |
489 | ||
81dff21b | 490 | NV_INFO(drm, "suspending kernel object tree...\n"); |
94580299 BS |
491 | ret = nouveau_client_fini(&drm->client.base, true); |
492 | if (ret) | |
493 | goto fail_client; | |
494 | ||
cb75d97e | 495 | nouveau_agp_fini(drm); |
94580299 BS |
496 | return 0; |
497 | ||
498 | fail_client: | |
499 | list_for_each_entry_continue_reverse(cli, &drm->clients, head) { | |
500 | nouveau_client_init(&cli->base); | |
501 | } | |
502 | ||
9430738d BS |
503 | if (dev->mode_config.num_crtc) { |
504 | NV_INFO(drm, "resuming display...\n"); | |
505 | nouveau_display_resume(dev); | |
506 | } | |
94580299 BS |
507 | return ret; |
508 | } | |
509 | ||
2d8b9ccb | 510 | int nouveau_pmops_suspend(struct device *dev) |
94580299 | 511 | { |
2d8b9ccb DA |
512 | struct pci_dev *pdev = to_pci_dev(dev); |
513 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
94580299 BS |
514 | int ret; |
515 | ||
2d8b9ccb | 516 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
94580299 BS |
517 | return 0; |
518 | ||
2d8b9ccb | 519 | ret = nouveau_do_suspend(drm_dev); |
94580299 BS |
520 | if (ret) |
521 | return ret; | |
2d8b9ccb DA |
522 | |
523 | pci_save_state(pdev); | |
524 | pci_disable_device(pdev); | |
525 | pci_set_power_state(pdev, PCI_D3hot); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
cd897837 | 530 | static int |
2d8b9ccb DA |
531 | nouveau_do_resume(struct drm_device *dev) |
532 | { | |
533 | struct nouveau_drm *drm = nouveau_drm(dev); | |
534 | struct nouveau_cli *cli; | |
535 | ||
536 | NV_INFO(drm, "re-enabling device...\n"); | |
94580299 | 537 | |
cb75d97e BS |
538 | nouveau_agp_reset(drm); |
539 | ||
81dff21b | 540 | NV_INFO(drm, "resuming kernel object tree...\n"); |
94580299 | 541 | nouveau_client_init(&drm->client.base); |
ebb945a9 | 542 | nouveau_agp_init(drm); |
94580299 | 543 | |
81dff21b BS |
544 | NV_INFO(drm, "resuming client object trees...\n"); |
545 | if (drm->fence && nouveau_fence(drm)->resume) | |
546 | nouveau_fence(drm)->resume(drm); | |
547 | ||
94580299 BS |
548 | list_for_each_entry(cli, &drm->clients, head) { |
549 | nouveau_client_init(&cli->base); | |
550 | } | |
cb75d97e | 551 | |
77145f1c | 552 | nouveau_run_vbios_init(dev); |
77145f1c BS |
553 | nouveau_pm_resume(dev); |
554 | ||
9430738d BS |
555 | if (dev->mode_config.num_crtc) { |
556 | NV_INFO(drm, "resuming display...\n"); | |
557 | nouveau_display_resume(dev); | |
558 | } | |
77145f1c | 559 | return 0; |
94580299 BS |
560 | } |
561 | ||
2d8b9ccb DA |
562 | int nouveau_pmops_resume(struct device *dev) |
563 | { | |
564 | struct pci_dev *pdev = to_pci_dev(dev); | |
565 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
566 | int ret; | |
567 | ||
568 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
569 | return 0; | |
570 | ||
571 | pci_set_power_state(pdev, PCI_D0); | |
572 | pci_restore_state(pdev); | |
573 | ret = pci_enable_device(pdev); | |
574 | if (ret) | |
575 | return ret; | |
576 | pci_set_master(pdev); | |
577 | ||
578 | return nouveau_do_resume(drm_dev); | |
579 | } | |
580 | ||
581 | static int nouveau_pmops_freeze(struct device *dev) | |
582 | { | |
583 | struct pci_dev *pdev = to_pci_dev(dev); | |
584 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
585 | ||
586 | return nouveau_do_suspend(drm_dev); | |
587 | } | |
588 | ||
589 | static int nouveau_pmops_thaw(struct device *dev) | |
590 | { | |
591 | struct pci_dev *pdev = to_pci_dev(dev); | |
592 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
593 | ||
594 | return nouveau_do_resume(drm_dev); | |
595 | } | |
596 | ||
597 | ||
5b8a43ae | 598 | static int |
ebb945a9 BS |
599 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
600 | { | |
601 | struct pci_dev *pdev = dev->pdev; | |
602 | struct nouveau_drm *drm = nouveau_drm(dev); | |
603 | struct nouveau_cli *cli; | |
a2896ced | 604 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
605 | int ret; |
606 | ||
a2896ced MS |
607 | get_task_comm(tmpname, current); |
608 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 BS |
609 | |
610 | ret = nouveau_cli_create(pdev, name, sizeof(*cli), (void **)&cli); | |
ebb945a9 BS |
611 | if (ret) |
612 | return ret; | |
613 | ||
614 | if (nv_device(drm->device)->card_type >= NV_50) { | |
615 | ret = nouveau_vm_new(nv_device(drm->device), 0, (1ULL << 40), | |
616 | 0x1000, &cli->base.vm); | |
617 | if (ret) { | |
618 | nouveau_cli_destroy(cli); | |
619 | return ret; | |
620 | } | |
621 | } | |
622 | ||
623 | fpriv->driver_priv = cli; | |
624 | ||
625 | mutex_lock(&drm->client.mutex); | |
626 | list_add(&cli->head, &drm->clients); | |
627 | mutex_unlock(&drm->client.mutex); | |
628 | return 0; | |
629 | } | |
630 | ||
5b8a43ae | 631 | static void |
ebb945a9 BS |
632 | nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv) |
633 | { | |
634 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
635 | struct nouveau_drm *drm = nouveau_drm(dev); | |
636 | ||
637 | if (cli->abi16) | |
638 | nouveau_abi16_fini(cli->abi16); | |
639 | ||
640 | mutex_lock(&drm->client.mutex); | |
641 | list_del(&cli->head); | |
642 | mutex_unlock(&drm->client.mutex); | |
643 | } | |
644 | ||
5b8a43ae | 645 | static void |
ebb945a9 BS |
646 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
647 | { | |
648 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
649 | nouveau_cli_destroy(cli); | |
650 | } | |
651 | ||
baa70943 | 652 | static const struct drm_ioctl_desc |
77145f1c BS |
653 | nouveau_ioctls[] = { |
654 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH), | |
655 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
656 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH), | |
657 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH), | |
658 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH), | |
659 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH), | |
660 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH), | |
661 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH), | |
662 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH), | |
663 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH), | |
664 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH), | |
665 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH), | |
666 | }; | |
667 | ||
668 | static const struct file_operations | |
669 | nouveau_driver_fops = { | |
670 | .owner = THIS_MODULE, | |
671 | .open = drm_open, | |
672 | .release = drm_release, | |
673 | .unlocked_ioctl = drm_ioctl, | |
674 | .mmap = nouveau_ttm_mmap, | |
675 | .poll = drm_poll, | |
77145f1c BS |
676 | .read = drm_read, |
677 | #if defined(CONFIG_COMPAT) | |
678 | .compat_ioctl = nouveau_compat_ioctl, | |
679 | #endif | |
680 | .llseek = noop_llseek, | |
681 | }; | |
682 | ||
683 | static struct drm_driver | |
684 | driver = { | |
685 | .driver_features = | |
4cb4ea39 | 686 | DRIVER_USE_AGP | |
0fa9061a | 687 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME, |
77145f1c BS |
688 | |
689 | .load = nouveau_drm_load, | |
690 | .unload = nouveau_drm_unload, | |
691 | .open = nouveau_drm_open, | |
692 | .preclose = nouveau_drm_preclose, | |
693 | .postclose = nouveau_drm_postclose, | |
694 | .lastclose = nouveau_vga_lastclose, | |
695 | ||
33b903e8 MS |
696 | #if defined(CONFIG_DEBUG_FS) |
697 | .debugfs_init = nouveau_debugfs_init, | |
698 | .debugfs_cleanup = nouveau_debugfs_takedown, | |
699 | #endif | |
700 | ||
77145f1c | 701 | .get_vblank_counter = drm_vblank_count, |
1d7c71a3 BS |
702 | .enable_vblank = nouveau_drm_vblank_enable, |
703 | .disable_vblank = nouveau_drm_vblank_disable, | |
77145f1c BS |
704 | |
705 | .ioctls = nouveau_ioctls, | |
baa70943 | 706 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
707 | .fops = &nouveau_driver_fops, |
708 | ||
709 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
710 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
711 | .gem_prime_export = drm_gem_prime_export, |
712 | .gem_prime_import = drm_gem_prime_import, | |
713 | .gem_prime_pin = nouveau_gem_prime_pin, | |
1af7c7dd | 714 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
715 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
716 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
717 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
718 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c BS |
719 | |
720 | .gem_init_object = nouveau_gem_object_new, | |
721 | .gem_free_object = nouveau_gem_object_del, | |
722 | .gem_open_object = nouveau_gem_object_open, | |
723 | .gem_close_object = nouveau_gem_object_close, | |
724 | ||
725 | .dumb_create = nouveau_display_dumb_create, | |
726 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
43387b37 | 727 | .dumb_destroy = drm_gem_dumb_destroy, |
77145f1c BS |
728 | |
729 | .name = DRIVER_NAME, | |
730 | .desc = DRIVER_DESC, | |
731 | #ifdef GIT_REVISION | |
732 | .date = GIT_REVISION, | |
733 | #else | |
734 | .date = DRIVER_DATE, | |
735 | #endif | |
736 | .major = DRIVER_MAJOR, | |
737 | .minor = DRIVER_MINOR, | |
738 | .patchlevel = DRIVER_PATCHLEVEL, | |
739 | }; | |
740 | ||
94580299 BS |
741 | static struct pci_device_id |
742 | nouveau_drm_pci_table[] = { | |
743 | { | |
744 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
745 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
746 | .class_mask = 0xff << 16, | |
747 | }, | |
748 | { | |
749 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
750 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
751 | .class_mask = 0xff << 16, | |
752 | }, | |
753 | {} | |
754 | }; | |
755 | ||
2d8b9ccb DA |
756 | static const struct dev_pm_ops nouveau_pm_ops = { |
757 | .suspend = nouveau_pmops_suspend, | |
758 | .resume = nouveau_pmops_resume, | |
759 | .freeze = nouveau_pmops_freeze, | |
760 | .thaw = nouveau_pmops_thaw, | |
761 | .poweroff = nouveau_pmops_freeze, | |
762 | .restore = nouveau_pmops_resume, | |
763 | }; | |
764 | ||
94580299 BS |
765 | static struct pci_driver |
766 | nouveau_drm_pci_driver = { | |
767 | .name = "nouveau", | |
768 | .id_table = nouveau_drm_pci_table, | |
769 | .probe = nouveau_drm_probe, | |
770 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 771 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
772 | }; |
773 | ||
774 | static int __init | |
775 | nouveau_drm_init(void) | |
776 | { | |
77145f1c BS |
777 | if (nouveau_modeset == -1) { |
778 | #ifdef CONFIG_VGA_CONSOLE | |
779 | if (vgacon_text_force()) | |
780 | nouveau_modeset = 0; | |
77145f1c | 781 | #endif |
77145f1c BS |
782 | } |
783 | ||
784 | if (!nouveau_modeset) | |
785 | return 0; | |
786 | ||
787 | nouveau_register_dsm_handler(); | |
788 | return drm_pci_init(&driver, &nouveau_drm_pci_driver); | |
94580299 BS |
789 | } |
790 | ||
791 | static void __exit | |
792 | nouveau_drm_exit(void) | |
793 | { | |
77145f1c BS |
794 | if (!nouveau_modeset) |
795 | return; | |
796 | ||
797 | drm_pci_exit(&driver, &nouveau_drm_pci_driver); | |
798 | nouveau_unregister_dsm_handler(); | |
94580299 BS |
799 | } |
800 | ||
801 | module_init(nouveau_drm_init); | |
802 | module_exit(nouveau_drm_exit); | |
803 | ||
804 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
805 | MODULE_AUTHOR(DRIVER_AUTHOR); |
806 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 807 | MODULE_LICENSE("GPL and additional rights"); |