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drm/nouveau/mmu: remove old vmm frontend
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CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
c5fd936e 26#include <linux/delay.h>
94580299
BS
27#include <linux/module.h>
28#include <linux/pci.h>
5addcf0a
DA
29#include <linux/pm_runtime.h>
30#include <linux/vga_switcheroo.h>
fdb751ef 31
ae95621b
MY
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
fdb751ef 34
ebb945a9 35#include <core/gpuobj.h>
c33e05a1 36#include <core/option.h>
7974dd1b
BS
37#include <core/pci.h>
38#include <core/tegra.h>
94580299 39
04b88677
BS
40#include <nvif/driver.h>
41
923bc416 42#include <nvif/class.h>
845f2725 43#include <nvif/cl0002.h>
8ed1730c 44#include <nvif/cla06f.h>
538b269b
BS
45#include <nvif/if0004.h>
46
4dc28134 47#include "nouveau_drv.h"
ebb945a9 48#include "nouveau_dma.h"
77145f1c
BS
49#include "nouveau_ttm.h"
50#include "nouveau_gem.h"
77145f1c 51#include "nouveau_vga.h"
8d021d71 52#include "nouveau_led.h"
b9ed919f 53#include "nouveau_hwmon.h"
77145f1c
BS
54#include "nouveau_acpi.h"
55#include "nouveau_bios.h"
56#include "nouveau_ioctl.h"
ebb945a9
BS
57#include "nouveau_abi16.h"
58#include "nouveau_fbcon.h"
59#include "nouveau_fence.h"
33b903e8 60#include "nouveau_debugfs.h"
27111a23 61#include "nouveau_usif.h"
703fa264 62#include "nouveau_connector.h"
055a65d5 63#include "nouveau_platform.h"
ebb945a9 64
94580299
BS
65MODULE_PARM_DESC(config, "option string to pass to driver core");
66static char *nouveau_config;
67module_param_named(config, nouveau_config, charp, 0400);
68
69MODULE_PARM_DESC(debug, "debug string to pass to driver core");
70static char *nouveau_debug;
71module_param_named(debug, nouveau_debug, charp, 0400);
72
ebb945a9
BS
73MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
74static int nouveau_noaccel = 0;
75module_param_named(noaccel, nouveau_noaccel, int, 0400);
76
9430738d
BS
77MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
78 "0 = disabled, 1 = enabled, 2 = headless)");
79int nouveau_modeset = -1;
77145f1c
BS
80module_param_named(modeset, nouveau_modeset, int, 0400);
81
5addcf0a 82MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
321f5c5f 83static int nouveau_runtime_pm = -1;
5addcf0a
DA
84module_param_named(runpm, nouveau_runtime_pm, int, 0400);
85
915b4d11
DH
86static struct drm_driver driver_stub;
87static struct drm_driver driver_pci;
88static struct drm_driver driver_platform;
77145f1c 89
94580299 90static u64
420b9469 91nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
92{
93 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
94 name |= pdev->bus->number << 16;
95 name |= PCI_SLOT(pdev->devfn) << 8;
96 return name | PCI_FUNC(pdev->devfn);
97}
98
420b9469
AC
99static u64
100nouveau_platform_name(struct platform_device *platformdev)
101{
102 return platformdev->id;
103}
104
105static u64
106nouveau_name(struct drm_device *dev)
107{
108 if (dev->pdev)
109 return nouveau_pci_name(dev->pdev);
110 else
76adb460 111 return nouveau_platform_name(to_platform_device(dev->dev));
420b9469
AC
112}
113
814a2324
BS
114static inline bool
115nouveau_cli_work_ready(struct dma_fence *fence, bool wait)
116{
117 if (!dma_fence_is_signaled(fence)) {
118 if (!wait)
119 return false;
120 WARN_ON(dma_fence_wait_timeout(fence, false, 2 * HZ) <= 0);
121 }
122 dma_fence_put(fence);
123 return true;
124}
125
126static void
127nouveau_cli_work_flush(struct nouveau_cli *cli, bool wait)
128{
129 struct nouveau_cli_work *work, *wtmp;
130 mutex_lock(&cli->lock);
131 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
132 if (!work->fence || nouveau_cli_work_ready(work->fence, wait)) {
133 list_del(&work->head);
134 work->func(work);
135 }
136 }
137 mutex_unlock(&cli->lock);
138}
139
140static void
141nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
142{
143 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
144 schedule_work(&work->cli->work);
145}
146
147void
148nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
149 struct nouveau_cli_work *work)
150{
151 work->fence = dma_fence_get(fence);
152 work->cli = cli;
153 mutex_lock(&cli->lock);
154 list_add_tail(&work->head, &cli->worker);
155 mutex_unlock(&cli->lock);
156 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
157 nouveau_cli_work_fence(fence, &work->cb);
158}
159
160static void
161nouveau_cli_work(struct work_struct *w)
162{
163 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
164 nouveau_cli_work_flush(cli, false);
165}
166
20d8a88e
BS
167static void
168nouveau_cli_fini(struct nouveau_cli *cli)
169{
814a2324 170 nouveau_cli_work_flush(cli, true);
20d8a88e 171 usif_client_fini(cli);
24e8375b 172 nouveau_vmm_fini(&cli->vmm);
01670a79 173 nvif_mmu_fini(&cli->mmu);
1167c6bc 174 nvif_device_fini(&cli->device);
cb7e88e7 175 mutex_lock(&cli->drm->master.lock);
20d8a88e 176 nvif_client_fini(&cli->base);
cb7e88e7 177 mutex_unlock(&cli->drm->master.lock);
20d8a88e
BS
178}
179
94580299 180static int
20d8a88e
BS
181nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
182 struct nouveau_cli *cli)
94580299 183{
7f507624
BS
184 static const struct nvif_mclass
185 mems[] = {
186 { NVIF_CLASS_MEM_GF100, -1 },
187 { NVIF_CLASS_MEM_NV50 , -1 },
188 { NVIF_CLASS_MEM_NV04 , -1 },
189 {}
190 };
01670a79
BS
191 static const struct nvif_mclass
192 mmus[] = {
193 { NVIF_CLASS_MMU_GF100, -1 },
194 { NVIF_CLASS_MMU_NV50 , -1 },
195 { NVIF_CLASS_MMU_NV04 , -1 },
196 {}
197 };
96da0bcd
BS
198 static const struct nvif_mclass
199 vmms[] = {
200 { NVIF_CLASS_VMM_GP100, -1 },
201 { NVIF_CLASS_VMM_GM200, -1 },
202 { NVIF_CLASS_VMM_GF100, -1 },
203 { NVIF_CLASS_VMM_NV50 , -1 },
204 { NVIF_CLASS_VMM_NV04 , -1 },
205 {}
206 };
20d8a88e 207 u64 device = nouveau_name(drm->dev);
9ad97ede 208 int ret;
9ad97ede 209
20d8a88e 210 snprintf(cli->name, sizeof(cli->name), "%s", sname);
e75c091b 211 cli->drm = drm;
20d8a88e
BS
212 mutex_init(&cli->mutex);
213 usif_client_init(cli);
214
814a2324
BS
215 INIT_WORK(&cli->work, nouveau_cli_work);
216 INIT_LIST_HEAD(&cli->worker);
cb7e88e7
BS
217 mutex_init(&cli->lock);
218
219 if (cli == &drm->master) {
80e60973
BS
220 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
221 cli->name, device, &cli->base);
222 } else {
cb7e88e7
BS
223 mutex_lock(&drm->master.lock);
224 ret = nvif_client_init(&drm->master.base, cli->name, device,
9ad97ede 225 &cli->base);
cb7e88e7 226 mutex_unlock(&drm->master.lock);
dd5700ea 227 }
20d8a88e
BS
228 if (ret) {
229 NV_ERROR(drm, "Client allocation failed: %d\n", ret);
230 goto done;
dd5700ea 231 }
94580299 232
1167c6bc
BS
233 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
234 &(struct nv_device_v0) {
235 .device = ~0,
236 }, sizeof(struct nv_device_v0),
237 &cli->device);
238 if (ret) {
239 NV_ERROR(drm, "Device allocation failed: %d\n", ret);
240 goto done;
241 }
242
01670a79
BS
243 ret = nvif_mclass(&cli->device.object, mmus);
244 if (ret < 0) {
245 NV_ERROR(drm, "No supported MMU class\n");
246 goto done;
247 }
248
249 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
250 if (ret) {
251 NV_ERROR(drm, "MMU allocation failed: %d\n", ret);
252 goto done;
253 }
254
96da0bcd
BS
255 ret = nvif_mclass(&cli->mmu.object, vmms);
256 if (ret < 0) {
257 NV_ERROR(drm, "No supported VMM class\n");
258 goto done;
259 }
260
261 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
262 if (ret) {
263 NV_ERROR(drm, "VMM allocation failed: %d\n", ret);
264 goto done;
265 }
266
7f507624
BS
267 ret = nvif_mclass(&cli->mmu.object, mems);
268 if (ret < 0) {
269 NV_ERROR(drm, "No supported MEM class\n");
270 goto done;
271 }
272
273 cli->mem = &mems[ret];
7f507624 274 return 0;
20d8a88e
BS
275done:
276 if (ret)
277 nouveau_cli_fini(cli);
278 return ret;
94580299
BS
279}
280
ebb945a9
BS
281static void
282nouveau_accel_fini(struct nouveau_drm *drm)
283{
fbd58ebd 284 nouveau_channel_idle(drm->channel);
0ad72863 285 nvif_object_fini(&drm->ntfy);
f027f491 286 nvkm_gpuobj_del(&drm->notify);
fbd58ebd 287 nvif_notify_fini(&drm->flip);
0ad72863 288 nvif_object_fini(&drm->nvsw);
fbd58ebd
BS
289 nouveau_channel_del(&drm->channel);
290
291 nouveau_channel_idle(drm->cechan);
0ad72863 292 nvif_object_fini(&drm->ttm.copy);
fbd58ebd
BS
293 nouveau_channel_del(&drm->cechan);
294
ebb945a9
BS
295 if (drm->fence)
296 nouveau_fence(drm)->dtor(drm);
297}
298
299static void
300nouveau_accel_init(struct nouveau_drm *drm)
301{
1167c6bc 302 struct nvif_device *device = &drm->client.device;
41a63406 303 struct nvif_sclass *sclass;
49981046 304 u32 arg0, arg1;
41a63406 305 int ret, i, n;
ebb945a9 306
967e7bde 307 if (nouveau_noaccel)
ebb945a9
BS
308 return;
309
310 /* initialise synchronisation routines */
967e7bde
BS
311 /*XXX: this is crap, but the fence/channel stuff is a little
312 * backwards in some places. this will be fixed.
313 */
41a63406 314 ret = n = nvif_object_sclass_get(&device->object, &sclass);
967e7bde
BS
315 if (ret < 0)
316 return;
317
41a63406
BS
318 for (ret = -ENOSYS, i = 0; i < n; i++) {
319 switch (sclass[i].oclass) {
bbf8906b 320 case NV03_CHANNEL_DMA:
967e7bde
BS
321 ret = nv04_fence_create(drm);
322 break;
bbf8906b 323 case NV10_CHANNEL_DMA:
967e7bde
BS
324 ret = nv10_fence_create(drm);
325 break;
bbf8906b
BS
326 case NV17_CHANNEL_DMA:
327 case NV40_CHANNEL_DMA:
967e7bde
BS
328 ret = nv17_fence_create(drm);
329 break;
bbf8906b 330 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
331 ret = nv50_fence_create(drm);
332 break;
bbf8906b 333 case G82_CHANNEL_GPFIFO:
967e7bde
BS
334 ret = nv84_fence_create(drm);
335 break;
bbf8906b
BS
336 case FERMI_CHANNEL_GPFIFO:
337 case KEPLER_CHANNEL_GPFIFO_A:
63f8c9b7 338 case KEPLER_CHANNEL_GPFIFO_B:
a1020afe 339 case MAXWELL_CHANNEL_GPFIFO_A:
e8ff9794 340 case PASCAL_CHANNEL_GPFIFO_A:
967e7bde
BS
341 ret = nvc0_fence_create(drm);
342 break;
343 default:
344 break;
345 }
346 }
347
41a63406 348 nvif_object_sclass_put(&sclass);
ebb945a9
BS
349 if (ret) {
350 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
351 nouveau_accel_fini(drm);
352 return;
353 }
354
967e7bde 355 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
1167c6bc 356 ret = nouveau_channel_new(drm, &drm->client.device,
1f5ff7f5
BS
357 NVA06F_V0_ENGINE_CE0 |
358 NVA06F_V0_ENGINE_CE1,
bbf8906b 359 0, &drm->cechan);
49981046
BS
360 if (ret)
361 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
362
1f5ff7f5 363 arg0 = NVA06F_V0_ENGINE_GR;
49469800 364 arg1 = 1;
00fc6f6f 365 } else
967e7bde
BS
366 if (device->info.chipset >= 0xa3 &&
367 device->info.chipset != 0xaa &&
368 device->info.chipset != 0xac) {
1167c6bc 369 ret = nouveau_channel_new(drm, &drm->client.device,
0ad72863 370 NvDmaFB, NvDmaTT, &drm->cechan);
00fc6f6f
BS
371 if (ret)
372 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
373
374 arg0 = NvDmaFB;
375 arg1 = NvDmaTT;
49981046
BS
376 } else {
377 arg0 = NvDmaFB;
378 arg1 = NvDmaTT;
379 }
380
1167c6bc
BS
381 ret = nouveau_channel_new(drm, &drm->client.device,
382 arg0, arg1, &drm->channel);
ebb945a9
BS
383 if (ret) {
384 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
385 nouveau_accel_fini(drm);
386 return;
387 }
388
a01ca78c 389 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
0ad72863 390 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
69a6146d 391 if (ret == 0) {
69a6146d
BS
392 ret = RING_SPACE(drm->channel, 2);
393 if (ret == 0) {
967e7bde 394 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
69a6146d
BS
395 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
396 OUT_RING (drm->channel, NVDRM_NVSW);
397 } else
967e7bde 398 if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
69a6146d
BS
399 BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
400 OUT_RING (drm->channel, 0x001f0000);
401 }
402 }
898a2b32
BS
403
404 ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete,
538b269b
BS
405 false, NV04_NVSW_NTFY_UEVENT,
406 NULL, 0, 0, &drm->flip);
898a2b32
BS
407 if (ret == 0)
408 ret = nvif_notify_get(&drm->flip);
409 if (ret) {
410 nouveau_accel_fini(drm);
411 return;
412 }
69a6146d
BS
413 }
414
415 if (ret) {
416 NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
417 nouveau_accel_fini(drm);
418 return;
419 }
420
967e7bde 421 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
1167c6bc
BS
422 ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0,
423 false, NULL, &drm->notify);
ebb945a9
BS
424 if (ret) {
425 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
426 nouveau_accel_fini(drm);
427 return;
428 }
429
a01ca78c 430 ret = nvif_object_init(&drm->channel->user, NvNotify0,
4acfd707
BS
431 NV_DMA_IN_MEMORY,
432 &(struct nv_dma_v0) {
433 .target = NV_DMA_V0_TARGET_VRAM,
434 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
435 .start = drm->notify->addr,
436 .limit = drm->notify->addr + 31
4acfd707 437 }, sizeof(struct nv_dma_v0),
0ad72863 438 &drm->ntfy);
ebb945a9
BS
439 if (ret) {
440 nouveau_accel_fini(drm);
441 return;
442 }
443 }
444
445
49981046 446 nouveau_bo_move_init(drm);
ebb945a9
BS
447}
448
56550d94
GKH
449static int nouveau_drm_probe(struct pci_dev *pdev,
450 const struct pci_device_id *pent)
94580299 451{
be83cd4e 452 struct nvkm_device *device;
ebb945a9
BS
453 struct apertures_struct *aper;
454 bool boot = false;
94580299
BS
455 int ret;
456
b00e5334 457 if (vga_switcheroo_client_probe_defer(pdev))
98b3a340
LW
458 return -EPROBE_DEFER;
459
0e67bed2
BS
460 /* We need to check that the chipset is supported before booting
461 * fbdev off the hardware, as there's no way to put it back.
462 */
463 ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device);
464 if (ret)
465 return ret;
466
467 nvkm_device_del(&device);
468
469 /* Remove conflicting drivers (vesafb, efifb etc). */
ebb945a9
BS
470 aper = alloc_apertures(3);
471 if (!aper)
472 return -ENOMEM;
473
474 aper->ranges[0].base = pci_resource_start(pdev, 1);
475 aper->ranges[0].size = pci_resource_len(pdev, 1);
476 aper->count = 1;
477
478 if (pci_resource_len(pdev, 2)) {
479 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
480 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
481 aper->count++;
482 }
483
484 if (pci_resource_len(pdev, 3)) {
485 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
486 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
487 aper->count++;
488 }
489
490#ifdef CONFIG_X86
491 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
492#endif
771fa0e4 493 if (nouveau_modeset != 2)
44adece5 494 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
83ef7777 495 kfree(aper);
ebb945a9 496
7974dd1b
BS
497 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
498 true, true, ~0ULL, &device);
94580299
BS
499 if (ret)
500 return ret;
501
502 pci_set_master(pdev);
503
915b4d11 504 ret = drm_get_pci_dev(pdev, pent, &driver_pci);
94580299 505 if (ret) {
e781dc8f 506 nvkm_device_del(&device);
94580299
BS
507 return ret;
508 }
509
510 return 0;
511}
512
5addcf0a
DA
513#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
514
515static void
46941b0f 516nouveau_get_hdmi_dev(struct nouveau_drm *drm)
5addcf0a 517{
46941b0f 518 struct pci_dev *pdev = drm->dev->pdev;
5addcf0a 519
420b9469 520 if (!pdev) {
f2a0adad 521 NV_DEBUG(drm, "not a PCI device; no HDMI\n");
420b9469
AC
522 drm->hdmi_device = NULL;
523 return;
524 }
525
5addcf0a
DA
526 /* subfunction one is a hdmi audio device? */
527 drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
528 PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
529
530 if (!drm->hdmi_device) {
46941b0f 531 NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
5addcf0a
DA
532 return;
533 }
534
535 if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
46941b0f 536 NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
5addcf0a
DA
537 pci_dev_put(drm->hdmi_device);
538 drm->hdmi_device = NULL;
539 return;
540 }
541}
542
5b8a43ae 543static int
94580299
BS
544nouveau_drm_load(struct drm_device *dev, unsigned long flags)
545{
94580299
BS
546 struct nouveau_drm *drm;
547 int ret;
548
20d8a88e
BS
549 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
550 return -ENOMEM;
551 dev->dev_private = drm;
552 drm->dev = dev;
553
cb7e88e7
BS
554 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
555 if (ret)
556 return ret;
557
20d8a88e 558 ret = nouveau_cli_init(drm, "DRM", &drm->client);
94580299
BS
559 if (ret)
560 return ret;
561
1167c6bc
BS
562 dev->irq_enabled = true;
563
989aa5b7 564 nvxx_client(&drm->client.base)->debug =
be83cd4e 565 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 566
94580299 567 INIT_LIST_HEAD(&drm->clients);
ebb945a9 568 spin_lock_init(&drm->tile.lock);
94580299 569
46941b0f 570 nouveau_get_hdmi_dev(drm);
5addcf0a 571
77145f1c
BS
572 /* workaround an odd issue on nvc1 by disabling the device's
573 * nosnoop capability. hopefully won't cause issues until a
574 * better fix is found - assuming there is one...
575 */
1167c6bc
BS
576 if (drm->client.device.info.chipset == 0xc1)
577 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 578
77145f1c 579 nouveau_vga_init(drm);
cb75d97e 580
ebb945a9 581 ret = nouveau_ttm_init(drm);
94580299 582 if (ret)
77145f1c
BS
583 goto fail_ttm;
584
585 ret = nouveau_bios_init(dev);
586 if (ret)
587 goto fail_bios;
588
77145f1c 589 ret = nouveau_display_create(dev);
ebb945a9 590 if (ret)
77145f1c
BS
591 goto fail_dispctor;
592
593 if (dev->mode_config.num_crtc) {
594 ret = nouveau_display_init(dev);
595 if (ret)
596 goto fail_dispinit;
597 }
598
b126a200 599 nouveau_debugfs_init(drm);
b9ed919f 600 nouveau_hwmon_init(dev);
ebb945a9
BS
601 nouveau_accel_init(drm);
602 nouveau_fbcon_init(dev);
8d021d71 603 nouveau_led_init(dev);
5addcf0a 604
8fa4338a 605 if (nouveau_pmops_runtime()) {
5addcf0a
DA
606 pm_runtime_use_autosuspend(dev->dev);
607 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
608 pm_runtime_set_active(dev->dev);
609 pm_runtime_allow(dev->dev);
610 pm_runtime_mark_last_busy(dev->dev);
611 pm_runtime_put(dev->dev);
9a2eba33
PU
612 } else {
613 /* enable polling for external displays */
614 drm_kms_helper_poll_enable(dev);
5addcf0a 615 }
94580299
BS
616 return 0;
617
77145f1c
BS
618fail_dispinit:
619 nouveau_display_destroy(dev);
620fail_dispctor:
77145f1c
BS
621 nouveau_bios_takedown(dev);
622fail_bios:
ebb945a9 623 nouveau_ttm_fini(drm);
77145f1c 624fail_ttm:
77145f1c 625 nouveau_vga_fini(drm);
20d8a88e 626 nouveau_cli_fini(&drm->client);
cb7e88e7 627 nouveau_cli_fini(&drm->master);
20d8a88e 628 kfree(drm);
94580299
BS
629 return ret;
630}
631
11b3c20b 632static void
94580299
BS
633nouveau_drm_unload(struct drm_device *dev)
634{
77145f1c 635 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 636
8fa4338a 637 if (nouveau_pmops_runtime()) {
c1b16b45 638 pm_runtime_get_sync(dev->dev);
55c868a3 639 pm_runtime_forbid(dev->dev);
c1b16b45
LW
640 }
641
8d021d71 642 nouveau_led_fini(dev);
ebb945a9
BS
643 nouveau_fbcon_fini(dev);
644 nouveau_accel_fini(drm);
b9ed919f 645 nouveau_hwmon_fini(dev);
b126a200 646 nouveau_debugfs_fini(drm);
77145f1c 647
9430738d 648 if (dev->mode_config.num_crtc)
3b4c0abb 649 nouveau_display_fini(dev, false);
77145f1c
BS
650 nouveau_display_destroy(dev);
651
77145f1c 652 nouveau_bios_takedown(dev);
94580299 653
ebb945a9 654 nouveau_ttm_fini(drm);
77145f1c 655 nouveau_vga_fini(drm);
cb75d97e 656
5addcf0a
DA
657 if (drm->hdmi_device)
658 pci_dev_put(drm->hdmi_device);
20d8a88e 659 nouveau_cli_fini(&drm->client);
cb7e88e7 660 nouveau_cli_fini(&drm->master);
20d8a88e 661 kfree(drm);
94580299
BS
662}
663
8ba9ff11
AC
664void
665nouveau_drm_device_remove(struct drm_device *dev)
94580299 666{
77145f1c 667 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e 668 struct nvkm_client *client;
76ecea5b 669 struct nvkm_device *device;
77145f1c 670
7d3428cd 671 dev->irq_enabled = false;
989aa5b7 672 client = nvxx_client(&drm->client.base);
4e7e62d6 673 device = nvkm_device_find(client->device);
77145f1c
BS
674 drm_put_dev(dev);
675
e781dc8f 676 nvkm_device_del(&device);
94580299 677}
8ba9ff11
AC
678
679static void
680nouveau_drm_remove(struct pci_dev *pdev)
681{
682 struct drm_device *dev = pci_get_drvdata(pdev);
683
684 nouveau_drm_device_remove(dev);
685}
94580299 686
cd897837 687static int
05c63c2f 688nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 689{
77145f1c 690 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
691 int ret;
692
8d021d71
MP
693 nouveau_led_suspend(dev);
694
6fbb702e 695 if (dev->mode_config.num_crtc) {
2d38a535 696 NV_DEBUG(drm, "suspending console...\n");
6fbb702e 697 nouveau_fbcon_set_suspend(dev, 1);
2d38a535 698 NV_DEBUG(drm, "suspending display...\n");
6fbb702e 699 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
700 if (ret)
701 return ret;
702 }
94580299 703
2d38a535 704 NV_DEBUG(drm, "evicting buffers...\n");
ebb945a9
BS
705 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
706
2d38a535 707 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
708 if (drm->cechan) {
709 ret = nouveau_channel_idle(drm->cechan);
710 if (ret)
f3980dc5 711 goto fail_display;
81dff21b
BS
712 }
713
714 if (drm->channel) {
715 ret = nouveau_channel_idle(drm->channel);
716 if (ret)
f3980dc5 717 goto fail_display;
81dff21b
BS
718 }
719
2d38a535 720 NV_DEBUG(drm, "suspending fence...\n");
ebb945a9 721 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
722 if (!nouveau_fence(drm)->suspend(drm)) {
723 ret = -ENOMEM;
724 goto fail_display;
725 }
ebb945a9
BS
726 }
727
2d38a535 728 NV_DEBUG(drm, "suspending object tree...\n");
cb7e88e7 729 ret = nvif_client_suspend(&drm->master.base);
94580299
BS
730 if (ret)
731 goto fail_client;
732
94580299
BS
733 return 0;
734
735fail_client:
f3980dc5
IM
736 if (drm->fence && nouveau_fence(drm)->resume)
737 nouveau_fence(drm)->resume(drm);
738
739fail_display:
9430738d 740 if (dev->mode_config.num_crtc) {
2d38a535 741 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 742 nouveau_display_resume(dev, runtime);
9430738d 743 }
94580299
BS
744 return ret;
745}
746
cd897837 747static int
6fbb702e 748nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb
DA
749{
750 struct nouveau_drm *drm = nouveau_drm(dev);
2d8b9ccb 751
2d38a535 752 NV_DEBUG(drm, "resuming object tree...\n");
cb7e88e7 753 nvif_client_resume(&drm->master.base);
94580299 754
2d38a535 755 NV_DEBUG(drm, "resuming fence...\n");
81dff21b
BS
756 if (drm->fence && nouveau_fence(drm)->resume)
757 nouveau_fence(drm)->resume(drm);
758
77145f1c 759 nouveau_run_vbios_init(dev);
77145f1c 760
9430738d 761 if (dev->mode_config.num_crtc) {
2d38a535 762 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 763 nouveau_display_resume(dev, runtime);
2d38a535 764 NV_DEBUG(drm, "resuming console...\n");
6fbb702e 765 nouveau_fbcon_set_suspend(dev, 0);
9430738d 766 }
5addcf0a 767
8d021d71
MP
768 nouveau_led_resume(dev);
769
77145f1c 770 return 0;
94580299
BS
771}
772
7bb6d442
BS
773int
774nouveau_pmops_suspend(struct device *dev)
775{
776 struct pci_dev *pdev = to_pci_dev(dev);
777 struct drm_device *drm_dev = pci_get_drvdata(pdev);
778 int ret;
779
780 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
781 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
782 return 0;
783
784 ret = nouveau_do_suspend(drm_dev, false);
785 if (ret)
786 return ret;
787
788 pci_save_state(pdev);
789 pci_disable_device(pdev);
7bb6d442 790 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 791 udelay(200);
7bb6d442
BS
792 return 0;
793}
794
795int
796nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
797{
798 struct pci_dev *pdev = to_pci_dev(dev);
799 struct drm_device *drm_dev = pci_get_drvdata(pdev);
800 int ret;
801
5addcf0a
DA
802 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
803 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
804 return 0;
805
806 pci_set_power_state(pdev, PCI_D0);
807 pci_restore_state(pdev);
808 ret = pci_enable_device(pdev);
809 if (ret)
810 return ret;
811 pci_set_master(pdev);
812
0b2fe659
HG
813 ret = nouveau_do_resume(drm_dev, false);
814
815 /* Monitors may have been connected / disconnected during suspend */
816 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
817
818 return ret;
2d8b9ccb
DA
819}
820
7bb6d442
BS
821static int
822nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
823{
824 struct pci_dev *pdev = to_pci_dev(dev);
825 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 826 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
827}
828
7bb6d442
BS
829static int
830nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
831{
832 struct pci_dev *pdev = to_pci_dev(dev);
833 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 834 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
835}
836
321f5c5f 837bool
5499473c 838nouveau_pmops_runtime(void)
321f5c5f
BS
839{
840 if (nouveau_runtime_pm == -1)
841 return nouveau_is_optimus() || nouveau_is_v1_dsm();
842 return nouveau_runtime_pm == 1;
843}
844
7bb6d442
BS
845static int
846nouveau_pmops_runtime_suspend(struct device *dev)
847{
848 struct pci_dev *pdev = to_pci_dev(dev);
849 struct drm_device *drm_dev = pci_get_drvdata(pdev);
850 int ret;
851
321f5c5f 852 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
853 pm_runtime_forbid(dev);
854 return -EBUSY;
855 }
856
7bb6d442
BS
857 drm_kms_helper_poll_disable(drm_dev);
858 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
859 nouveau_switcheroo_optimus_dsm();
860 ret = nouveau_do_suspend(drm_dev, true);
861 pci_save_state(pdev);
862 pci_disable_device(pdev);
8c863944 863 pci_ignore_hotplug(pdev);
7bb6d442
BS
864 pci_set_power_state(pdev, PCI_D3cold);
865 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
866 return ret;
867}
868
869static int
870nouveau_pmops_runtime_resume(struct device *dev)
871{
872 struct pci_dev *pdev = to_pci_dev(dev);
873 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1167c6bc 874 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
7bb6d442
BS
875 int ret;
876
321f5c5f
BS
877 if (!nouveau_pmops_runtime()) {
878 pm_runtime_forbid(dev);
879 return -EBUSY;
880 }
7bb6d442
BS
881
882 pci_set_power_state(pdev, PCI_D0);
883 pci_restore_state(pdev);
884 ret = pci_enable_device(pdev);
885 if (ret)
886 return ret;
887 pci_set_master(pdev);
888
889 ret = nouveau_do_resume(drm_dev, true);
cae9ff03 890
7bb6d442 891 /* do magic */
a01ca78c 892 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
7bb6d442
BS
893 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
894 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
0b2fe659
HG
895
896 /* Monitors may have been connected / disconnected during suspend */
897 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
898
7bb6d442
BS
899 return ret;
900}
901
902static int
903nouveau_pmops_runtime_idle(struct device *dev)
904{
905 struct pci_dev *pdev = to_pci_dev(dev);
906 struct drm_device *drm_dev = pci_get_drvdata(pdev);
907 struct nouveau_drm *drm = nouveau_drm(drm_dev);
908 struct drm_crtc *crtc;
909
321f5c5f 910 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
911 pm_runtime_forbid(dev);
912 return -EBUSY;
913 }
914
915 /* if we have a hdmi audio device - make sure it has a driver loaded */
916 if (drm->hdmi_device) {
917 if (!drm->hdmi_device->driver) {
918 DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
919 pm_runtime_mark_last_busy(dev);
920 return -EBUSY;
921 }
922 }
923
924 list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
925 if (crtc->enabled) {
926 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
927 return -EBUSY;
928 }
929 }
930 pm_runtime_mark_last_busy(dev);
931 pm_runtime_autosuspend(dev);
932 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
933 return 1;
934}
2d8b9ccb 935
5b8a43ae 936static int
ebb945a9
BS
937nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
938{
ebb945a9
BS
939 struct nouveau_drm *drm = nouveau_drm(dev);
940 struct nouveau_cli *cli;
a2896ced 941 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
942 int ret;
943
5addcf0a
DA
944 /* need to bring up power immediately if opening device */
945 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 946 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
947 return ret;
948
a2896ced
MS
949 get_task_comm(tmpname, current);
950 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 951
20d8a88e
BS
952 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL)))
953 return ret;
420b9469 954
20d8a88e 955 ret = nouveau_cli_init(drm, name, cli);
ebb945a9 956 if (ret)
20d8a88e 957 goto done;
ebb945a9 958
0ad72863
BS
959 cli->base.super = false;
960
ebb945a9
BS
961 fpriv->driver_priv = cli;
962
963 mutex_lock(&drm->client.mutex);
964 list_add(&cli->head, &drm->clients);
965 mutex_unlock(&drm->client.mutex);
5addcf0a 966
20d8a88e
BS
967done:
968 if (ret && cli) {
969 nouveau_cli_fini(cli);
970 kfree(cli);
971 }
972
5addcf0a
DA
973 pm_runtime_mark_last_busy(dev->dev);
974 pm_runtime_put_autosuspend(dev->dev);
5addcf0a 975 return ret;
ebb945a9
BS
976}
977
5b8a43ae 978static void
f0e73ff3 979nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
ebb945a9
BS
980{
981 struct nouveau_cli *cli = nouveau_cli(fpriv);
982 struct nouveau_drm *drm = nouveau_drm(dev);
983
5addcf0a
DA
984 pm_runtime_get_sync(dev->dev);
985
ac8c7930 986 mutex_lock(&cli->mutex);
ebb945a9
BS
987 if (cli->abi16)
988 nouveau_abi16_fini(cli->abi16);
ac8c7930 989 mutex_unlock(&cli->mutex);
ebb945a9
BS
990
991 mutex_lock(&drm->client.mutex);
992 list_del(&cli->head);
993 mutex_unlock(&drm->client.mutex);
5addcf0a 994
20d8a88e
BS
995 nouveau_cli_fini(cli);
996 kfree(cli);
5addcf0a
DA
997 pm_runtime_mark_last_busy(dev->dev);
998 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
999}
1000
baa70943 1001static const struct drm_ioctl_desc
77145f1c 1002nouveau_ioctls[] = {
f8c47144
DV
1003 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1005 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
1007 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1009 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
1010 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
1011 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
1012 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1013 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1014 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
1015};
1016
27111a23
BS
1017long
1018nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 1019{
27111a23
BS
1020 struct drm_file *filp = file->private_data;
1021 struct drm_device *dev = filp->minor->dev;
5addcf0a 1022 long ret;
5addcf0a
DA
1023
1024 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 1025 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
1026 return ret;
1027
27111a23
BS
1028 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1029 case DRM_NOUVEAU_NVIF:
1030 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1031 break;
1032 default:
1033 ret = drm_ioctl(file, cmd, arg);
1034 break;
1035 }
5addcf0a
DA
1036
1037 pm_runtime_mark_last_busy(dev->dev);
1038 pm_runtime_put_autosuspend(dev->dev);
1039 return ret;
1040}
27111a23 1041
77145f1c
BS
1042static const struct file_operations
1043nouveau_driver_fops = {
1044 .owner = THIS_MODULE,
1045 .open = drm_open,
1046 .release = drm_release,
5addcf0a 1047 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
1048 .mmap = nouveau_ttm_mmap,
1049 .poll = drm_poll,
77145f1c
BS
1050 .read = drm_read,
1051#if defined(CONFIG_COMPAT)
1052 .compat_ioctl = nouveau_compat_ioctl,
1053#endif
1054 .llseek = noop_llseek,
1055};
1056
1057static struct drm_driver
915b4d11 1058driver_stub = {
77145f1c 1059 .driver_features =
0e975980
PA
1060 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER |
1061 DRIVER_KMS_LEGACY_CONTEXT,
77145f1c
BS
1062
1063 .load = nouveau_drm_load,
1064 .unload = nouveau_drm_unload,
1065 .open = nouveau_drm_open,
77145f1c
BS
1066 .postclose = nouveau_drm_postclose,
1067 .lastclose = nouveau_vga_lastclose,
1068
33b903e8 1069#if defined(CONFIG_DEBUG_FS)
56c101af 1070 .debugfs_init = nouveau_drm_debugfs_init,
33b903e8
MS
1071#endif
1072
51cb4b39
BS
1073 .enable_vblank = nouveau_display_vblank_enable,
1074 .disable_vblank = nouveau_display_vblank_disable,
d83ef853 1075 .get_scanout_position = nouveau_display_scanoutpos,
1bf6ad62 1076 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
77145f1c
BS
1077
1078 .ioctls = nouveau_ioctls,
baa70943 1079 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
1080 .fops = &nouveau_driver_fops,
1081
1082 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1083 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
1084 .gem_prime_export = drm_gem_prime_export,
1085 .gem_prime_import = drm_gem_prime_import,
1086 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 1087 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 1088 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
1089 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1090 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1091 .gem_prime_vmap = nouveau_gem_prime_vmap,
1092 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 1093
a51e6ac4 1094 .gem_free_object_unlocked = nouveau_gem_object_del,
77145f1c
BS
1095 .gem_open_object = nouveau_gem_object_open,
1096 .gem_close_object = nouveau_gem_object_close,
1097
1098 .dumb_create = nouveau_display_dumb_create,
1099 .dumb_map_offset = nouveau_display_dumb_map_offset,
77145f1c
BS
1100
1101 .name = DRIVER_NAME,
1102 .desc = DRIVER_DESC,
1103#ifdef GIT_REVISION
1104 .date = GIT_REVISION,
1105#else
1106 .date = DRIVER_DATE,
1107#endif
1108 .major = DRIVER_MAJOR,
1109 .minor = DRIVER_MINOR,
1110 .patchlevel = DRIVER_PATCHLEVEL,
1111};
1112
94580299
BS
1113static struct pci_device_id
1114nouveau_drm_pci_table[] = {
1115 {
1116 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1117 .class = PCI_BASE_CLASS_DISPLAY << 16,
1118 .class_mask = 0xff << 16,
1119 },
1120 {
1121 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1122 .class = PCI_BASE_CLASS_DISPLAY << 16,
1123 .class_mask = 0xff << 16,
1124 },
1125 {}
1126};
1127
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PM
1128static void nouveau_display_options(void)
1129{
1130 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1131
1132 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1133 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1134 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1135 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1136 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1137 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1138 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1139 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1140 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1141 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
f3a8b664 1142 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
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PM
1143}
1144
2d8b9ccb
DA
1145static const struct dev_pm_ops nouveau_pm_ops = {
1146 .suspend = nouveau_pmops_suspend,
1147 .resume = nouveau_pmops_resume,
1148 .freeze = nouveau_pmops_freeze,
1149 .thaw = nouveau_pmops_thaw,
1150 .poweroff = nouveau_pmops_freeze,
1151 .restore = nouveau_pmops_resume,
5addcf0a
DA
1152 .runtime_suspend = nouveau_pmops_runtime_suspend,
1153 .runtime_resume = nouveau_pmops_runtime_resume,
1154 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1155};
1156
94580299
BS
1157static struct pci_driver
1158nouveau_drm_pci_driver = {
1159 .name = "nouveau",
1160 .id_table = nouveau_drm_pci_table,
1161 .probe = nouveau_drm_probe,
1162 .remove = nouveau_drm_remove,
2d8b9ccb 1163 .driver.pm = &nouveau_pm_ops,
94580299
BS
1164};
1165
8ba9ff11 1166struct drm_device *
e396ecd1
AC
1167nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1168 struct platform_device *pdev,
47b2505e 1169 struct nvkm_device **pdevice)
420b9469 1170{
8ba9ff11
AC
1171 struct drm_device *drm;
1172 int err;
420b9469 1173
e396ecd1 1174 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
7974dd1b 1175 true, true, ~0ULL, pdevice);
8ba9ff11 1176 if (err)
e781dc8f 1177 goto err_free;
8ba9ff11 1178
915b4d11 1179 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
0f288605
TG
1180 if (IS_ERR(drm)) {
1181 err = PTR_ERR(drm);
8ba9ff11 1182 goto err_free;
420b9469
AC
1183 }
1184
8ba9ff11
AC
1185 platform_set_drvdata(pdev, drm);
1186
1187 return drm;
1188
1189err_free:
e781dc8f 1190 nvkm_device_del(pdevice);
8ba9ff11
AC
1191
1192 return ERR_PTR(err);
420b9469
AC
1193}
1194
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BS
1195static int __init
1196nouveau_drm_init(void)
1197{
915b4d11 1198 driver_pci = driver_stub;
915b4d11 1199 driver_platform = driver_stub;
915b4d11 1200
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PM
1201 nouveau_display_options();
1202
77145f1c 1203 if (nouveau_modeset == -1) {
77145f1c
BS
1204 if (vgacon_text_force())
1205 nouveau_modeset = 0;
77145f1c
BS
1206 }
1207
1208 if (!nouveau_modeset)
1209 return 0;
1210
055a65d5
AC
1211#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1212 platform_driver_register(&nouveau_platform_driver);
1213#endif
1214
77145f1c 1215 nouveau_register_dsm_handler();
db1a0ae2 1216 nouveau_backlight_ctor();
10631d72
DV
1217
1218#ifdef CONFIG_PCI
1219 return pci_register_driver(&nouveau_drm_pci_driver);
1220#else
1221 return 0;
1222#endif
94580299
BS
1223}
1224
1225static void __exit
1226nouveau_drm_exit(void)
1227{
77145f1c
BS
1228 if (!nouveau_modeset)
1229 return;
1230
10631d72
DV
1231#ifdef CONFIG_PCI
1232 pci_unregister_driver(&nouveau_drm_pci_driver);
1233#endif
db1a0ae2 1234 nouveau_backlight_dtor();
77145f1c 1235 nouveau_unregister_dsm_handler();
055a65d5
AC
1236
1237#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1238 platform_driver_unregister(&nouveau_platform_driver);
1239#endif
94580299
BS
1240}
1241
1242module_init(nouveau_drm_init);
1243module_exit(nouveau_drm_exit);
1244
1245MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1246MODULE_AUTHOR(DRIVER_AUTHOR);
1247MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1248MODULE_LICENSE("GPL and additional rights");