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Commit | Line | Data |
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94580299 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
77145f1c | 25 | #include <linux/console.h> |
c5fd936e | 26 | #include <linux/delay.h> |
94580299 BS |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> | |
5addcf0a DA |
29 | #include <linux/pm_runtime.h> |
30 | #include <linux/vga_switcheroo.h> | |
fdb751ef | 31 | |
ae95621b MY |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc_helper.h> | |
fdb751ef | 34 | |
ebb945a9 | 35 | #include <core/gpuobj.h> |
c33e05a1 | 36 | #include <core/option.h> |
7974dd1b BS |
37 | #include <core/pci.h> |
38 | #include <core/tegra.h> | |
94580299 | 39 | |
04b88677 BS |
40 | #include <nvif/driver.h> |
41 | ||
923bc416 | 42 | #include <nvif/class.h> |
845f2725 | 43 | #include <nvif/cl0002.h> |
8ed1730c | 44 | #include <nvif/cla06f.h> |
538b269b BS |
45 | #include <nvif/if0004.h> |
46 | ||
4dc28134 | 47 | #include "nouveau_drv.h" |
ebb945a9 | 48 | #include "nouveau_dma.h" |
77145f1c BS |
49 | #include "nouveau_ttm.h" |
50 | #include "nouveau_gem.h" | |
77145f1c | 51 | #include "nouveau_vga.h" |
8d021d71 | 52 | #include "nouveau_led.h" |
b9ed919f | 53 | #include "nouveau_hwmon.h" |
77145f1c BS |
54 | #include "nouveau_acpi.h" |
55 | #include "nouveau_bios.h" | |
56 | #include "nouveau_ioctl.h" | |
ebb945a9 BS |
57 | #include "nouveau_abi16.h" |
58 | #include "nouveau_fbcon.h" | |
59 | #include "nouveau_fence.h" | |
33b903e8 | 60 | #include "nouveau_debugfs.h" |
27111a23 | 61 | #include "nouveau_usif.h" |
703fa264 | 62 | #include "nouveau_connector.h" |
055a65d5 | 63 | #include "nouveau_platform.h" |
ebb945a9 | 64 | |
94580299 BS |
65 | MODULE_PARM_DESC(config, "option string to pass to driver core"); |
66 | static char *nouveau_config; | |
67 | module_param_named(config, nouveau_config, charp, 0400); | |
68 | ||
69 | MODULE_PARM_DESC(debug, "debug string to pass to driver core"); | |
70 | static char *nouveau_debug; | |
71 | module_param_named(debug, nouveau_debug, charp, 0400); | |
72 | ||
ebb945a9 BS |
73 | MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); |
74 | static int nouveau_noaccel = 0; | |
75 | module_param_named(noaccel, nouveau_noaccel, int, 0400); | |
76 | ||
9430738d BS |
77 | MODULE_PARM_DESC(modeset, "enable driver (default: auto, " |
78 | "0 = disabled, 1 = enabled, 2 = headless)"); | |
79 | int nouveau_modeset = -1; | |
77145f1c BS |
80 | module_param_named(modeset, nouveau_modeset, int, 0400); |
81 | ||
5addcf0a | 82 | MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); |
321f5c5f | 83 | static int nouveau_runtime_pm = -1; |
5addcf0a DA |
84 | module_param_named(runpm, nouveau_runtime_pm, int, 0400); |
85 | ||
915b4d11 DH |
86 | static struct drm_driver driver_stub; |
87 | static struct drm_driver driver_pci; | |
88 | static struct drm_driver driver_platform; | |
77145f1c | 89 | |
94580299 | 90 | static u64 |
420b9469 | 91 | nouveau_pci_name(struct pci_dev *pdev) |
94580299 BS |
92 | { |
93 | u64 name = (u64)pci_domain_nr(pdev->bus) << 32; | |
94 | name |= pdev->bus->number << 16; | |
95 | name |= PCI_SLOT(pdev->devfn) << 8; | |
96 | return name | PCI_FUNC(pdev->devfn); | |
97 | } | |
98 | ||
420b9469 AC |
99 | static u64 |
100 | nouveau_platform_name(struct platform_device *platformdev) | |
101 | { | |
102 | return platformdev->id; | |
103 | } | |
104 | ||
105 | static u64 | |
106 | nouveau_name(struct drm_device *dev) | |
107 | { | |
108 | if (dev->pdev) | |
109 | return nouveau_pci_name(dev->pdev); | |
110 | else | |
76adb460 | 111 | return nouveau_platform_name(to_platform_device(dev->dev)); |
420b9469 AC |
112 | } |
113 | ||
20d8a88e BS |
114 | static void |
115 | nouveau_cli_fini(struct nouveau_cli *cli) | |
116 | { | |
20d8a88e | 117 | usif_client_fini(cli); |
24e8375b | 118 | nouveau_vmm_fini(&cli->vmm); |
01670a79 | 119 | nvif_mmu_fini(&cli->mmu); |
1167c6bc | 120 | nvif_device_fini(&cli->device); |
cb7e88e7 | 121 | mutex_lock(&cli->drm->master.lock); |
20d8a88e | 122 | nvif_client_fini(&cli->base); |
cb7e88e7 | 123 | mutex_unlock(&cli->drm->master.lock); |
20d8a88e BS |
124 | } |
125 | ||
94580299 | 126 | static int |
20d8a88e BS |
127 | nouveau_cli_init(struct nouveau_drm *drm, const char *sname, |
128 | struct nouveau_cli *cli) | |
94580299 | 129 | { |
01670a79 BS |
130 | static const struct nvif_mclass |
131 | mmus[] = { | |
132 | { NVIF_CLASS_MMU_GF100, -1 }, | |
133 | { NVIF_CLASS_MMU_NV50 , -1 }, | |
134 | { NVIF_CLASS_MMU_NV04 , -1 }, | |
135 | {} | |
136 | }; | |
96da0bcd BS |
137 | static const struct nvif_mclass |
138 | vmms[] = { | |
139 | { NVIF_CLASS_VMM_GP100, -1 }, | |
140 | { NVIF_CLASS_VMM_GM200, -1 }, | |
141 | { NVIF_CLASS_VMM_GF100, -1 }, | |
142 | { NVIF_CLASS_VMM_NV50 , -1 }, | |
143 | { NVIF_CLASS_VMM_NV04 , -1 }, | |
144 | {} | |
145 | }; | |
20d8a88e | 146 | u64 device = nouveau_name(drm->dev); |
9ad97ede | 147 | int ret; |
9ad97ede | 148 | |
20d8a88e | 149 | snprintf(cli->name, sizeof(cli->name), "%s", sname); |
e75c091b | 150 | cli->drm = drm; |
20d8a88e BS |
151 | mutex_init(&cli->mutex); |
152 | usif_client_init(cli); | |
153 | ||
cb7e88e7 BS |
154 | mutex_init(&cli->lock); |
155 | ||
156 | if (cli == &drm->master) { | |
80e60973 BS |
157 | ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, |
158 | cli->name, device, &cli->base); | |
159 | } else { | |
cb7e88e7 BS |
160 | mutex_lock(&drm->master.lock); |
161 | ret = nvif_client_init(&drm->master.base, cli->name, device, | |
9ad97ede | 162 | &cli->base); |
cb7e88e7 | 163 | mutex_unlock(&drm->master.lock); |
dd5700ea | 164 | } |
20d8a88e BS |
165 | if (ret) { |
166 | NV_ERROR(drm, "Client allocation failed: %d\n", ret); | |
167 | goto done; | |
dd5700ea | 168 | } |
94580299 | 169 | |
1167c6bc BS |
170 | ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, |
171 | &(struct nv_device_v0) { | |
172 | .device = ~0, | |
173 | }, sizeof(struct nv_device_v0), | |
174 | &cli->device); | |
175 | if (ret) { | |
176 | NV_ERROR(drm, "Device allocation failed: %d\n", ret); | |
177 | goto done; | |
178 | } | |
179 | ||
01670a79 BS |
180 | ret = nvif_mclass(&cli->device.object, mmus); |
181 | if (ret < 0) { | |
182 | NV_ERROR(drm, "No supported MMU class\n"); | |
183 | goto done; | |
184 | } | |
185 | ||
186 | ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); | |
187 | if (ret) { | |
188 | NV_ERROR(drm, "MMU allocation failed: %d\n", ret); | |
189 | goto done; | |
190 | } | |
191 | ||
96da0bcd BS |
192 | ret = nvif_mclass(&cli->mmu.object, vmms); |
193 | if (ret < 0) { | |
194 | NV_ERROR(drm, "No supported VMM class\n"); | |
195 | goto done; | |
196 | } | |
197 | ||
198 | ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); | |
199 | if (ret) { | |
200 | NV_ERROR(drm, "VMM allocation failed: %d\n", ret); | |
201 | goto done; | |
202 | } | |
203 | ||
204 | if (1) { | |
205 | cli->vm = cli->vmm.vm; | |
206 | nvxx_client(&cli->base)->vm = cli->vm; | |
207 | } | |
208 | ||
20d8a88e BS |
209 | done: |
210 | if (ret) | |
211 | nouveau_cli_fini(cli); | |
212 | return ret; | |
94580299 BS |
213 | } |
214 | ||
ebb945a9 BS |
215 | static void |
216 | nouveau_accel_fini(struct nouveau_drm *drm) | |
217 | { | |
fbd58ebd | 218 | nouveau_channel_idle(drm->channel); |
0ad72863 | 219 | nvif_object_fini(&drm->ntfy); |
f027f491 | 220 | nvkm_gpuobj_del(&drm->notify); |
fbd58ebd | 221 | nvif_notify_fini(&drm->flip); |
0ad72863 | 222 | nvif_object_fini(&drm->nvsw); |
fbd58ebd BS |
223 | nouveau_channel_del(&drm->channel); |
224 | ||
225 | nouveau_channel_idle(drm->cechan); | |
0ad72863 | 226 | nvif_object_fini(&drm->ttm.copy); |
fbd58ebd BS |
227 | nouveau_channel_del(&drm->cechan); |
228 | ||
ebb945a9 BS |
229 | if (drm->fence) |
230 | nouveau_fence(drm)->dtor(drm); | |
231 | } | |
232 | ||
233 | static void | |
234 | nouveau_accel_init(struct nouveau_drm *drm) | |
235 | { | |
1167c6bc | 236 | struct nvif_device *device = &drm->client.device; |
41a63406 | 237 | struct nvif_sclass *sclass; |
49981046 | 238 | u32 arg0, arg1; |
41a63406 | 239 | int ret, i, n; |
ebb945a9 | 240 | |
967e7bde | 241 | if (nouveau_noaccel) |
ebb945a9 BS |
242 | return; |
243 | ||
244 | /* initialise synchronisation routines */ | |
967e7bde BS |
245 | /*XXX: this is crap, but the fence/channel stuff is a little |
246 | * backwards in some places. this will be fixed. | |
247 | */ | |
41a63406 | 248 | ret = n = nvif_object_sclass_get(&device->object, &sclass); |
967e7bde BS |
249 | if (ret < 0) |
250 | return; | |
251 | ||
41a63406 BS |
252 | for (ret = -ENOSYS, i = 0; i < n; i++) { |
253 | switch (sclass[i].oclass) { | |
bbf8906b | 254 | case NV03_CHANNEL_DMA: |
967e7bde BS |
255 | ret = nv04_fence_create(drm); |
256 | break; | |
bbf8906b | 257 | case NV10_CHANNEL_DMA: |
967e7bde BS |
258 | ret = nv10_fence_create(drm); |
259 | break; | |
bbf8906b BS |
260 | case NV17_CHANNEL_DMA: |
261 | case NV40_CHANNEL_DMA: | |
967e7bde BS |
262 | ret = nv17_fence_create(drm); |
263 | break; | |
bbf8906b | 264 | case NV50_CHANNEL_GPFIFO: |
967e7bde BS |
265 | ret = nv50_fence_create(drm); |
266 | break; | |
bbf8906b | 267 | case G82_CHANNEL_GPFIFO: |
967e7bde BS |
268 | ret = nv84_fence_create(drm); |
269 | break; | |
bbf8906b BS |
270 | case FERMI_CHANNEL_GPFIFO: |
271 | case KEPLER_CHANNEL_GPFIFO_A: | |
63f8c9b7 | 272 | case KEPLER_CHANNEL_GPFIFO_B: |
a1020afe | 273 | case MAXWELL_CHANNEL_GPFIFO_A: |
e8ff9794 | 274 | case PASCAL_CHANNEL_GPFIFO_A: |
967e7bde BS |
275 | ret = nvc0_fence_create(drm); |
276 | break; | |
277 | default: | |
278 | break; | |
279 | } | |
280 | } | |
281 | ||
41a63406 | 282 | nvif_object_sclass_put(&sclass); |
ebb945a9 BS |
283 | if (ret) { |
284 | NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); | |
285 | nouveau_accel_fini(drm); | |
286 | return; | |
287 | } | |
288 | ||
967e7bde | 289 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { |
1167c6bc | 290 | ret = nouveau_channel_new(drm, &drm->client.device, |
1f5ff7f5 BS |
291 | NVA06F_V0_ENGINE_CE0 | |
292 | NVA06F_V0_ENGINE_CE1, | |
bbf8906b | 293 | 0, &drm->cechan); |
49981046 BS |
294 | if (ret) |
295 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
296 | ||
1f5ff7f5 | 297 | arg0 = NVA06F_V0_ENGINE_GR; |
49469800 | 298 | arg1 = 1; |
00fc6f6f | 299 | } else |
967e7bde BS |
300 | if (device->info.chipset >= 0xa3 && |
301 | device->info.chipset != 0xaa && | |
302 | device->info.chipset != 0xac) { | |
1167c6bc | 303 | ret = nouveau_channel_new(drm, &drm->client.device, |
0ad72863 | 304 | NvDmaFB, NvDmaTT, &drm->cechan); |
00fc6f6f BS |
305 | if (ret) |
306 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | |
307 | ||
308 | arg0 = NvDmaFB; | |
309 | arg1 = NvDmaTT; | |
49981046 BS |
310 | } else { |
311 | arg0 = NvDmaFB; | |
312 | arg1 = NvDmaTT; | |
313 | } | |
314 | ||
1167c6bc BS |
315 | ret = nouveau_channel_new(drm, &drm->client.device, |
316 | arg0, arg1, &drm->channel); | |
ebb945a9 BS |
317 | if (ret) { |
318 | NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); | |
319 | nouveau_accel_fini(drm); | |
320 | return; | |
321 | } | |
322 | ||
a01ca78c | 323 | ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, |
0ad72863 | 324 | nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); |
69a6146d | 325 | if (ret == 0) { |
69a6146d BS |
326 | ret = RING_SPACE(drm->channel, 2); |
327 | if (ret == 0) { | |
967e7bde | 328 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
69a6146d BS |
329 | BEGIN_NV04(drm->channel, NvSubSw, 0, 1); |
330 | OUT_RING (drm->channel, NVDRM_NVSW); | |
331 | } else | |
967e7bde | 332 | if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) { |
69a6146d BS |
333 | BEGIN_NVC0(drm->channel, FermiSw, 0, 1); |
334 | OUT_RING (drm->channel, 0x001f0000); | |
335 | } | |
336 | } | |
898a2b32 BS |
337 | |
338 | ret = nvif_notify_init(&drm->nvsw, nouveau_flip_complete, | |
538b269b BS |
339 | false, NV04_NVSW_NTFY_UEVENT, |
340 | NULL, 0, 0, &drm->flip); | |
898a2b32 BS |
341 | if (ret == 0) |
342 | ret = nvif_notify_get(&drm->flip); | |
343 | if (ret) { | |
344 | nouveau_accel_fini(drm); | |
345 | return; | |
346 | } | |
69a6146d BS |
347 | } |
348 | ||
349 | if (ret) { | |
350 | NV_ERROR(drm, "failed to allocate software object, %d\n", ret); | |
351 | nouveau_accel_fini(drm); | |
352 | return; | |
353 | } | |
354 | ||
967e7bde | 355 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
1167c6bc BS |
356 | ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0, |
357 | false, NULL, &drm->notify); | |
ebb945a9 BS |
358 | if (ret) { |
359 | NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); | |
360 | nouveau_accel_fini(drm); | |
361 | return; | |
362 | } | |
363 | ||
a01ca78c | 364 | ret = nvif_object_init(&drm->channel->user, NvNotify0, |
4acfd707 BS |
365 | NV_DMA_IN_MEMORY, |
366 | &(struct nv_dma_v0) { | |
367 | .target = NV_DMA_V0_TARGET_VRAM, | |
368 | .access = NV_DMA_V0_ACCESS_RDWR, | |
ebb945a9 BS |
369 | .start = drm->notify->addr, |
370 | .limit = drm->notify->addr + 31 | |
4acfd707 | 371 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 372 | &drm->ntfy); |
ebb945a9 BS |
373 | if (ret) { |
374 | nouveau_accel_fini(drm); | |
375 | return; | |
376 | } | |
377 | } | |
378 | ||
379 | ||
49981046 | 380 | nouveau_bo_move_init(drm); |
ebb945a9 BS |
381 | } |
382 | ||
56550d94 GKH |
383 | static int nouveau_drm_probe(struct pci_dev *pdev, |
384 | const struct pci_device_id *pent) | |
94580299 | 385 | { |
be83cd4e | 386 | struct nvkm_device *device; |
ebb945a9 BS |
387 | struct apertures_struct *aper; |
388 | bool boot = false; | |
94580299 BS |
389 | int ret; |
390 | ||
b00e5334 | 391 | if (vga_switcheroo_client_probe_defer(pdev)) |
98b3a340 LW |
392 | return -EPROBE_DEFER; |
393 | ||
0e67bed2 BS |
394 | /* We need to check that the chipset is supported before booting |
395 | * fbdev off the hardware, as there's no way to put it back. | |
396 | */ | |
397 | ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device); | |
398 | if (ret) | |
399 | return ret; | |
400 | ||
401 | nvkm_device_del(&device); | |
402 | ||
403 | /* Remove conflicting drivers (vesafb, efifb etc). */ | |
ebb945a9 BS |
404 | aper = alloc_apertures(3); |
405 | if (!aper) | |
406 | return -ENOMEM; | |
407 | ||
408 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
409 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
410 | aper->count = 1; | |
411 | ||
412 | if (pci_resource_len(pdev, 2)) { | |
413 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
414 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
415 | aper->count++; | |
416 | } | |
417 | ||
418 | if (pci_resource_len(pdev, 3)) { | |
419 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
420 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
421 | aper->count++; | |
422 | } | |
423 | ||
424 | #ifdef CONFIG_X86 | |
425 | boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
426 | #endif | |
771fa0e4 | 427 | if (nouveau_modeset != 2) |
44adece5 | 428 | drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot); |
83ef7777 | 429 | kfree(aper); |
ebb945a9 | 430 | |
7974dd1b BS |
431 | ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, |
432 | true, true, ~0ULL, &device); | |
94580299 BS |
433 | if (ret) |
434 | return ret; | |
435 | ||
436 | pci_set_master(pdev); | |
437 | ||
915b4d11 | 438 | ret = drm_get_pci_dev(pdev, pent, &driver_pci); |
94580299 | 439 | if (ret) { |
e781dc8f | 440 | nvkm_device_del(&device); |
94580299 BS |
441 | return ret; |
442 | } | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
5addcf0a DA |
447 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 |
448 | ||
449 | static void | |
46941b0f | 450 | nouveau_get_hdmi_dev(struct nouveau_drm *drm) |
5addcf0a | 451 | { |
46941b0f | 452 | struct pci_dev *pdev = drm->dev->pdev; |
5addcf0a | 453 | |
420b9469 | 454 | if (!pdev) { |
f2a0adad | 455 | NV_DEBUG(drm, "not a PCI device; no HDMI\n"); |
420b9469 AC |
456 | drm->hdmi_device = NULL; |
457 | return; | |
458 | } | |
459 | ||
5addcf0a DA |
460 | /* subfunction one is a hdmi audio device? */ |
461 | drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number, | |
462 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 1)); | |
463 | ||
464 | if (!drm->hdmi_device) { | |
46941b0f | 465 | NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1); |
5addcf0a DA |
466 | return; |
467 | } | |
468 | ||
469 | if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) { | |
46941b0f | 470 | NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class); |
5addcf0a DA |
471 | pci_dev_put(drm->hdmi_device); |
472 | drm->hdmi_device = NULL; | |
473 | return; | |
474 | } | |
475 | } | |
476 | ||
5b8a43ae | 477 | static int |
94580299 BS |
478 | nouveau_drm_load(struct drm_device *dev, unsigned long flags) |
479 | { | |
94580299 BS |
480 | struct nouveau_drm *drm; |
481 | int ret; | |
482 | ||
20d8a88e BS |
483 | if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) |
484 | return -ENOMEM; | |
485 | dev->dev_private = drm; | |
486 | drm->dev = dev; | |
487 | ||
cb7e88e7 BS |
488 | ret = nouveau_cli_init(drm, "DRM-master", &drm->master); |
489 | if (ret) | |
490 | return ret; | |
491 | ||
20d8a88e | 492 | ret = nouveau_cli_init(drm, "DRM", &drm->client); |
94580299 BS |
493 | if (ret) |
494 | return ret; | |
495 | ||
1167c6bc BS |
496 | dev->irq_enabled = true; |
497 | ||
989aa5b7 | 498 | nvxx_client(&drm->client.base)->debug = |
be83cd4e | 499 | nvkm_dbgopt(nouveau_debug, "DRM"); |
77145f1c | 500 | |
94580299 | 501 | INIT_LIST_HEAD(&drm->clients); |
ebb945a9 | 502 | spin_lock_init(&drm->tile.lock); |
94580299 | 503 | |
46941b0f | 504 | nouveau_get_hdmi_dev(drm); |
5addcf0a | 505 | |
77145f1c BS |
506 | /* workaround an odd issue on nvc1 by disabling the device's |
507 | * nosnoop capability. hopefully won't cause issues until a | |
508 | * better fix is found - assuming there is one... | |
509 | */ | |
1167c6bc BS |
510 | if (drm->client.device.info.chipset == 0xc1) |
511 | nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); | |
ebb945a9 | 512 | |
77145f1c | 513 | nouveau_vga_init(drm); |
cb75d97e | 514 | |
ebb945a9 | 515 | ret = nouveau_ttm_init(drm); |
94580299 | 516 | if (ret) |
77145f1c BS |
517 | goto fail_ttm; |
518 | ||
519 | ret = nouveau_bios_init(dev); | |
520 | if (ret) | |
521 | goto fail_bios; | |
522 | ||
77145f1c | 523 | ret = nouveau_display_create(dev); |
ebb945a9 | 524 | if (ret) |
77145f1c BS |
525 | goto fail_dispctor; |
526 | ||
527 | if (dev->mode_config.num_crtc) { | |
528 | ret = nouveau_display_init(dev); | |
529 | if (ret) | |
530 | goto fail_dispinit; | |
531 | } | |
532 | ||
b126a200 | 533 | nouveau_debugfs_init(drm); |
b9ed919f | 534 | nouveau_hwmon_init(dev); |
ebb945a9 BS |
535 | nouveau_accel_init(drm); |
536 | nouveau_fbcon_init(dev); | |
8d021d71 | 537 | nouveau_led_init(dev); |
5addcf0a | 538 | |
8fa4338a | 539 | if (nouveau_pmops_runtime()) { |
5addcf0a DA |
540 | pm_runtime_use_autosuspend(dev->dev); |
541 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
542 | pm_runtime_set_active(dev->dev); | |
543 | pm_runtime_allow(dev->dev); | |
544 | pm_runtime_mark_last_busy(dev->dev); | |
545 | pm_runtime_put(dev->dev); | |
9a2eba33 PU |
546 | } else { |
547 | /* enable polling for external displays */ | |
548 | drm_kms_helper_poll_enable(dev); | |
5addcf0a | 549 | } |
94580299 BS |
550 | return 0; |
551 | ||
77145f1c BS |
552 | fail_dispinit: |
553 | nouveau_display_destroy(dev); | |
554 | fail_dispctor: | |
77145f1c BS |
555 | nouveau_bios_takedown(dev); |
556 | fail_bios: | |
ebb945a9 | 557 | nouveau_ttm_fini(drm); |
77145f1c | 558 | fail_ttm: |
77145f1c | 559 | nouveau_vga_fini(drm); |
20d8a88e | 560 | nouveau_cli_fini(&drm->client); |
cb7e88e7 | 561 | nouveau_cli_fini(&drm->master); |
20d8a88e | 562 | kfree(drm); |
94580299 BS |
563 | return ret; |
564 | } | |
565 | ||
11b3c20b | 566 | static void |
94580299 BS |
567 | nouveau_drm_unload(struct drm_device *dev) |
568 | { | |
77145f1c | 569 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 | 570 | |
8fa4338a | 571 | if (nouveau_pmops_runtime()) { |
c1b16b45 | 572 | pm_runtime_get_sync(dev->dev); |
55c868a3 | 573 | pm_runtime_forbid(dev->dev); |
c1b16b45 LW |
574 | } |
575 | ||
8d021d71 | 576 | nouveau_led_fini(dev); |
ebb945a9 BS |
577 | nouveau_fbcon_fini(dev); |
578 | nouveau_accel_fini(drm); | |
b9ed919f | 579 | nouveau_hwmon_fini(dev); |
b126a200 | 580 | nouveau_debugfs_fini(drm); |
77145f1c | 581 | |
9430738d | 582 | if (dev->mode_config.num_crtc) |
3b4c0abb | 583 | nouveau_display_fini(dev, false); |
77145f1c BS |
584 | nouveau_display_destroy(dev); |
585 | ||
77145f1c | 586 | nouveau_bios_takedown(dev); |
94580299 | 587 | |
ebb945a9 | 588 | nouveau_ttm_fini(drm); |
77145f1c | 589 | nouveau_vga_fini(drm); |
cb75d97e | 590 | |
5addcf0a DA |
591 | if (drm->hdmi_device) |
592 | pci_dev_put(drm->hdmi_device); | |
20d8a88e | 593 | nouveau_cli_fini(&drm->client); |
cb7e88e7 | 594 | nouveau_cli_fini(&drm->master); |
20d8a88e | 595 | kfree(drm); |
94580299 BS |
596 | } |
597 | ||
8ba9ff11 AC |
598 | void |
599 | nouveau_drm_device_remove(struct drm_device *dev) | |
94580299 | 600 | { |
77145f1c | 601 | struct nouveau_drm *drm = nouveau_drm(dev); |
be83cd4e | 602 | struct nvkm_client *client; |
76ecea5b | 603 | struct nvkm_device *device; |
77145f1c | 604 | |
7d3428cd | 605 | dev->irq_enabled = false; |
989aa5b7 | 606 | client = nvxx_client(&drm->client.base); |
4e7e62d6 | 607 | device = nvkm_device_find(client->device); |
77145f1c BS |
608 | drm_put_dev(dev); |
609 | ||
e781dc8f | 610 | nvkm_device_del(&device); |
94580299 | 611 | } |
8ba9ff11 AC |
612 | |
613 | static void | |
614 | nouveau_drm_remove(struct pci_dev *pdev) | |
615 | { | |
616 | struct drm_device *dev = pci_get_drvdata(pdev); | |
617 | ||
618 | nouveau_drm_device_remove(dev); | |
619 | } | |
94580299 | 620 | |
cd897837 | 621 | static int |
05c63c2f | 622 | nouveau_do_suspend(struct drm_device *dev, bool runtime) |
94580299 | 623 | { |
77145f1c | 624 | struct nouveau_drm *drm = nouveau_drm(dev); |
94580299 BS |
625 | int ret; |
626 | ||
8d021d71 MP |
627 | nouveau_led_suspend(dev); |
628 | ||
6fbb702e | 629 | if (dev->mode_config.num_crtc) { |
2d38a535 | 630 | NV_DEBUG(drm, "suspending console...\n"); |
6fbb702e | 631 | nouveau_fbcon_set_suspend(dev, 1); |
2d38a535 | 632 | NV_DEBUG(drm, "suspending display...\n"); |
6fbb702e | 633 | ret = nouveau_display_suspend(dev, runtime); |
9430738d BS |
634 | if (ret) |
635 | return ret; | |
636 | } | |
94580299 | 637 | |
2d38a535 | 638 | NV_DEBUG(drm, "evicting buffers...\n"); |
ebb945a9 BS |
639 | ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); |
640 | ||
2d38a535 | 641 | NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); |
81dff21b BS |
642 | if (drm->cechan) { |
643 | ret = nouveau_channel_idle(drm->cechan); | |
644 | if (ret) | |
f3980dc5 | 645 | goto fail_display; |
81dff21b BS |
646 | } |
647 | ||
648 | if (drm->channel) { | |
649 | ret = nouveau_channel_idle(drm->channel); | |
650 | if (ret) | |
f3980dc5 | 651 | goto fail_display; |
81dff21b BS |
652 | } |
653 | ||
2d38a535 | 654 | NV_DEBUG(drm, "suspending fence...\n"); |
ebb945a9 | 655 | if (drm->fence && nouveau_fence(drm)->suspend) { |
f3980dc5 IM |
656 | if (!nouveau_fence(drm)->suspend(drm)) { |
657 | ret = -ENOMEM; | |
658 | goto fail_display; | |
659 | } | |
ebb945a9 BS |
660 | } |
661 | ||
2d38a535 | 662 | NV_DEBUG(drm, "suspending object tree...\n"); |
cb7e88e7 | 663 | ret = nvif_client_suspend(&drm->master.base); |
94580299 BS |
664 | if (ret) |
665 | goto fail_client; | |
666 | ||
94580299 BS |
667 | return 0; |
668 | ||
669 | fail_client: | |
f3980dc5 IM |
670 | if (drm->fence && nouveau_fence(drm)->resume) |
671 | nouveau_fence(drm)->resume(drm); | |
672 | ||
673 | fail_display: | |
9430738d | 674 | if (dev->mode_config.num_crtc) { |
2d38a535 | 675 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 676 | nouveau_display_resume(dev, runtime); |
9430738d | 677 | } |
94580299 BS |
678 | return ret; |
679 | } | |
680 | ||
cd897837 | 681 | static int |
6fbb702e | 682 | nouveau_do_resume(struct drm_device *dev, bool runtime) |
2d8b9ccb DA |
683 | { |
684 | struct nouveau_drm *drm = nouveau_drm(dev); | |
2d8b9ccb | 685 | |
2d38a535 | 686 | NV_DEBUG(drm, "resuming object tree...\n"); |
cb7e88e7 | 687 | nvif_client_resume(&drm->master.base); |
94580299 | 688 | |
2d38a535 | 689 | NV_DEBUG(drm, "resuming fence...\n"); |
81dff21b BS |
690 | if (drm->fence && nouveau_fence(drm)->resume) |
691 | nouveau_fence(drm)->resume(drm); | |
692 | ||
77145f1c | 693 | nouveau_run_vbios_init(dev); |
77145f1c | 694 | |
9430738d | 695 | if (dev->mode_config.num_crtc) { |
2d38a535 | 696 | NV_DEBUG(drm, "resuming display...\n"); |
6fbb702e | 697 | nouveau_display_resume(dev, runtime); |
2d38a535 | 698 | NV_DEBUG(drm, "resuming console...\n"); |
6fbb702e | 699 | nouveau_fbcon_set_suspend(dev, 0); |
9430738d | 700 | } |
5addcf0a | 701 | |
8d021d71 MP |
702 | nouveau_led_resume(dev); |
703 | ||
77145f1c | 704 | return 0; |
94580299 BS |
705 | } |
706 | ||
7bb6d442 BS |
707 | int |
708 | nouveau_pmops_suspend(struct device *dev) | |
709 | { | |
710 | struct pci_dev *pdev = to_pci_dev(dev); | |
711 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
712 | int ret; | |
713 | ||
714 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || | |
715 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
716 | return 0; | |
717 | ||
718 | ret = nouveau_do_suspend(drm_dev, false); | |
719 | if (ret) | |
720 | return ret; | |
721 | ||
722 | pci_save_state(pdev); | |
723 | pci_disable_device(pdev); | |
7bb6d442 | 724 | pci_set_power_state(pdev, PCI_D3hot); |
c5fd936e | 725 | udelay(200); |
7bb6d442 BS |
726 | return 0; |
727 | } | |
728 | ||
729 | int | |
730 | nouveau_pmops_resume(struct device *dev) | |
2d8b9ccb DA |
731 | { |
732 | struct pci_dev *pdev = to_pci_dev(dev); | |
733 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
734 | int ret; | |
735 | ||
5addcf0a DA |
736 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || |
737 | drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) | |
2d8b9ccb DA |
738 | return 0; |
739 | ||
740 | pci_set_power_state(pdev, PCI_D0); | |
741 | pci_restore_state(pdev); | |
742 | ret = pci_enable_device(pdev); | |
743 | if (ret) | |
744 | return ret; | |
745 | pci_set_master(pdev); | |
746 | ||
0b2fe659 HG |
747 | ret = nouveau_do_resume(drm_dev, false); |
748 | ||
749 | /* Monitors may have been connected / disconnected during suspend */ | |
750 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
751 | ||
752 | return ret; | |
2d8b9ccb DA |
753 | } |
754 | ||
7bb6d442 BS |
755 | static int |
756 | nouveau_pmops_freeze(struct device *dev) | |
2d8b9ccb DA |
757 | { |
758 | struct pci_dev *pdev = to_pci_dev(dev); | |
759 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 760 | return nouveau_do_suspend(drm_dev, false); |
2d8b9ccb DA |
761 | } |
762 | ||
7bb6d442 BS |
763 | static int |
764 | nouveau_pmops_thaw(struct device *dev) | |
2d8b9ccb DA |
765 | { |
766 | struct pci_dev *pdev = to_pci_dev(dev); | |
767 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6fbb702e | 768 | return nouveau_do_resume(drm_dev, false); |
2d8b9ccb DA |
769 | } |
770 | ||
321f5c5f | 771 | bool |
5499473c | 772 | nouveau_pmops_runtime(void) |
321f5c5f BS |
773 | { |
774 | if (nouveau_runtime_pm == -1) | |
775 | return nouveau_is_optimus() || nouveau_is_v1_dsm(); | |
776 | return nouveau_runtime_pm == 1; | |
777 | } | |
778 | ||
7bb6d442 BS |
779 | static int |
780 | nouveau_pmops_runtime_suspend(struct device *dev) | |
781 | { | |
782 | struct pci_dev *pdev = to_pci_dev(dev); | |
783 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
784 | int ret; | |
785 | ||
321f5c5f | 786 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
787 | pm_runtime_forbid(dev); |
788 | return -EBUSY; | |
789 | } | |
790 | ||
7bb6d442 BS |
791 | drm_kms_helper_poll_disable(drm_dev); |
792 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
793 | nouveau_switcheroo_optimus_dsm(); | |
794 | ret = nouveau_do_suspend(drm_dev, true); | |
795 | pci_save_state(pdev); | |
796 | pci_disable_device(pdev); | |
8c863944 | 797 | pci_ignore_hotplug(pdev); |
7bb6d442 BS |
798 | pci_set_power_state(pdev, PCI_D3cold); |
799 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; | |
800 | return ret; | |
801 | } | |
802 | ||
803 | static int | |
804 | nouveau_pmops_runtime_resume(struct device *dev) | |
805 | { | |
806 | struct pci_dev *pdev = to_pci_dev(dev); | |
807 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1167c6bc | 808 | struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; |
7bb6d442 BS |
809 | int ret; |
810 | ||
321f5c5f BS |
811 | if (!nouveau_pmops_runtime()) { |
812 | pm_runtime_forbid(dev); | |
813 | return -EBUSY; | |
814 | } | |
7bb6d442 BS |
815 | |
816 | pci_set_power_state(pdev, PCI_D0); | |
817 | pci_restore_state(pdev); | |
818 | ret = pci_enable_device(pdev); | |
819 | if (ret) | |
820 | return ret; | |
821 | pci_set_master(pdev); | |
822 | ||
823 | ret = nouveau_do_resume(drm_dev, true); | |
cae9ff03 | 824 | |
7bb6d442 | 825 | /* do magic */ |
a01ca78c | 826 | nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); |
7bb6d442 BS |
827 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); |
828 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
0b2fe659 HG |
829 | |
830 | /* Monitors may have been connected / disconnected during suspend */ | |
831 | schedule_work(&nouveau_drm(drm_dev)->hpd_work); | |
832 | ||
7bb6d442 BS |
833 | return ret; |
834 | } | |
835 | ||
836 | static int | |
837 | nouveau_pmops_runtime_idle(struct device *dev) | |
838 | { | |
839 | struct pci_dev *pdev = to_pci_dev(dev); | |
840 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
841 | struct nouveau_drm *drm = nouveau_drm(drm_dev); | |
842 | struct drm_crtc *crtc; | |
843 | ||
321f5c5f | 844 | if (!nouveau_pmops_runtime()) { |
7bb6d442 BS |
845 | pm_runtime_forbid(dev); |
846 | return -EBUSY; | |
847 | } | |
848 | ||
849 | /* if we have a hdmi audio device - make sure it has a driver loaded */ | |
850 | if (drm->hdmi_device) { | |
851 | if (!drm->hdmi_device->driver) { | |
852 | DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n"); | |
853 | pm_runtime_mark_last_busy(dev); | |
854 | return -EBUSY; | |
855 | } | |
856 | } | |
857 | ||
858 | list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) { | |
859 | if (crtc->enabled) { | |
860 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
861 | return -EBUSY; | |
862 | } | |
863 | } | |
864 | pm_runtime_mark_last_busy(dev); | |
865 | pm_runtime_autosuspend(dev); | |
866 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
867 | return 1; | |
868 | } | |
2d8b9ccb | 869 | |
5b8a43ae | 870 | static int |
ebb945a9 BS |
871 | nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) |
872 | { | |
ebb945a9 BS |
873 | struct nouveau_drm *drm = nouveau_drm(dev); |
874 | struct nouveau_cli *cli; | |
a2896ced | 875 | char name[32], tmpname[TASK_COMM_LEN]; |
ebb945a9 BS |
876 | int ret; |
877 | ||
5addcf0a DA |
878 | /* need to bring up power immediately if opening device */ |
879 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 880 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
881 | return ret; |
882 | ||
a2896ced MS |
883 | get_task_comm(tmpname, current); |
884 | snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); | |
fa6df8c1 | 885 | |
20d8a88e BS |
886 | if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) |
887 | return ret; | |
420b9469 | 888 | |
20d8a88e | 889 | ret = nouveau_cli_init(drm, name, cli); |
ebb945a9 | 890 | if (ret) |
20d8a88e | 891 | goto done; |
ebb945a9 | 892 | |
0ad72863 BS |
893 | cli->base.super = false; |
894 | ||
ebb945a9 BS |
895 | fpriv->driver_priv = cli; |
896 | ||
897 | mutex_lock(&drm->client.mutex); | |
898 | list_add(&cli->head, &drm->clients); | |
899 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 900 | |
20d8a88e BS |
901 | done: |
902 | if (ret && cli) { | |
903 | nouveau_cli_fini(cli); | |
904 | kfree(cli); | |
905 | } | |
906 | ||
5addcf0a DA |
907 | pm_runtime_mark_last_busy(dev->dev); |
908 | pm_runtime_put_autosuspend(dev->dev); | |
5addcf0a | 909 | return ret; |
ebb945a9 BS |
910 | } |
911 | ||
5b8a43ae | 912 | static void |
f0e73ff3 | 913 | nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) |
ebb945a9 BS |
914 | { |
915 | struct nouveau_cli *cli = nouveau_cli(fpriv); | |
916 | struct nouveau_drm *drm = nouveau_drm(dev); | |
917 | ||
5addcf0a DA |
918 | pm_runtime_get_sync(dev->dev); |
919 | ||
ac8c7930 | 920 | mutex_lock(&cli->mutex); |
ebb945a9 BS |
921 | if (cli->abi16) |
922 | nouveau_abi16_fini(cli->abi16); | |
ac8c7930 | 923 | mutex_unlock(&cli->mutex); |
ebb945a9 BS |
924 | |
925 | mutex_lock(&drm->client.mutex); | |
926 | list_del(&cli->head); | |
927 | mutex_unlock(&drm->client.mutex); | |
5addcf0a | 928 | |
20d8a88e BS |
929 | nouveau_cli_fini(cli); |
930 | kfree(cli); | |
5addcf0a DA |
931 | pm_runtime_mark_last_busy(dev->dev); |
932 | pm_runtime_put_autosuspend(dev->dev); | |
ebb945a9 BS |
933 | } |
934 | ||
baa70943 | 935 | static const struct drm_ioctl_desc |
77145f1c | 936 | nouveau_ioctls[] = { |
f8c47144 DV |
937 | DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW), |
938 | DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
939 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
940 | DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
941 | DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
942 | DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), | |
943 | DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW), | |
944 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW), | |
945 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW), | |
946 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), | |
947 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), | |
948 | DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW), | |
77145f1c BS |
949 | }; |
950 | ||
27111a23 BS |
951 | long |
952 | nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
5addcf0a | 953 | { |
27111a23 BS |
954 | struct drm_file *filp = file->private_data; |
955 | struct drm_device *dev = filp->minor->dev; | |
5addcf0a | 956 | long ret; |
5addcf0a DA |
957 | |
958 | ret = pm_runtime_get_sync(dev->dev); | |
b6c4285a | 959 | if (ret < 0 && ret != -EACCES) |
5addcf0a DA |
960 | return ret; |
961 | ||
27111a23 BS |
962 | switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { |
963 | case DRM_NOUVEAU_NVIF: | |
964 | ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); | |
965 | break; | |
966 | default: | |
967 | ret = drm_ioctl(file, cmd, arg); | |
968 | break; | |
969 | } | |
5addcf0a DA |
970 | |
971 | pm_runtime_mark_last_busy(dev->dev); | |
972 | pm_runtime_put_autosuspend(dev->dev); | |
973 | return ret; | |
974 | } | |
27111a23 | 975 | |
77145f1c BS |
976 | static const struct file_operations |
977 | nouveau_driver_fops = { | |
978 | .owner = THIS_MODULE, | |
979 | .open = drm_open, | |
980 | .release = drm_release, | |
5addcf0a | 981 | .unlocked_ioctl = nouveau_drm_ioctl, |
77145f1c BS |
982 | .mmap = nouveau_ttm_mmap, |
983 | .poll = drm_poll, | |
77145f1c BS |
984 | .read = drm_read, |
985 | #if defined(CONFIG_COMPAT) | |
986 | .compat_ioctl = nouveau_compat_ioctl, | |
987 | #endif | |
988 | .llseek = noop_llseek, | |
989 | }; | |
990 | ||
991 | static struct drm_driver | |
915b4d11 | 992 | driver_stub = { |
77145f1c | 993 | .driver_features = |
0e975980 PA |
994 | DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | |
995 | DRIVER_KMS_LEGACY_CONTEXT, | |
77145f1c BS |
996 | |
997 | .load = nouveau_drm_load, | |
998 | .unload = nouveau_drm_unload, | |
999 | .open = nouveau_drm_open, | |
77145f1c BS |
1000 | .postclose = nouveau_drm_postclose, |
1001 | .lastclose = nouveau_vga_lastclose, | |
1002 | ||
33b903e8 | 1003 | #if defined(CONFIG_DEBUG_FS) |
56c101af | 1004 | .debugfs_init = nouveau_drm_debugfs_init, |
33b903e8 MS |
1005 | #endif |
1006 | ||
51cb4b39 BS |
1007 | .enable_vblank = nouveau_display_vblank_enable, |
1008 | .disable_vblank = nouveau_display_vblank_disable, | |
d83ef853 | 1009 | .get_scanout_position = nouveau_display_scanoutpos, |
1bf6ad62 | 1010 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
77145f1c BS |
1011 | |
1012 | .ioctls = nouveau_ioctls, | |
baa70943 | 1013 | .num_ioctls = ARRAY_SIZE(nouveau_ioctls), |
77145f1c BS |
1014 | .fops = &nouveau_driver_fops, |
1015 | ||
1016 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1017 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
ab9ccb96 AP |
1018 | .gem_prime_export = drm_gem_prime_export, |
1019 | .gem_prime_import = drm_gem_prime_import, | |
1020 | .gem_prime_pin = nouveau_gem_prime_pin, | |
3aac4502 | 1021 | .gem_prime_res_obj = nouveau_gem_prime_res_obj, |
1af7c7dd | 1022 | .gem_prime_unpin = nouveau_gem_prime_unpin, |
ab9ccb96 AP |
1023 | .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, |
1024 | .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, | |
1025 | .gem_prime_vmap = nouveau_gem_prime_vmap, | |
1026 | .gem_prime_vunmap = nouveau_gem_prime_vunmap, | |
77145f1c | 1027 | |
a51e6ac4 | 1028 | .gem_free_object_unlocked = nouveau_gem_object_del, |
77145f1c BS |
1029 | .gem_open_object = nouveau_gem_object_open, |
1030 | .gem_close_object = nouveau_gem_object_close, | |
1031 | ||
1032 | .dumb_create = nouveau_display_dumb_create, | |
1033 | .dumb_map_offset = nouveau_display_dumb_map_offset, | |
77145f1c BS |
1034 | |
1035 | .name = DRIVER_NAME, | |
1036 | .desc = DRIVER_DESC, | |
1037 | #ifdef GIT_REVISION | |
1038 | .date = GIT_REVISION, | |
1039 | #else | |
1040 | .date = DRIVER_DATE, | |
1041 | #endif | |
1042 | .major = DRIVER_MAJOR, | |
1043 | .minor = DRIVER_MINOR, | |
1044 | .patchlevel = DRIVER_PATCHLEVEL, | |
1045 | }; | |
1046 | ||
94580299 BS |
1047 | static struct pci_device_id |
1048 | nouveau_drm_pci_table[] = { | |
1049 | { | |
1050 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
1051 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1052 | .class_mask = 0xff << 16, | |
1053 | }, | |
1054 | { | |
1055 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
1056 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
1057 | .class_mask = 0xff << 16, | |
1058 | }, | |
1059 | {} | |
1060 | }; | |
1061 | ||
703fa264 PM |
1062 | static void nouveau_display_options(void) |
1063 | { | |
1064 | DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); | |
1065 | ||
1066 | DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); | |
1067 | DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); | |
1068 | DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); | |
1069 | DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); | |
1070 | DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); | |
1071 | DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); | |
1072 | DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); | |
1073 | DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); | |
1074 | DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); | |
1075 | DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); | |
f3a8b664 | 1076 | DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); |
703fa264 PM |
1077 | } |
1078 | ||
2d8b9ccb DA |
1079 | static const struct dev_pm_ops nouveau_pm_ops = { |
1080 | .suspend = nouveau_pmops_suspend, | |
1081 | .resume = nouveau_pmops_resume, | |
1082 | .freeze = nouveau_pmops_freeze, | |
1083 | .thaw = nouveau_pmops_thaw, | |
1084 | .poweroff = nouveau_pmops_freeze, | |
1085 | .restore = nouveau_pmops_resume, | |
5addcf0a DA |
1086 | .runtime_suspend = nouveau_pmops_runtime_suspend, |
1087 | .runtime_resume = nouveau_pmops_runtime_resume, | |
1088 | .runtime_idle = nouveau_pmops_runtime_idle, | |
2d8b9ccb DA |
1089 | }; |
1090 | ||
94580299 BS |
1091 | static struct pci_driver |
1092 | nouveau_drm_pci_driver = { | |
1093 | .name = "nouveau", | |
1094 | .id_table = nouveau_drm_pci_table, | |
1095 | .probe = nouveau_drm_probe, | |
1096 | .remove = nouveau_drm_remove, | |
2d8b9ccb | 1097 | .driver.pm = &nouveau_pm_ops, |
94580299 BS |
1098 | }; |
1099 | ||
8ba9ff11 | 1100 | struct drm_device * |
e396ecd1 AC |
1101 | nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, |
1102 | struct platform_device *pdev, | |
47b2505e | 1103 | struct nvkm_device **pdevice) |
420b9469 | 1104 | { |
8ba9ff11 AC |
1105 | struct drm_device *drm; |
1106 | int err; | |
420b9469 | 1107 | |
e396ecd1 | 1108 | err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, |
7974dd1b | 1109 | true, true, ~0ULL, pdevice); |
8ba9ff11 | 1110 | if (err) |
e781dc8f | 1111 | goto err_free; |
8ba9ff11 | 1112 | |
915b4d11 | 1113 | drm = drm_dev_alloc(&driver_platform, &pdev->dev); |
0f288605 TG |
1114 | if (IS_ERR(drm)) { |
1115 | err = PTR_ERR(drm); | |
8ba9ff11 | 1116 | goto err_free; |
420b9469 AC |
1117 | } |
1118 | ||
8ba9ff11 AC |
1119 | platform_set_drvdata(pdev, drm); |
1120 | ||
1121 | return drm; | |
1122 | ||
1123 | err_free: | |
e781dc8f | 1124 | nvkm_device_del(pdevice); |
8ba9ff11 AC |
1125 | |
1126 | return ERR_PTR(err); | |
420b9469 AC |
1127 | } |
1128 | ||
94580299 BS |
1129 | static int __init |
1130 | nouveau_drm_init(void) | |
1131 | { | |
915b4d11 | 1132 | driver_pci = driver_stub; |
915b4d11 | 1133 | driver_platform = driver_stub; |
915b4d11 | 1134 | |
703fa264 PM |
1135 | nouveau_display_options(); |
1136 | ||
77145f1c | 1137 | if (nouveau_modeset == -1) { |
77145f1c BS |
1138 | if (vgacon_text_force()) |
1139 | nouveau_modeset = 0; | |
77145f1c BS |
1140 | } |
1141 | ||
1142 | if (!nouveau_modeset) | |
1143 | return 0; | |
1144 | ||
055a65d5 AC |
1145 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER |
1146 | platform_driver_register(&nouveau_platform_driver); | |
1147 | #endif | |
1148 | ||
77145f1c | 1149 | nouveau_register_dsm_handler(); |
db1a0ae2 | 1150 | nouveau_backlight_ctor(); |
10631d72 DV |
1151 | |
1152 | #ifdef CONFIG_PCI | |
1153 | return pci_register_driver(&nouveau_drm_pci_driver); | |
1154 | #else | |
1155 | return 0; | |
1156 | #endif | |
94580299 BS |
1157 | } |
1158 | ||
1159 | static void __exit | |
1160 | nouveau_drm_exit(void) | |
1161 | { | |
77145f1c BS |
1162 | if (!nouveau_modeset) |
1163 | return; | |
1164 | ||
10631d72 DV |
1165 | #ifdef CONFIG_PCI |
1166 | pci_unregister_driver(&nouveau_drm_pci_driver); | |
1167 | #endif | |
db1a0ae2 | 1168 | nouveau_backlight_dtor(); |
77145f1c | 1169 | nouveau_unregister_dsm_handler(); |
055a65d5 AC |
1170 | |
1171 | #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER | |
1172 | platform_driver_unregister(&nouveau_platform_driver); | |
1173 | #endif | |
94580299 BS |
1174 | } |
1175 | ||
1176 | module_init(nouveau_drm_init); | |
1177 | module_exit(nouveau_drm_exit); | |
1178 | ||
1179 | MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); | |
77145f1c BS |
1180 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1181 | MODULE_DESCRIPTION(DRIVER_DESC); | |
94580299 | 1182 | MODULE_LICENSE("GPL and additional rights"); |