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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drm.c
CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
c5fd936e 26#include <linux/delay.h>
94580299
BS
27#include <linux/module.h>
28#include <linux/pci.h>
5addcf0a
DA
29#include <linux/pm_runtime.h>
30#include <linux/vga_switcheroo.h>
fdb751ef 31
ae95621b
MY
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
fdb751ef 34
ebb945a9 35#include <core/gpuobj.h>
c33e05a1 36#include <core/option.h>
7974dd1b
BS
37#include <core/pci.h>
38#include <core/tegra.h>
94580299 39
04b88677 40#include <nvif/driver.h>
a7cf0180 41#include <nvif/fifo.h>
37e1c45a 42#include <nvif/user.h>
04b88677 43
923bc416 44#include <nvif/class.h>
845f2725 45#include <nvif/cl0002.h>
8ed1730c 46#include <nvif/cla06f.h>
538b269b 47
4dc28134 48#include "nouveau_drv.h"
ebb945a9 49#include "nouveau_dma.h"
77145f1c
BS
50#include "nouveau_ttm.h"
51#include "nouveau_gem.h"
77145f1c 52#include "nouveau_vga.h"
8d021d71 53#include "nouveau_led.h"
b9ed919f 54#include "nouveau_hwmon.h"
77145f1c
BS
55#include "nouveau_acpi.h"
56#include "nouveau_bios.h"
57#include "nouveau_ioctl.h"
ebb945a9
BS
58#include "nouveau_abi16.h"
59#include "nouveau_fbcon.h"
60#include "nouveau_fence.h"
33b903e8 61#include "nouveau_debugfs.h"
27111a23 62#include "nouveau_usif.h"
703fa264 63#include "nouveau_connector.h"
055a65d5 64#include "nouveau_platform.h"
eeaf06ac 65#include "nouveau_svm.h"
5be73b69 66#include "nouveau_dmem.h"
ebb945a9 67
94580299
BS
68MODULE_PARM_DESC(config, "option string to pass to driver core");
69static char *nouveau_config;
70module_param_named(config, nouveau_config, charp, 0400);
71
72MODULE_PARM_DESC(debug, "debug string to pass to driver core");
73static char *nouveau_debug;
74module_param_named(debug, nouveau_debug, charp, 0400);
75
ebb945a9
BS
76MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
77static int nouveau_noaccel = 0;
78module_param_named(noaccel, nouveau_noaccel, int, 0400);
79
9430738d
BS
80MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
81 "0 = disabled, 1 = enabled, 2 = headless)");
82int nouveau_modeset = -1;
77145f1c
BS
83module_param_named(modeset, nouveau_modeset, int, 0400);
84
eb493fbc
LP
85MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
86static int nouveau_atomic = 0;
87module_param_named(atomic, nouveau_atomic, int, 0400);
88
5addcf0a 89MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
321f5c5f 90static int nouveau_runtime_pm = -1;
5addcf0a
DA
91module_param_named(runpm, nouveau_runtime_pm, int, 0400);
92
915b4d11
DH
93static struct drm_driver driver_stub;
94static struct drm_driver driver_pci;
95static struct drm_driver driver_platform;
77145f1c 96
94580299 97static u64
420b9469 98nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
99{
100 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
101 name |= pdev->bus->number << 16;
102 name |= PCI_SLOT(pdev->devfn) << 8;
103 return name | PCI_FUNC(pdev->devfn);
104}
105
420b9469
AC
106static u64
107nouveau_platform_name(struct platform_device *platformdev)
108{
109 return platformdev->id;
110}
111
112static u64
113nouveau_name(struct drm_device *dev)
114{
115 if (dev->pdev)
116 return nouveau_pci_name(dev->pdev);
117 else
76adb460 118 return nouveau_platform_name(to_platform_device(dev->dev));
420b9469
AC
119}
120
814a2324 121static inline bool
11e451e7 122nouveau_cli_work_ready(struct dma_fence *fence)
814a2324 123{
11e451e7
BS
124 if (!dma_fence_is_signaled(fence))
125 return false;
814a2324
BS
126 dma_fence_put(fence);
127 return true;
128}
129
130static void
11e451e7 131nouveau_cli_work(struct work_struct *w)
814a2324 132{
11e451e7 133 struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
814a2324
BS
134 struct nouveau_cli_work *work, *wtmp;
135 mutex_lock(&cli->lock);
136 list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
11e451e7 137 if (!work->fence || nouveau_cli_work_ready(work->fence)) {
814a2324
BS
138 list_del(&work->head);
139 work->func(work);
140 }
141 }
142 mutex_unlock(&cli->lock);
143}
144
145static void
146nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
147{
148 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
149 schedule_work(&work->cli->work);
150}
151
152void
153nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
154 struct nouveau_cli_work *work)
155{
156 work->fence = dma_fence_get(fence);
157 work->cli = cli;
158 mutex_lock(&cli->lock);
159 list_add_tail(&work->head, &cli->worker);
814a2324
BS
160 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
161 nouveau_cli_work_fence(fence, &work->cb);
b26a2319 162 mutex_unlock(&cli->lock);
814a2324
BS
163}
164
20d8a88e
BS
165static void
166nouveau_cli_fini(struct nouveau_cli *cli)
167{
11e451e7
BS
168 /* All our channels are dead now, which means all the fences they
169 * own are signalled, and all callback functions have been called.
170 *
171 * So, after flushing the workqueue, there should be nothing left.
172 */
173 flush_work(&cli->work);
174 WARN_ON(!list_empty(&cli->worker));
175
20d8a88e 176 usif_client_fini(cli);
bfe91afa 177 nouveau_vmm_fini(&cli->svm);
24e8375b 178 nouveau_vmm_fini(&cli->vmm);
01670a79 179 nvif_mmu_fini(&cli->mmu);
1167c6bc 180 nvif_device_fini(&cli->device);
cb7e88e7 181 mutex_lock(&cli->drm->master.lock);
20d8a88e 182 nvif_client_fini(&cli->base);
cb7e88e7 183 mutex_unlock(&cli->drm->master.lock);
20d8a88e
BS
184}
185
94580299 186static int
20d8a88e
BS
187nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
188 struct nouveau_cli *cli)
94580299 189{
7f507624
BS
190 static const struct nvif_mclass
191 mems[] = {
192 { NVIF_CLASS_MEM_GF100, -1 },
193 { NVIF_CLASS_MEM_NV50 , -1 },
194 { NVIF_CLASS_MEM_NV04 , -1 },
195 {}
196 };
01670a79
BS
197 static const struct nvif_mclass
198 mmus[] = {
199 { NVIF_CLASS_MMU_GF100, -1 },
200 { NVIF_CLASS_MMU_NV50 , -1 },
201 { NVIF_CLASS_MMU_NV04 , -1 },
202 {}
203 };
96da0bcd
BS
204 static const struct nvif_mclass
205 vmms[] = {
206 { NVIF_CLASS_VMM_GP100, -1 },
207 { NVIF_CLASS_VMM_GM200, -1 },
208 { NVIF_CLASS_VMM_GF100, -1 },
209 { NVIF_CLASS_VMM_NV50 , -1 },
210 { NVIF_CLASS_VMM_NV04 , -1 },
211 {}
212 };
20d8a88e 213 u64 device = nouveau_name(drm->dev);
9ad97ede 214 int ret;
9ad97ede 215
20d8a88e 216 snprintf(cli->name, sizeof(cli->name), "%s", sname);
e75c091b 217 cli->drm = drm;
20d8a88e
BS
218 mutex_init(&cli->mutex);
219 usif_client_init(cli);
220
814a2324
BS
221 INIT_WORK(&cli->work, nouveau_cli_work);
222 INIT_LIST_HEAD(&cli->worker);
cb7e88e7
BS
223 mutex_init(&cli->lock);
224
225 if (cli == &drm->master) {
80e60973
BS
226 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
227 cli->name, device, &cli->base);
228 } else {
cb7e88e7
BS
229 mutex_lock(&drm->master.lock);
230 ret = nvif_client_init(&drm->master.base, cli->name, device,
9ad97ede 231 &cli->base);
cb7e88e7 232 mutex_unlock(&drm->master.lock);
dd5700ea 233 }
20d8a88e 234 if (ret) {
a43b16dd 235 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
20d8a88e 236 goto done;
dd5700ea 237 }
94580299 238
1167c6bc
BS
239 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE,
240 &(struct nv_device_v0) {
241 .device = ~0,
242 }, sizeof(struct nv_device_v0),
243 &cli->device);
244 if (ret) {
a43b16dd 245 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
1167c6bc
BS
246 goto done;
247 }
248
01670a79
BS
249 ret = nvif_mclass(&cli->device.object, mmus);
250 if (ret < 0) {
a43b16dd 251 NV_PRINTK(err, cli, "No supported MMU class\n");
01670a79
BS
252 goto done;
253 }
254
255 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu);
256 if (ret) {
a43b16dd 257 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
01670a79
BS
258 goto done;
259 }
260
96da0bcd
BS
261 ret = nvif_mclass(&cli->mmu.object, vmms);
262 if (ret < 0) {
a43b16dd 263 NV_PRINTK(err, cli, "No supported VMM class\n");
96da0bcd
BS
264 goto done;
265 }
266
267 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
268 if (ret) {
a43b16dd 269 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
96da0bcd
BS
270 goto done;
271 }
272
7f507624
BS
273 ret = nvif_mclass(&cli->mmu.object, mems);
274 if (ret < 0) {
a43b16dd 275 NV_PRINTK(err, cli, "No supported MEM class\n");
7f507624
BS
276 goto done;
277 }
278
279 cli->mem = &mems[ret];
7f507624 280 return 0;
20d8a88e
BS
281done:
282 if (ret)
283 nouveau_cli_fini(cli);
284 return ret;
94580299
BS
285}
286
ebb945a9 287static void
f0eee9ae
BS
288nouveau_accel_ce_fini(struct nouveau_drm *drm)
289{
290 nouveau_channel_idle(drm->cechan);
291 nvif_object_fini(&drm->ttm.copy);
292 nouveau_channel_del(&drm->cechan);
293}
294
295static void
296nouveau_accel_ce_init(struct nouveau_drm *drm)
297{
298 struct nvif_device *device = &drm->client.device;
299 int ret = 0;
300
301 /* Allocate channel that has access to a (preferably async) copy
302 * engine, to use for TTM buffer moves.
303 */
304 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
305 ret = nouveau_channel_new(drm, device,
306 nvif_fifo_runlist_ce(device), 0,
307 true, &drm->cechan);
308 } else
309 if (device->info.chipset >= 0xa3 &&
310 device->info.chipset != 0xaa &&
311 device->info.chipset != 0xac) {
312 /* Prior to Kepler, there's only a single runlist, so all
313 * engines can be accessed from any channel.
314 *
315 * We still want to use a separate channel though.
316 */
317 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
318 &drm->cechan);
319 }
320
321 if (ret)
322 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
323}
324
325static void
326nouveau_accel_gr_fini(struct nouveau_drm *drm)
ebb945a9 327{
fbd58ebd 328 nouveau_channel_idle(drm->channel);
0ad72863 329 nvif_object_fini(&drm->ntfy);
f027f491 330 nvkm_gpuobj_del(&drm->notify);
0ad72863 331 nvif_object_fini(&drm->nvsw);
fbd58ebd 332 nouveau_channel_del(&drm->channel);
f0eee9ae 333}
fbd58ebd 334
f0eee9ae
BS
335static void
336nouveau_accel_gr_init(struct nouveau_drm *drm)
337{
338 struct nvif_device *device = &drm->client.device;
339 u32 arg0, arg1;
340 int ret;
341
342 /* Allocate channel that has access to the graphics engine. */
343 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
344 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
345 arg1 = 1;
346 } else {
347 arg0 = NvDmaFB;
348 arg1 = NvDmaTT;
349 }
350
351 ret = nouveau_channel_new(drm, device, arg0, arg1, false,
352 &drm->channel);
353 if (ret) {
354 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
355 nouveau_accel_gr_fini(drm);
356 return;
357 }
358
359 /* A SW class is used on pre-NV50 HW to assist with handling the
360 * synchronisation of page flips, as well as to implement fences
361 * on TNT/TNT2 HW that lacks any kind of support in host.
362 */
363 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
364 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW,
365 nouveau_abi16_swclass(drm), NULL, 0,
366 &drm->nvsw);
367 if (ret == 0) {
368 ret = RING_SPACE(drm->channel, 2);
369 if (ret == 0) {
370 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
371 OUT_RING (drm->channel, drm->nvsw.handle);
372 }
373 }
374
375 if (ret) {
376 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
377 nouveau_accel_gr_fini(drm);
378 return;
379 }
380 }
381
382 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
383 * even if notification is never requested, so, allocate a ctxdma on
384 * any GPU where it's possible we'll end up using M2MF for BO moves.
385 */
386 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
387 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
388 &drm->notify);
389 if (ret) {
390 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
391 nouveau_accel_gr_fini(drm);
392 return;
393 }
394
395 ret = nvif_object_init(&drm->channel->user, NvNotify0,
396 NV_DMA_IN_MEMORY,
397 &(struct nv_dma_v0) {
398 .target = NV_DMA_V0_TARGET_VRAM,
399 .access = NV_DMA_V0_ACCESS_RDWR,
400 .start = drm->notify->addr,
401 .limit = drm->notify->addr + 31
402 }, sizeof(struct nv_dma_v0),
403 &drm->ntfy);
404 if (ret) {
405 nouveau_accel_gr_fini(drm);
406 return;
407 }
408 }
409}
fbd58ebd 410
f0eee9ae
BS
411static void
412nouveau_accel_fini(struct nouveau_drm *drm)
413{
414 nouveau_accel_ce_fini(drm);
415 nouveau_accel_gr_fini(drm);
ebb945a9
BS
416 if (drm->fence)
417 nouveau_fence(drm)->dtor(drm);
418}
419
420static void
421nouveau_accel_init(struct nouveau_drm *drm)
422{
1167c6bc 423 struct nvif_device *device = &drm->client.device;
41a63406 424 struct nvif_sclass *sclass;
41a63406 425 int ret, i, n;
ebb945a9 426
967e7bde 427 if (nouveau_noaccel)
ebb945a9
BS
428 return;
429
f0eee9ae 430 /* Initialise global support for channels, and synchronisation. */
eb47db4f
BS
431 ret = nouveau_channels_init(drm);
432 if (ret)
433 return;
434
967e7bde
BS
435 /*XXX: this is crap, but the fence/channel stuff is a little
436 * backwards in some places. this will be fixed.
437 */
41a63406 438 ret = n = nvif_object_sclass_get(&device->object, &sclass);
967e7bde
BS
439 if (ret < 0)
440 return;
441
41a63406
BS
442 for (ret = -ENOSYS, i = 0; i < n; i++) {
443 switch (sclass[i].oclass) {
bbf8906b 444 case NV03_CHANNEL_DMA:
967e7bde
BS
445 ret = nv04_fence_create(drm);
446 break;
bbf8906b 447 case NV10_CHANNEL_DMA:
967e7bde
BS
448 ret = nv10_fence_create(drm);
449 break;
bbf8906b
BS
450 case NV17_CHANNEL_DMA:
451 case NV40_CHANNEL_DMA:
967e7bde
BS
452 ret = nv17_fence_create(drm);
453 break;
bbf8906b 454 case NV50_CHANNEL_GPFIFO:
967e7bde
BS
455 ret = nv50_fence_create(drm);
456 break;
bbf8906b 457 case G82_CHANNEL_GPFIFO:
967e7bde
BS
458 ret = nv84_fence_create(drm);
459 break;
bbf8906b
BS
460 case FERMI_CHANNEL_GPFIFO:
461 case KEPLER_CHANNEL_GPFIFO_A:
63f8c9b7 462 case KEPLER_CHANNEL_GPFIFO_B:
a1020afe 463 case MAXWELL_CHANNEL_GPFIFO_A:
e8ff9794 464 case PASCAL_CHANNEL_GPFIFO_A:
37e1c45a 465 case VOLTA_CHANNEL_GPFIFO_A:
641d0b30 466 case TURING_CHANNEL_GPFIFO_A:
967e7bde
BS
467 ret = nvc0_fence_create(drm);
468 break;
469 default:
470 break;
471 }
472 }
473
41a63406 474 nvif_object_sclass_put(&sclass);
ebb945a9
BS
475 if (ret) {
476 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
477 nouveau_accel_fini(drm);
478 return;
479 }
480
f0eee9ae
BS
481 /* Volta requires access to a doorbell register for kickoff. */
482 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
483 ret = nvif_user_init(device);
00fc6f6f 484 if (ret)
ebb945a9 485 return;
ebb945a9
BS
486 }
487
f0eee9ae
BS
488 /* Allocate channels we need to support various functions. */
489 nouveau_accel_gr_init(drm);
490 nouveau_accel_ce_init(drm);
ebb945a9 491
f0eee9ae 492 /* Initialise accelerated TTM buffer moves. */
49981046 493 nouveau_bo_move_init(drm);
ebb945a9
BS
494}
495
5b8a43ae 496static int
cfea88a4 497nouveau_drm_device_init(struct drm_device *dev)
94580299 498{
94580299
BS
499 struct nouveau_drm *drm;
500 int ret;
501
20d8a88e
BS
502 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
503 return -ENOMEM;
504 dev->dev_private = drm;
505 drm->dev = dev;
506
cb7e88e7
BS
507 ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
508 if (ret)
c4cee69a 509 goto fail_alloc;
cb7e88e7 510
20d8a88e 511 ret = nouveau_cli_init(drm, "DRM", &drm->client);
94580299 512 if (ret)
c4cee69a 513 goto fail_master;
94580299 514
1167c6bc
BS
515 dev->irq_enabled = true;
516
989aa5b7 517 nvxx_client(&drm->client.base)->debug =
be83cd4e 518 nvkm_dbgopt(nouveau_debug, "DRM");
77145f1c 519
94580299 520 INIT_LIST_HEAD(&drm->clients);
ebb945a9 521 spin_lock_init(&drm->tile.lock);
94580299 522
77145f1c
BS
523 /* workaround an odd issue on nvc1 by disabling the device's
524 * nosnoop capability. hopefully won't cause issues until a
525 * better fix is found - assuming there is one...
526 */
1167c6bc
BS
527 if (drm->client.device.info.chipset == 0xc1)
528 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 529
77145f1c 530 nouveau_vga_init(drm);
cb75d97e 531
ebb945a9 532 ret = nouveau_ttm_init(drm);
94580299 533 if (ret)
77145f1c
BS
534 goto fail_ttm;
535
536 ret = nouveau_bios_init(dev);
537 if (ret)
538 goto fail_bios;
539
d7f9bb65
BS
540 nouveau_accel_init(drm);
541
77145f1c 542 ret = nouveau_display_create(dev);
ebb945a9 543 if (ret)
77145f1c
BS
544 goto fail_dispctor;
545
546 if (dev->mode_config.num_crtc) {
0f9976dd 547 ret = nouveau_display_init(dev, false, false);
77145f1c
BS
548 if (ret)
549 goto fail_dispinit;
550 }
551
b126a200 552 nouveau_debugfs_init(drm);
b9ed919f 553 nouveau_hwmon_init(dev);
eeaf06ac 554 nouveau_svm_init(drm);
5be73b69 555 nouveau_dmem_init(drm);
ebb945a9 556 nouveau_fbcon_init(dev);
8d021d71 557 nouveau_led_init(dev);
5addcf0a 558
8fa4338a 559 if (nouveau_pmops_runtime()) {
5addcf0a
DA
560 pm_runtime_use_autosuspend(dev->dev);
561 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
562 pm_runtime_set_active(dev->dev);
563 pm_runtime_allow(dev->dev);
564 pm_runtime_mark_last_busy(dev->dev);
565 pm_runtime_put(dev->dev);
566 }
7326ead9 567
94580299
BS
568 return 0;
569
77145f1c
BS
570fail_dispinit:
571 nouveau_display_destroy(dev);
572fail_dispctor:
d7f9bb65 573 nouveau_accel_fini(drm);
77145f1c
BS
574 nouveau_bios_takedown(dev);
575fail_bios:
ebb945a9 576 nouveau_ttm_fini(drm);
77145f1c 577fail_ttm:
77145f1c 578 nouveau_vga_fini(drm);
20d8a88e 579 nouveau_cli_fini(&drm->client);
c4cee69a 580fail_master:
cb7e88e7 581 nouveau_cli_fini(&drm->master);
c4cee69a 582fail_alloc:
20d8a88e 583 kfree(drm);
94580299
BS
584 return ret;
585}
586
11b3c20b 587static void
cfea88a4 588nouveau_drm_device_fini(struct drm_device *dev)
94580299 589{
77145f1c 590 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 591
8fa4338a 592 if (nouveau_pmops_runtime()) {
c1b16b45 593 pm_runtime_get_sync(dev->dev);
55c868a3 594 pm_runtime_forbid(dev->dev);
c1b16b45
LW
595 }
596
8d021d71 597 nouveau_led_fini(dev);
ebb945a9 598 nouveau_fbcon_fini(dev);
5be73b69 599 nouveau_dmem_fini(drm);
eeaf06ac 600 nouveau_svm_fini(drm);
b9ed919f 601 nouveau_hwmon_fini(dev);
b126a200 602 nouveau_debugfs_fini(drm);
77145f1c 603
9430738d 604 if (dev->mode_config.num_crtc)
2f7ca781 605 nouveau_display_fini(dev, false, false);
77145f1c
BS
606 nouveau_display_destroy(dev);
607
d7f9bb65 608 nouveau_accel_fini(drm);
77145f1c 609 nouveau_bios_takedown(dev);
94580299 610
ebb945a9 611 nouveau_ttm_fini(drm);
77145f1c 612 nouveau_vga_fini(drm);
cb75d97e 613
20d8a88e 614 nouveau_cli_fini(&drm->client);
cb7e88e7 615 nouveau_cli_fini(&drm->master);
20d8a88e 616 kfree(drm);
94580299
BS
617}
618
cfea88a4
LP
619static int nouveau_drm_probe(struct pci_dev *pdev,
620 const struct pci_device_id *pent)
621{
622 struct nvkm_device *device;
623 struct drm_device *drm_dev;
624 struct apertures_struct *aper;
625 bool boot = false;
626 int ret;
627
628 if (vga_switcheroo_client_probe_defer(pdev))
629 return -EPROBE_DEFER;
630
631 /* We need to check that the chipset is supported before booting
632 * fbdev off the hardware, as there's no way to put it back.
633 */
a2ac09a0
BS
634 ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
635 true, false, 0, &device);
cfea88a4
LP
636 if (ret)
637 return ret;
638
639 nvkm_device_del(&device);
640
641 /* Remove conflicting drivers (vesafb, efifb etc). */
642 aper = alloc_apertures(3);
643 if (!aper)
644 return -ENOMEM;
645
646 aper->ranges[0].base = pci_resource_start(pdev, 1);
647 aper->ranges[0].size = pci_resource_len(pdev, 1);
648 aper->count = 1;
649
650 if (pci_resource_len(pdev, 2)) {
651 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
652 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
653 aper->count++;
654 }
655
656 if (pci_resource_len(pdev, 3)) {
657 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
658 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
659 aper->count++;
660 }
661
662#ifdef CONFIG_X86
663 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
664#endif
665 if (nouveau_modeset != 2)
666 drm_fb_helper_remove_conflicting_framebuffers(aper, "nouveaufb", boot);
667 kfree(aper);
668
669 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
670 true, true, ~0ULL, &device);
671 if (ret)
672 return ret;
673
674 pci_set_master(pdev);
675
676 if (nouveau_atomic)
677 driver_pci.driver_features |= DRIVER_ATOMIC;
678
679 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
680 if (IS_ERR(drm_dev)) {
681 ret = PTR_ERR(drm_dev);
682 goto fail_nvkm;
683 }
684
685 ret = pci_enable_device(pdev);
686 if (ret)
687 goto fail_drm;
688
689 drm_dev->pdev = pdev;
690 pci_set_drvdata(pdev, drm_dev);
691
692 ret = nouveau_drm_device_init(drm_dev);
693 if (ret)
694 goto fail_pci;
695
696 ret = drm_dev_register(drm_dev, pent->driver_data);
697 if (ret)
698 goto fail_drm_dev_init;
699
700 return 0;
701
702fail_drm_dev_init:
703 nouveau_drm_device_fini(drm_dev);
704fail_pci:
705 pci_disable_device(pdev);
706fail_drm:
707 drm_dev_put(drm_dev);
708fail_nvkm:
709 nvkm_device_del(&device);
710 return ret;
711}
712
8ba9ff11
AC
713void
714nouveau_drm_device_remove(struct drm_device *dev)
94580299 715{
cfea88a4 716 struct pci_dev *pdev = dev->pdev;
77145f1c 717 struct nouveau_drm *drm = nouveau_drm(dev);
be83cd4e 718 struct nvkm_client *client;
76ecea5b 719 struct nvkm_device *device;
77145f1c 720
cfea88a4
LP
721 drm_dev_unregister(dev);
722
7d3428cd 723 dev->irq_enabled = false;
989aa5b7 724 client = nvxx_client(&drm->client.base);
4e7e62d6 725 device = nvkm_device_find(client->device);
77145f1c 726
cfea88a4
LP
727 nouveau_drm_device_fini(dev);
728 pci_disable_device(pdev);
729 drm_dev_put(dev);
e781dc8f 730 nvkm_device_del(&device);
94580299 731}
8ba9ff11
AC
732
733static void
734nouveau_drm_remove(struct pci_dev *pdev)
735{
736 struct drm_device *dev = pci_get_drvdata(pdev);
737
738 nouveau_drm_device_remove(dev);
739}
94580299 740
cd897837 741static int
05c63c2f 742nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 743{
77145f1c 744 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
745 int ret;
746
eeaf06ac 747 nouveau_svm_suspend(drm);
5be73b69 748 nouveau_dmem_suspend(drm);
8d021d71
MP
749 nouveau_led_suspend(dev);
750
6fbb702e 751 if (dev->mode_config.num_crtc) {
2d38a535 752 NV_DEBUG(drm, "suspending console...\n");
6fbb702e 753 nouveau_fbcon_set_suspend(dev, 1);
2d38a535 754 NV_DEBUG(drm, "suspending display...\n");
6fbb702e 755 ret = nouveau_display_suspend(dev, runtime);
9430738d
BS
756 if (ret)
757 return ret;
758 }
94580299 759
2d38a535 760 NV_DEBUG(drm, "evicting buffers...\n");
ebb945a9
BS
761 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
762
2d38a535 763 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
764 if (drm->cechan) {
765 ret = nouveau_channel_idle(drm->cechan);
766 if (ret)
f3980dc5 767 goto fail_display;
81dff21b
BS
768 }
769
770 if (drm->channel) {
771 ret = nouveau_channel_idle(drm->channel);
772 if (ret)
f3980dc5 773 goto fail_display;
81dff21b
BS
774 }
775
2d38a535 776 NV_DEBUG(drm, "suspending fence...\n");
ebb945a9 777 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
778 if (!nouveau_fence(drm)->suspend(drm)) {
779 ret = -ENOMEM;
780 goto fail_display;
781 }
ebb945a9
BS
782 }
783
2d38a535 784 NV_DEBUG(drm, "suspending object tree...\n");
cb7e88e7 785 ret = nvif_client_suspend(&drm->master.base);
94580299
BS
786 if (ret)
787 goto fail_client;
788
94580299
BS
789 return 0;
790
791fail_client:
f3980dc5
IM
792 if (drm->fence && nouveau_fence(drm)->resume)
793 nouveau_fence(drm)->resume(drm);
794
795fail_display:
9430738d 796 if (dev->mode_config.num_crtc) {
2d38a535 797 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 798 nouveau_display_resume(dev, runtime);
9430738d 799 }
94580299
BS
800 return ret;
801}
802
cd897837 803static int
6fbb702e 804nouveau_do_resume(struct drm_device *dev, bool runtime)
2d8b9ccb 805{
30df16b9 806 int ret = 0;
2d8b9ccb 807 struct nouveau_drm *drm = nouveau_drm(dev);
2d8b9ccb 808
2d38a535 809 NV_DEBUG(drm, "resuming object tree...\n");
30df16b9
TK
810 ret = nvif_client_resume(&drm->master.base);
811 if (ret) {
812 NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
813 return ret;
814 }
94580299 815
2d38a535 816 NV_DEBUG(drm, "resuming fence...\n");
81dff21b
BS
817 if (drm->fence && nouveau_fence(drm)->resume)
818 nouveau_fence(drm)->resume(drm);
819
77145f1c 820 nouveau_run_vbios_init(dev);
77145f1c 821
9430738d 822 if (dev->mode_config.num_crtc) {
2d38a535 823 NV_DEBUG(drm, "resuming display...\n");
6fbb702e 824 nouveau_display_resume(dev, runtime);
2d38a535 825 NV_DEBUG(drm, "resuming console...\n");
6fbb702e 826 nouveau_fbcon_set_suspend(dev, 0);
9430738d 827 }
5addcf0a 828
8d021d71 829 nouveau_led_resume(dev);
5be73b69 830 nouveau_dmem_resume(drm);
eeaf06ac 831 nouveau_svm_resume(drm);
77145f1c 832 return 0;
94580299
BS
833}
834
7bb6d442
BS
835int
836nouveau_pmops_suspend(struct device *dev)
837{
838 struct pci_dev *pdev = to_pci_dev(dev);
839 struct drm_device *drm_dev = pci_get_drvdata(pdev);
840 int ret;
841
842 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
843 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
844 return 0;
845
846 ret = nouveau_do_suspend(drm_dev, false);
847 if (ret)
848 return ret;
849
850 pci_save_state(pdev);
851 pci_disable_device(pdev);
7bb6d442 852 pci_set_power_state(pdev, PCI_D3hot);
c5fd936e 853 udelay(200);
7bb6d442
BS
854 return 0;
855}
856
857int
858nouveau_pmops_resume(struct device *dev)
2d8b9ccb
DA
859{
860 struct pci_dev *pdev = to_pci_dev(dev);
861 struct drm_device *drm_dev = pci_get_drvdata(pdev);
862 int ret;
863
5addcf0a
DA
864 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
865 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
866 return 0;
867
868 pci_set_power_state(pdev, PCI_D0);
869 pci_restore_state(pdev);
870 ret = pci_enable_device(pdev);
871 if (ret)
872 return ret;
873 pci_set_master(pdev);
874
0b2fe659
HG
875 ret = nouveau_do_resume(drm_dev, false);
876
877 /* Monitors may have been connected / disconnected during suspend */
878 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
879
880 return ret;
2d8b9ccb
DA
881}
882
7bb6d442
BS
883static int
884nouveau_pmops_freeze(struct device *dev)
2d8b9ccb
DA
885{
886 struct pci_dev *pdev = to_pci_dev(dev);
887 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 888 return nouveau_do_suspend(drm_dev, false);
2d8b9ccb
DA
889}
890
7bb6d442
BS
891static int
892nouveau_pmops_thaw(struct device *dev)
2d8b9ccb
DA
893{
894 struct pci_dev *pdev = to_pci_dev(dev);
895 struct drm_device *drm_dev = pci_get_drvdata(pdev);
6fbb702e 896 return nouveau_do_resume(drm_dev, false);
2d8b9ccb
DA
897}
898
321f5c5f 899bool
5499473c 900nouveau_pmops_runtime(void)
321f5c5f
BS
901{
902 if (nouveau_runtime_pm == -1)
903 return nouveau_is_optimus() || nouveau_is_v1_dsm();
904 return nouveau_runtime_pm == 1;
905}
906
7bb6d442
BS
907static int
908nouveau_pmops_runtime_suspend(struct device *dev)
909{
910 struct pci_dev *pdev = to_pci_dev(dev);
911 struct drm_device *drm_dev = pci_get_drvdata(pdev);
912 int ret;
913
321f5c5f 914 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
915 pm_runtime_forbid(dev);
916 return -EBUSY;
917 }
918
7bb6d442
BS
919 nouveau_switcheroo_optimus_dsm();
920 ret = nouveau_do_suspend(drm_dev, true);
921 pci_save_state(pdev);
922 pci_disable_device(pdev);
8c863944 923 pci_ignore_hotplug(pdev);
7bb6d442
BS
924 pci_set_power_state(pdev, PCI_D3cold);
925 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
926 return ret;
927}
928
929static int
930nouveau_pmops_runtime_resume(struct device *dev)
931{
932 struct pci_dev *pdev = to_pci_dev(dev);
933 struct drm_device *drm_dev = pci_get_drvdata(pdev);
30df16b9 934 struct nouveau_drm *drm = nouveau_drm(drm_dev);
1167c6bc 935 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
7bb6d442
BS
936 int ret;
937
321f5c5f
BS
938 if (!nouveau_pmops_runtime()) {
939 pm_runtime_forbid(dev);
940 return -EBUSY;
941 }
7bb6d442
BS
942
943 pci_set_power_state(pdev, PCI_D0);
944 pci_restore_state(pdev);
945 ret = pci_enable_device(pdev);
946 if (ret)
947 return ret;
948 pci_set_master(pdev);
949
950 ret = nouveau_do_resume(drm_dev, true);
30df16b9
TK
951 if (ret) {
952 NV_ERROR(drm, "resume failed with: %d\n", ret);
953 return ret;
954 }
cae9ff03 955
7bb6d442 956 /* do magic */
a01ca78c 957 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
7bb6d442 958 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
0b2fe659
HG
959
960 /* Monitors may have been connected / disconnected during suspend */
961 schedule_work(&nouveau_drm(drm_dev)->hpd_work);
962
7bb6d442
BS
963 return ret;
964}
965
966static int
967nouveau_pmops_runtime_idle(struct device *dev)
968{
321f5c5f 969 if (!nouveau_pmops_runtime()) {
7bb6d442
BS
970 pm_runtime_forbid(dev);
971 return -EBUSY;
972 }
973
7bb6d442
BS
974 pm_runtime_mark_last_busy(dev);
975 pm_runtime_autosuspend(dev);
976 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
977 return 1;
978}
2d8b9ccb 979
5b8a43ae 980static int
ebb945a9
BS
981nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
982{
ebb945a9
BS
983 struct nouveau_drm *drm = nouveau_drm(dev);
984 struct nouveau_cli *cli;
a2896ced 985 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
986 int ret;
987
5addcf0a
DA
988 /* need to bring up power immediately if opening device */
989 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 990 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
991 return ret;
992
a2896ced
MS
993 get_task_comm(tmpname, current);
994 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 995
922a8c82
LP
996 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
997 ret = -ENOMEM;
998 goto done;
999 }
420b9469 1000
20d8a88e 1001 ret = nouveau_cli_init(drm, name, cli);
ebb945a9 1002 if (ret)
20d8a88e 1003 goto done;
ebb945a9 1004
0ad72863
BS
1005 cli->base.super = false;
1006
ebb945a9
BS
1007 fpriv->driver_priv = cli;
1008
1009 mutex_lock(&drm->client.mutex);
1010 list_add(&cli->head, &drm->clients);
1011 mutex_unlock(&drm->client.mutex);
5addcf0a 1012
20d8a88e
BS
1013done:
1014 if (ret && cli) {
1015 nouveau_cli_fini(cli);
1016 kfree(cli);
1017 }
1018
5addcf0a
DA
1019 pm_runtime_mark_last_busy(dev->dev);
1020 pm_runtime_put_autosuspend(dev->dev);
5addcf0a 1021 return ret;
ebb945a9
BS
1022}
1023
5b8a43ae 1024static void
f0e73ff3 1025nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
ebb945a9
BS
1026{
1027 struct nouveau_cli *cli = nouveau_cli(fpriv);
1028 struct nouveau_drm *drm = nouveau_drm(dev);
1029
5addcf0a
DA
1030 pm_runtime_get_sync(dev->dev);
1031
ac8c7930 1032 mutex_lock(&cli->mutex);
ebb945a9
BS
1033 if (cli->abi16)
1034 nouveau_abi16_fini(cli->abi16);
ac8c7930 1035 mutex_unlock(&cli->mutex);
ebb945a9
BS
1036
1037 mutex_lock(&drm->client.mutex);
1038 list_del(&cli->head);
1039 mutex_unlock(&drm->client.mutex);
5addcf0a 1040
20d8a88e
BS
1041 nouveau_cli_fini(cli);
1042 kfree(cli);
5addcf0a
DA
1043 pm_runtime_mark_last_busy(dev->dev);
1044 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
1045}
1046
baa70943 1047static const struct drm_ioctl_desc
77145f1c 1048nouveau_ioctls[] = {
f8c47144
DV
1049 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1050 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1051 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1052 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
1053 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1054 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
1055 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
eeaf06ac 1056 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_AUTH|DRM_RENDER_ALLOW),
f180bf12 1057 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_AUTH|DRM_RENDER_ALLOW),
f8c47144
DV
1058 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
1059 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
1060 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1061 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1062 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
1063};
1064
27111a23
BS
1065long
1066nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5addcf0a 1067{
27111a23
BS
1068 struct drm_file *filp = file->private_data;
1069 struct drm_device *dev = filp->minor->dev;
5addcf0a 1070 long ret;
5addcf0a
DA
1071
1072 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 1073 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
1074 return ret;
1075
27111a23
BS
1076 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
1077 case DRM_NOUVEAU_NVIF:
1078 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
1079 break;
1080 default:
1081 ret = drm_ioctl(file, cmd, arg);
1082 break;
1083 }
5addcf0a
DA
1084
1085 pm_runtime_mark_last_busy(dev->dev);
1086 pm_runtime_put_autosuspend(dev->dev);
1087 return ret;
1088}
27111a23 1089
77145f1c
BS
1090static const struct file_operations
1091nouveau_driver_fops = {
1092 .owner = THIS_MODULE,
1093 .open = drm_open,
1094 .release = drm_release,
5addcf0a 1095 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
1096 .mmap = nouveau_ttm_mmap,
1097 .poll = drm_poll,
77145f1c
BS
1098 .read = drm_read,
1099#if defined(CONFIG_COMPAT)
1100 .compat_ioctl = nouveau_compat_ioctl,
1101#endif
1102 .llseek = noop_llseek,
1103};
1104
1105static struct drm_driver
915b4d11 1106driver_stub = {
77145f1c 1107 .driver_features =
b30a43ac
DA
1108 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER
1109#if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
1110 | DRIVER_KMS_LEGACY_CONTEXT
1111#endif
1112 ,
77145f1c 1113
77145f1c 1114 .open = nouveau_drm_open,
77145f1c
BS
1115 .postclose = nouveau_drm_postclose,
1116 .lastclose = nouveau_vga_lastclose,
1117
33b903e8 1118#if defined(CONFIG_DEBUG_FS)
56c101af 1119 .debugfs_init = nouveau_drm_debugfs_init,
33b903e8
MS
1120#endif
1121
51cb4b39
BS
1122 .enable_vblank = nouveau_display_vblank_enable,
1123 .disable_vblank = nouveau_display_vblank_disable,
d83ef853 1124 .get_scanout_position = nouveau_display_scanoutpos,
1bf6ad62 1125 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
77145f1c
BS
1126
1127 .ioctls = nouveau_ioctls,
baa70943 1128 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
1129 .fops = &nouveau_driver_fops,
1130
1131 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1132 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
1133 .gem_prime_export = drm_gem_prime_export,
1134 .gem_prime_import = drm_gem_prime_import,
1135 .gem_prime_pin = nouveau_gem_prime_pin,
3aac4502 1136 .gem_prime_res_obj = nouveau_gem_prime_res_obj,
1af7c7dd 1137 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
1138 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
1139 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
1140 .gem_prime_vmap = nouveau_gem_prime_vmap,
1141 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 1142
a51e6ac4 1143 .gem_free_object_unlocked = nouveau_gem_object_del,
77145f1c
BS
1144 .gem_open_object = nouveau_gem_object_open,
1145 .gem_close_object = nouveau_gem_object_close,
1146
1147 .dumb_create = nouveau_display_dumb_create,
1148 .dumb_map_offset = nouveau_display_dumb_map_offset,
77145f1c
BS
1149
1150 .name = DRIVER_NAME,
1151 .desc = DRIVER_DESC,
1152#ifdef GIT_REVISION
1153 .date = GIT_REVISION,
1154#else
1155 .date = DRIVER_DATE,
1156#endif
1157 .major = DRIVER_MAJOR,
1158 .minor = DRIVER_MINOR,
1159 .patchlevel = DRIVER_PATCHLEVEL,
1160};
1161
94580299
BS
1162static struct pci_device_id
1163nouveau_drm_pci_table[] = {
1164 {
1165 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
1166 .class = PCI_BASE_CLASS_DISPLAY << 16,
1167 .class_mask = 0xff << 16,
1168 },
1169 {
1170 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
1171 .class = PCI_BASE_CLASS_DISPLAY << 16,
1172 .class_mask = 0xff << 16,
1173 },
1174 {}
1175};
1176
703fa264
PM
1177static void nouveau_display_options(void)
1178{
1179 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
1180
1181 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
1182 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
1183 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
1184 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
1185 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
1186 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
1187 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
1188 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
1189 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
1190 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
f3a8b664 1191 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
703fa264
PM
1192}
1193
2d8b9ccb
DA
1194static const struct dev_pm_ops nouveau_pm_ops = {
1195 .suspend = nouveau_pmops_suspend,
1196 .resume = nouveau_pmops_resume,
1197 .freeze = nouveau_pmops_freeze,
1198 .thaw = nouveau_pmops_thaw,
1199 .poweroff = nouveau_pmops_freeze,
1200 .restore = nouveau_pmops_resume,
5addcf0a
DA
1201 .runtime_suspend = nouveau_pmops_runtime_suspend,
1202 .runtime_resume = nouveau_pmops_runtime_resume,
1203 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1204};
1205
94580299
BS
1206static struct pci_driver
1207nouveau_drm_pci_driver = {
1208 .name = "nouveau",
1209 .id_table = nouveau_drm_pci_table,
1210 .probe = nouveau_drm_probe,
1211 .remove = nouveau_drm_remove,
2d8b9ccb 1212 .driver.pm = &nouveau_pm_ops,
94580299
BS
1213};
1214
8ba9ff11 1215struct drm_device *
e396ecd1
AC
1216nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
1217 struct platform_device *pdev,
47b2505e 1218 struct nvkm_device **pdevice)
420b9469 1219{
8ba9ff11
AC
1220 struct drm_device *drm;
1221 int err;
420b9469 1222
e396ecd1 1223 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
7974dd1b 1224 true, true, ~0ULL, pdevice);
8ba9ff11 1225 if (err)
e781dc8f 1226 goto err_free;
8ba9ff11 1227
915b4d11 1228 drm = drm_dev_alloc(&driver_platform, &pdev->dev);
0f288605
TG
1229 if (IS_ERR(drm)) {
1230 err = PTR_ERR(drm);
8ba9ff11 1231 goto err_free;
420b9469
AC
1232 }
1233
4ac0a807
TR
1234 err = nouveau_drm_device_init(drm);
1235 if (err)
1236 goto err_put;
1237
8ba9ff11
AC
1238 platform_set_drvdata(pdev, drm);
1239
1240 return drm;
1241
4ac0a807
TR
1242err_put:
1243 drm_dev_put(drm);
8ba9ff11 1244err_free:
e781dc8f 1245 nvkm_device_del(pdevice);
8ba9ff11
AC
1246
1247 return ERR_PTR(err);
420b9469
AC
1248}
1249
94580299
BS
1250static int __init
1251nouveau_drm_init(void)
1252{
915b4d11 1253 driver_pci = driver_stub;
915b4d11 1254 driver_platform = driver_stub;
915b4d11 1255
703fa264
PM
1256 nouveau_display_options();
1257
77145f1c 1258 if (nouveau_modeset == -1) {
77145f1c
BS
1259 if (vgacon_text_force())
1260 nouveau_modeset = 0;
77145f1c
BS
1261 }
1262
1263 if (!nouveau_modeset)
1264 return 0;
1265
055a65d5
AC
1266#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1267 platform_driver_register(&nouveau_platform_driver);
1268#endif
1269
77145f1c 1270 nouveau_register_dsm_handler();
db1a0ae2 1271 nouveau_backlight_ctor();
10631d72
DV
1272
1273#ifdef CONFIG_PCI
1274 return pci_register_driver(&nouveau_drm_pci_driver);
1275#else
1276 return 0;
1277#endif
94580299
BS
1278}
1279
1280static void __exit
1281nouveau_drm_exit(void)
1282{
77145f1c
BS
1283 if (!nouveau_modeset)
1284 return;
1285
10631d72
DV
1286#ifdef CONFIG_PCI
1287 pci_unregister_driver(&nouveau_drm_pci_driver);
1288#endif
db1a0ae2 1289 nouveau_backlight_dtor();
77145f1c 1290 nouveau_unregister_dsm_handler();
055a65d5
AC
1291
1292#ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
1293 platform_driver_unregister(&nouveau_platform_driver);
1294#endif
94580299
BS
1295}
1296
1297module_init(nouveau_drm_init);
1298module_exit(nouveau_drm_exit);
1299
1300MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1301MODULE_AUTHOR(DRIVER_AUTHOR);
1302MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1303MODULE_LICENSE("GPL and additional rights");