[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>
#include <linux/module.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_pm.h"
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
int nouveau_agpmode = -1;
module_param_named(agpmode, nouveau_agpmode, int, 0400);

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
int nouveau_modeset = -1;
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = -1;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(force_post, "Force POST");
int nouveau_force_post = 0;
module_param_named(force_post, nouveau_force_post, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);

MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);

MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);

MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n");
int nouveau_ctxfw;
module_param_named(ctxfw, nouveau_ctxfw, int, 0400);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i, e;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	drm_kms_helper_poll_disable(dev);

	NV_INFO(dev, "Disabling fbcon acceleration...\n");
	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < pfifo->channels; i++) {
		chan = dev_priv->channels.ptr[i];

		if (chan && chan->pushbuf_bo)
			nouveau_channel_idle(chan);
	}

	pfifo->reassign(dev, false);
	pfifo->disable(dev);
	pfifo->unload_context(dev);

	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
		if (!dev_priv->eng[e])
			continue;

		ret = dev_priv->eng[e]->fini(dev, e, true);
		if (ret) {
			NV_ERROR(dev, "... engine %d failed: %d\n", i, ret);
			goto out_abort;
		}
	}

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		pinstmem->resume(dev);
		goto out_abort;
	}

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	console_lock();
	nouveau_fbcon_set_suspend(dev, 1);
	console_unlock();
	nouveau_fbcon_restore_accel(dev);
	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
		if (dev_priv->eng[e])
			dev_priv->eng[e]->init(dev, e);
	}
	pfifo->enable(dev);
	pfifo->reassign(dev, true);
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
		nouveau_mem_reset_agp(dev);

	/* Make the CRTCs accessible */
	engine->display.early_init(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
		ret = nouveau_mem_init_agp(dev);
		if (ret) {
			NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
		if (dev_priv->eng[i])
			dev_priv->eng[i]->init(dev, i);
	}
	engine->fifo.init(dev);

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
			chan = dev_priv->channels.ptr[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	nouveau_pm_resume(dev);

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	engine->display.init(dev);

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	console_lock();
	nouveau_fbcon_set_suspend(dev, 0);
	console_unlock();

	nouveau_fbcon_zfill_all(dev);

	drm_helper_resume_force_mode(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
		u32 offset = nv_crtc->cursor.nvbo->bo.offset;

		nv_crtc->cursor.set_offset(nv_crtc, offset);
		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
						 nv_crtc->cursor_saved_y);
	}

	nouveau_fbcon_restore_accel(dev);
	drm_kms_helper_poll_enable(dev);
	return 0;
}

static const struct file_operations nouveau_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = nouveau_ttm_mmap,
	.poll = drm_poll,
	.fasync = drm_fasync,
	.read = drm_read,
#if defined(CONFIG_COMPAT)
	.compat_ioctl = nouveau_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.open = nouveau_open,
	.preclose = nouveau_preclose,
	.postclose = nouveau_postclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.get_vblank_counter = drm_vblank_count,
	.enable_vblank = nouveau_vblank_enable,
	.disable_vblank = nouveau_vblank_disable,
	.reclaim_buffers = drm_core_reclaim_buffers,
	.ioctls = nouveau_ioctls,
	.fops = &nouveau_driver_fops,
	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,
	.gem_open_object = nouveau_gem_object_open,
	.gem_close_object = nouveau_gem_object_close,

	.dumb_create = nouveau_display_dumb_create,
	.dumb_map_offset = nouveau_display_dumb_map_offset,
	.dumb_destroy = nouveau_display_dumb_destroy,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static struct pci_driver nouveau_pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = nouveau_max_ioctl;

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_pci_init(&driver, &nouveau_pci_driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_pci_exit(&driver, &nouveau_pci_driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
e0cd3608	26	#include <linux/module.h>
6ee73861 BS	27
	28	#include "drmP.h"
	29	#include "drm.h"
	30	#include "drm_crtc_helper.h"
	31	#include "nouveau_drv.h"
	32	#include "nouveau_hw.h"
	33	#include "nouveau_fb.h"
	34	#include "nouveau_fbcon.h"
64f1c11a	35	#include "nouveau_pm.h"
6ee73861 BS	36	#include "nv50_display.h"
	37
	38	#include "drm_pciids.h"
	39
de5899bd FJ	40	MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
	41	int nouveau_agpmode = -1;
	42	module_param_named(agpmode, nouveau_agpmode, int, 0400);
6ee73861 BS	43
6ee73861 BS	44	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
03bc9675	45	int nouveau_modeset = -1;
6ee73861 BS	46	module_param_named(modeset, nouveau_modeset, int, 0400);
	47
	48	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	49	char *nouveau_vbios;
	50	module_param_named(vbios, nouveau_vbios, charp, 0400);
	51
	52	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	53	int nouveau_vram_pushbuf;
	54	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	55
	56	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	57	int nouveau_vram_notify = 0;
6ee73861 BS	58	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
	59
	60	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	61	int nouveau_duallink = 1;
	62	module_param_named(duallink, nouveau_duallink, int, 0400);
	63
	64	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	65	int nouveau_uscript_lvds = -1;
	66	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	67
	68	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	69	int nouveau_uscript_tmds = -1;
	70	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	71
a1470890 BS	72	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	73	int nouveau_ignorelid = 0;
	74	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	75
81e2d422	76	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
aba99a84	77	int nouveau_noaccel = -1;
a32ed69d MK	78	module_param_named(noaccel, nouveau_noaccel, int, 0400);
a32ed69d MK	79
81e2d422	80	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	81	int nouveau_nofbaccel = 0;
	82	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	83
0cba1b76 MK	84	MODULE_PARM_DESC(force_post, "Force POST");
	85	int nouveau_force_post = 0;
	86	module_param_named(force_post, nouveau_force_post, int, 0400);
	87
da647d5b BS	88	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	89	int nouveau_override_conntype = 0;
	90	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	91
f4053509 BS	92	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
	93	int nouveau_tv_disable = 0;
	94	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	95
6ee73861 BS	96	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	97	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	98	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	99	"\t\tDefault: PAL\n"
	100	"\t\tNOTE Ignored for cards with external TV encoders.");
	101	char *nouveau_tv_norm;
	102	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	103
	104	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	105	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	106	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
	107	"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
	108	int nouveau_reg_debug;
	109	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	110
6f876986 BS	111	MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
	112	char *nouveau_perflvl;
	113	module_param_named(perflvl, nouveau_perflvl, charp, 0400);
	114
	115	MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
	116	int nouveau_perflvl_wr;
	117	module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
	118
35fa2f2a BS	119	MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
	120	int nouveau_msi;
	121	module_param_named(msi, nouveau_msi, int, 0400);
	122
0411de85 BS	123	MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n");
	124	int nouveau_ctxfw;
	125	module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
	126
6ee73861 BS	127	int nouveau_fbpercrtc;
	128	#if 0
	129	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	130	#endif
	131
	132	static struct pci_device_id pciidlist[] = {
	133	{
	134	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	135	.class = PCI_BASE_CLASS_DISPLAY << 16,
	136	.class_mask = 0xff << 16,
	137	},
	138	{
	139	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	140	.class = PCI_BASE_CLASS_DISPLAY << 16,
	141	.class_mask = 0xff << 16,
	142	},
	143	{}
	144	};
	145
	146	MODULE_DEVICE_TABLE(pci, pciidlist);
	147
	148	static struct drm_driver driver;
	149
	150	static int __devinit
	151	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	152	{
dcdb1674	153	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	154	}
	155
	156	static void
	157	nouveau_pci_remove(struct pci_dev *pdev)
	158	{
	159	struct drm_device *dev = pci_get_drvdata(pdev);
	160
	161	drm_put_dev(dev);
	162	}
	163
6a9ee8af	164	int
6ee73861 BS	165	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	166	{
	167	struct drm_device *dev = pci_get_drvdata(pdev);
	168	struct drm_nouveau_private *dev_priv = dev->dev_private;
	169	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
6ee73861 BS	170	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	171	struct nouveau_channel *chan;
	172	struct drm_crtc *crtc;
92abe749	173	int ret, i, e;
6ee73861	174
6ee73861 BS	175	if (pm_state.event == PM_EVENT_PRETHAW)
	176	return 0;
	177
5bcf719b DA	178	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	179	return 0;
	180
4bfb94a1 ML	181	drm_kms_helper_poll_disable(dev);
4bfb94a1 ML	182
81441570	183	NV_INFO(dev, "Disabling fbcon acceleration...\n");
38651674	184	nouveau_fbcon_save_disable_accel(dev);
6ee73861	185
81441570	186	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	187	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	188	struct nouveau_framebuffer *nouveau_fb;
	189
	190	nouveau_fb = nouveau_framebuffer(crtc->fb);
	191	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	192	continue;
	193
	194	nouveau_bo_unpin(nouveau_fb->nvbo);
	195	}
	196
b334f2b3 MM	197	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	198	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	199
	200	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	201	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	202	}
	203
6ee73861 BS	204	NV_INFO(dev, "Evicting buffers...\n");
	205	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	206
	207	NV_INFO(dev, "Idling channels...\n");
	208	for (i = 0; i < pfifo->channels; i++) {
cff5c133	209	chan = dev_priv->channels.ptr[i];
6ee73861	210
6dccd311 FJ	211	if (chan && chan->pushbuf_bo)
6dccd311 FJ	212	nouveau_channel_idle(chan);
6ee73861 BS	213	}
6ee73861 BS	214
6ee73861 BS	215	pfifo->reassign(dev, false);
	216	pfifo->disable(dev);
	217	pfifo->unload_context(dev);
92abe749 BS	218
92abe749 BS	219	for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
6c320fef BS	220	if (!dev_priv->eng[e])
	221	continue;
	222
	223	ret = dev_priv->eng[e]->fini(dev, e, true);
	224	if (ret) {
	225	NV_ERROR(dev, "... engine %d failed: %d\n", i, ret);
	226	goto out_abort;
92abe749 BS	227	}
92abe749 BS	228	}
6ee73861	229
dc1e5c0d	230	ret = pinstmem->suspend(dev);
6ee73861 BS	231	if (ret) {
	232	NV_ERROR(dev, "... failed: %d\n", ret);
	233	goto out_abort;
	234	}
	235
dc1e5c0d BS	236	NV_INFO(dev, "Suspending GPU objects...\n");
dc1e5c0d BS	237	ret = nouveau_gpuobj_suspend(dev);
6ee73861 BS	238	if (ret) {
6ee73861 BS	239	NV_ERROR(dev, "... failed: %d\n", ret);
dc1e5c0d	240	pinstmem->resume(dev);
6ee73861 BS	241	goto out_abort;
	242	}
	243
	244	NV_INFO(dev, "And we're gone!\n");
	245	pci_save_state(pdev);
	246	if (pm_state.event == PM_EVENT_SUSPEND) {
	247	pci_disable_device(pdev);
	248	pci_set_power_state(pdev, PCI_D3hot);
	249	}
	250
ac751efa	251	console_lock();
38651674	252	nouveau_fbcon_set_suspend(dev, 1);
ac751efa	253	console_unlock();
38651674	254	nouveau_fbcon_restore_accel(dev);
6ee73861 BS	255	return 0;
	256
	257	out_abort:
	258	NV_INFO(dev, "Re-enabling acceleration..\n");
92abe749 BS	259	for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
	260	if (dev_priv->eng[e])
	261	dev_priv->eng[e]->init(dev, e);
	262	}
6ee73861 BS	263	pfifo->enable(dev);
6ee73861 BS	264	pfifo->reassign(dev, true);
6ee73861 BS	265	return ret;
	266	}
	267
6a9ee8af	268	int
6ee73861 BS	269	nouveau_pci_resume(struct pci_dev *pdev)
	270	{
	271	struct drm_device *dev = pci_get_drvdata(pdev);
	272	struct drm_nouveau_private *dev_priv = dev->dev_private;
	273	struct nouveau_engine *engine = &dev_priv->engine;
	274	struct drm_crtc *crtc;
6ee73861 BS	275	int ret, i;
6ee73861 BS	276
5bcf719b DA	277	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	278	return 0;
	279
38651674	280	nouveau_fbcon_save_disable_accel(dev);
6ee73861 BS	281
	282	NV_INFO(dev, "We're back, enabling device...\n");
	283	pci_set_power_state(pdev, PCI_D0);
	284	pci_restore_state(pdev);
	285	if (pci_enable_device(pdev))
	286	return -1;
	287	pci_set_master(dev->pdev);
	288
e04d8e82 FJ	289	/* Make sure the AGP controller is in a consistent state */
	290	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	291	nouveau_mem_reset_agp(dev);
	292
c88c2e06 FJ	293	/* Make the CRTCs accessible */
	294	engine->display.early_init(dev);
	295
6ee73861 BS	296	NV_INFO(dev, "POSTing device...\n");
	297	ret = nouveau_run_vbios_init(dev);
	298	if (ret)
	299	return ret;
	300
	301	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
	302	ret = nouveau_mem_init_agp(dev);
	303	if (ret) {
	304	NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
	305	return ret;
	306	}
	307	}
	308
dc1e5c0d BS	309	NV_INFO(dev, "Restoring GPU objects...\n");
	310	nouveau_gpuobj_resume(dev);
	311
6ee73861 BS	312	NV_INFO(dev, "Reinitialising engines...\n");
	313	engine->instmem.resume(dev);
	314	engine->mc.init(dev);
	315	engine->timer.init(dev);
	316	engine->fb.init(dev);
6dfdd7a6 BS	317	for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
	318	if (dev_priv->eng[i])
	319	dev_priv->eng[i]->init(dev, i);
	320	}
6ee73861 BS	321	engine->fifo.init(dev);
6ee73861 BS	322
6ee73861 BS	323	nouveau_irq_postinstall(dev);
	324
	325	/* Re-write SKIPS, they'll have been lost over the suspend */
	326	if (nouveau_vram_pushbuf) {
	327	struct nouveau_channel *chan;
	328	int j;
	329
	330	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	331	chan = dev_priv->channels.ptr[i];
3c8868d3	332	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	333	continue;
	334
	335	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	336	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	337	}
	338	}
	339
71d91f65 ML	340	nouveau_pm_resume(dev);
71d91f65 ML	341
6ee73861 BS	342	NV_INFO(dev, "Restoring mode...\n");
	343	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	344	struct nouveau_framebuffer *nouveau_fb;
	345
	346	nouveau_fb = nouveau_framebuffer(crtc->fb);
	347	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	348	continue;
	349
	350	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	351	}
	352
b334f2b3 MM	353	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	354	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	355
	356	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	357	if (!ret)
	358	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	359	if (ret)
	360	NV_ERROR(dev, "Could not pin/map cursor.\n");
	361	}
	362
c88c2e06	363	engine->display.init(dev);
6ee73861 BS	364
	365	/* Force CLUT to get re-loaded during modeset */
	366	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	367	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	368
	369	nv_crtc->lut.depth = 0;
	370	}
	371
ac751efa	372	console_lock();
38651674	373	nouveau_fbcon_set_suspend(dev, 0);
ac751efa	374	console_unlock();
6ee73861	375
38651674	376	nouveau_fbcon_zfill_all(dev);
6ee73861 BS	377
6ee73861 BS	378	drm_helper_resume_force_mode(dev);
38651674	379
a4eaa0a0 ML	380	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	381	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	382	u32 offset = nv_crtc->cursor.nvbo->bo.offset;
	383
	384	nv_crtc->cursor.set_offset(nv_crtc, offset);
	385	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
	386	nv_crtc->cursor_saved_y);
	387	}
	388
38651674	389	nouveau_fbcon_restore_accel(dev);
4bfb94a1	390	drm_kms_helper_poll_enable(dev);
6ee73861 BS	391	return 0;
	392	}
	393
e08e96de AV	394	static const struct file_operations nouveau_driver_fops = {
	395	.owner = THIS_MODULE,
	396	.open = drm_open,
	397	.release = drm_release,
	398	.unlocked_ioctl = drm_ioctl,
	399	.mmap = nouveau_ttm_mmap,
	400	.poll = drm_poll,
	401	.fasync = drm_fasync,
	402	.read = drm_read,
	403	#if defined(CONFIG_COMPAT)
	404	.compat_ioctl = nouveau_compat_ioctl,
	405	#endif
	406	.llseek = noop_llseek,
	407	};
	408
6ee73861 BS	409	static struct drm_driver driver = {
	410	.driver_features =
	411	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f BS	412	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
cd0b072f BS	413	DRIVER_MODESET,
6ee73861 BS	414	.load = nouveau_load,
	415	.firstopen = nouveau_firstopen,
	416	.lastclose = nouveau_lastclose,
	417	.unload = nouveau_unload,
3f0a68d8	418	.open = nouveau_open,
6ee73861	419	.preclose = nouveau_preclose,
3f0a68d8	420	.postclose = nouveau_postclose,
6ee73861 BS	421	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	422	.debugfs_init = nouveau_debugfs_init,
	423	.debugfs_cleanup = nouveau_debugfs_takedown,
	424	#endif
	425	.irq_preinstall = nouveau_irq_preinstall,
	426	.irq_postinstall = nouveau_irq_postinstall,
	427	.irq_uninstall = nouveau_irq_uninstall,
	428	.irq_handler = nouveau_irq_handler,
042206c0 FJ	429	.get_vblank_counter = drm_vblank_count,
	430	.enable_vblank = nouveau_vblank_enable,
	431	.disable_vblank = nouveau_vblank_disable,
6ee73861	432	.reclaim_buffers = drm_core_reclaim_buffers,
6ee73861	433	.ioctls = nouveau_ioctls,
e08e96de	434	.fops = &nouveau_driver_fops,
6ee73861 BS	435	.gem_init_object = nouveau_gem_object_new,
6ee73861 BS	436	.gem_free_object = nouveau_gem_object_del,
639212d0 BS	437	.gem_open_object = nouveau_gem_object_open,
639212d0 BS	438	.gem_close_object = nouveau_gem_object_close,
6ee73861	439
33dbc27f BS	440	.dumb_create = nouveau_display_dumb_create,
	441	.dumb_map_offset = nouveau_display_dumb_map_offset,
	442	.dumb_destroy = nouveau_display_dumb_destroy,
	443
6ee73861 BS	444	.name = DRIVER_NAME,
	445	.desc = DRIVER_DESC,
	446	#ifdef GIT_REVISION
	447	.date = GIT_REVISION,
	448	#else
	449	.date = DRIVER_DATE,
	450	#endif
	451	.major = DRIVER_MAJOR,
	452	.minor = DRIVER_MINOR,
	453	.patchlevel = DRIVER_PATCHLEVEL,
	454	};
	455
8410ea3b DA	456	static struct pci_driver nouveau_pci_driver = {
	457	.name = DRIVER_NAME,
	458	.id_table = pciidlist,
	459	.probe = nouveau_pci_probe,
	460	.remove = nouveau_pci_remove,
	461	.suspend = nouveau_pci_suspend,
	462	.resume = nouveau_pci_resume
	463	};
	464
6ee73861 BS	465	static int __init nouveau_init(void)
	466	{
	467	driver.num_ioctls = nouveau_max_ioctl;
	468
	469	if (nouveau_modeset == -1) {
	470	#ifdef CONFIG_VGA_CONSOLE
	471	if (vgacon_text_force())
	472	nouveau_modeset = 0;
	473	else
	474	#endif
	475	nouveau_modeset = 1;
	476	}
	477
cd0b072f BS	478	if (!nouveau_modeset)
cd0b072f BS	479	return 0;
6ee73861	480
cd0b072f	481	nouveau_register_dsm_handler();
8410ea3b	482	return drm_pci_init(&driver, &nouveau_pci_driver);
6ee73861 BS	483	}
	484
	485	static void __exit nouveau_exit(void)
	486	{
cd0b072f BS	487	if (!nouveau_modeset)
	488	return;
	489
8410ea3b	490	drm_pci_exit(&driver, &nouveau_pci_driver);
6a9ee8af	491	nouveau_unregister_dsm_handler();
6ee73861 BS	492	}
	493
	494	module_init(nouveau_init);
	495	module_exit(nouveau_exit);
	496
	497	MODULE_AUTHOR(DRIVER_AUTHOR);
	498	MODULE_DESCRIPTION(DRIVER_DESC);
	499	MODULE_LICENSE("GPL and additional rights");