[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.c

/*
 * Copyright 2005 Stephane Marchesin.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/console.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_fb.h"
#include "nouveau_fbcon.h"
#include "nouveau_pm.h"
#include "nv50_display.h"

#include "drm_pciids.h"

MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
int nouveau_agpmode = -1;
module_param_named(agpmode, nouveau_agpmode, int, 0400);

MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
static int nouveau_modeset = -1; /* kms */
module_param_named(modeset, nouveau_modeset, int, 0400);

MODULE_PARM_DESC(vbios, "Override default VBIOS location");
char *nouveau_vbios;
module_param_named(vbios, nouveau_vbios, charp, 0400);

MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
int nouveau_vram_notify = 0;
module_param_named(vram_notify, nouveau_vram_notify, int, 0400);

MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
int nouveau_duallink = 1;
module_param_named(duallink, nouveau_duallink, int, 0400);

MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
int nouveau_uscript_lvds = -1;
module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);

MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
int nouveau_uscript_tmds = -1;
module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);

MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
int nouveau_ignorelid = 0;
module_param_named(ignorelid, nouveau_ignorelid, int, 0400);

MODULE_PARM_DESC(noaccel, "Disable all acceleration");
int nouveau_noaccel = 0;
module_param_named(noaccel, nouveau_noaccel, int, 0400);

MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
int nouveau_nofbaccel = 0;
module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);

MODULE_PARM_DESC(force_post, "Force POST");
int nouveau_force_post = 0;
module_param_named(force_post, nouveau_force_post, int, 0400);

MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
int nouveau_override_conntype = 0;
module_param_named(override_conntype, nouveau_override_conntype, int, 0400);

MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
int nouveau_tv_disable = 0;
module_param_named(tv_disable, nouveau_tv_disable, int, 0400);

MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
		 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
		 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
		 "\t\tDefault: PAL\n"
		 "\t\t*NOTE* Ignored for cards with external TV encoders.");
char *nouveau_tv_norm;
module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);

MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
		"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
		"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
		"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
int nouveau_reg_debug;
module_param_named(reg_debug, nouveau_reg_debug, int, 0600);

MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
char *nouveau_perflvl;
module_param_named(perflvl, nouveau_perflvl, charp, 0400);

MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
int nouveau_perflvl_wr;
module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);

MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
int nouveau_msi;
module_param_named(msi, nouveau_msi, int, 0400);

int nouveau_fbpercrtc;
#if 0
module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
#endif

static struct pci_device_id pciidlist[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
		.class = PCI_BASE_CLASS_DISPLAY << 16,
		.class_mask  = 0xff << 16,
	},
	{}
};

MODULE_DEVICE_TABLE(pci, pciidlist);

static struct drm_driver driver;

static int __devinit
nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	return drm_get_pci_dev(pdev, ent, &driver);
}

static void
nouveau_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

int
nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_channel *chan;
	struct drm_crtc *crtc;
	int ret, i;

	if (pm_state.event == PM_EVENT_PRETHAW)
		return 0;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	NV_INFO(dev, "Disabling fbcon acceleration...\n");
	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_unpin(nouveau_fb->nvbo);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nouveau_bo_unmap(nv_crtc->cursor.nvbo);
		nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	}

	NV_INFO(dev, "Evicting buffers...\n");
	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);

	NV_INFO(dev, "Idling channels...\n");
	for (i = 0; i < pfifo->channels; i++) {
		chan = dev_priv->channels.ptr[i];

		if (chan && chan->pushbuf_bo)
			nouveau_channel_idle(chan);
	}

	pgraph->fifo_access(dev, false);
	nouveau_wait_for_idle(dev);
	pfifo->reassign(dev, false);
	pfifo->disable(dev);
	pfifo->unload_context(dev);
	pgraph->unload_context(dev);

	ret = pinstmem->suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		goto out_abort;
	}

	NV_INFO(dev, "Suspending GPU objects...\n");
	ret = nouveau_gpuobj_suspend(dev);
	if (ret) {
		NV_ERROR(dev, "... failed: %d\n", ret);
		pinstmem->resume(dev);
		goto out_abort;
	}

	NV_INFO(dev, "And we're gone!\n");
	pci_save_state(pdev);
	if (pm_state.event == PM_EVENT_SUSPEND) {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	console_lock();
	nouveau_fbcon_set_suspend(dev, 1);
	console_unlock();
	nouveau_fbcon_restore_accel(dev);
	return 0;

out_abort:
	NV_INFO(dev, "Re-enabling acceleration..\n");
	pfifo->enable(dev);
	pfifo->reassign(dev, true);
	pgraph->fifo_access(dev, true);
	return ret;
}

int
nouveau_pci_resume(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_engine *engine = &dev_priv->engine;
	struct drm_crtc *crtc;
	int ret, i;

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

	nouveau_fbcon_save_disable_accel(dev);

	NV_INFO(dev, "We're back, enabling device...\n");
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	if (pci_enable_device(pdev))
		return -1;
	pci_set_master(dev->pdev);

	/* Make sure the AGP controller is in a consistent state */
	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
		nouveau_mem_reset_agp(dev);

	/* Make the CRTCs accessible */
	engine->display.early_init(dev);

	NV_INFO(dev, "POSTing device...\n");
	ret = nouveau_run_vbios_init(dev);
	if (ret)
		return ret;

	nouveau_pm_resume(dev);

	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
		ret = nouveau_mem_init_agp(dev);
		if (ret) {
			NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "Restoring GPU objects...\n");
	nouveau_gpuobj_resume(dev);

	NV_INFO(dev, "Reinitialising engines...\n");
	engine->instmem.resume(dev);
	engine->mc.init(dev);
	engine->timer.init(dev);
	engine->fb.init(dev);
	engine->graph.init(dev);
	engine->crypt.init(dev);
	engine->fifo.init(dev);

	nouveau_irq_postinstall(dev);

	/* Re-write SKIPS, they'll have been lost over the suspend */
	if (nouveau_vram_pushbuf) {
		struct nouveau_channel *chan;
		int j;

		for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
			chan = dev_priv->channels.ptr[i];
			if (!chan || !chan->pushbuf_bo)
				continue;

			for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
				nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
		}
	}

	NV_INFO(dev, "Restoring mode...\n");
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_framebuffer *nouveau_fb;

		nouveau_fb = nouveau_framebuffer(crtc->fb);
		if (!nouveau_fb || !nouveau_fb->nvbo)
			continue;

		nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
		if (!ret)
			ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
		if (ret)
			NV_ERROR(dev, "Could not pin/map cursor.\n");
	}

	engine->display.init(dev);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
		u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT;

		nv_crtc->cursor.set_offset(nv_crtc, offset);
		nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
						 nv_crtc->cursor_saved_y);
	}

	/* Force CLUT to get re-loaded during modeset */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);

		nv_crtc->lut.depth = 0;
	}

	console_lock();
	nouveau_fbcon_set_suspend(dev, 0);
	console_unlock();

	nouveau_fbcon_zfill_all(dev);

	drm_helper_resume_force_mode(dev);

	nouveau_fbcon_restore_accel(dev);
	return 0;
}

static struct drm_driver driver = {
	.driver_features =
		DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
		DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
		DRIVER_MODESET,
	.load = nouveau_load,
	.firstopen = nouveau_firstopen,
	.lastclose = nouveau_lastclose,
	.unload = nouveau_unload,
	.preclose = nouveau_preclose,
#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	.debugfs_init = nouveau_debugfs_init,
	.debugfs_cleanup = nouveau_debugfs_takedown,
#endif
	.irq_preinstall = nouveau_irq_preinstall,
	.irq_postinstall = nouveau_irq_postinstall,
	.irq_uninstall = nouveau_irq_uninstall,
	.irq_handler = nouveau_irq_handler,
	.get_vblank_counter = drm_vblank_count,
	.enable_vblank = nouveau_vblank_enable,
	.disable_vblank = nouveau_vblank_disable,
	.reclaim_buffers = drm_core_reclaim_buffers,
	.ioctls = nouveau_ioctls,
	.fops = {
		.owner = THIS_MODULE,
		.open = drm_open,
		.release = drm_release,
		.unlocked_ioctl = drm_ioctl,
		.mmap = nouveau_ttm_mmap,
		.poll = drm_poll,
		.fasync = drm_fasync,
		.read = drm_read,
#if defined(CONFIG_COMPAT)
		.compat_ioctl = nouveau_compat_ioctl,
#endif
		.llseek = noop_llseek,
	},
	.pci_driver = {
		.name = DRIVER_NAME,
		.id_table = pciidlist,
		.probe = nouveau_pci_probe,
		.remove = nouveau_pci_remove,
		.suspend = nouveau_pci_suspend,
		.resume = nouveau_pci_resume
	},

	.gem_init_object = nouveau_gem_object_new,
	.gem_free_object = nouveau_gem_object_del,

	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
#ifdef GIT_REVISION
	.date = GIT_REVISION,
#else
	.date = DRIVER_DATE,
#endif
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
};

static int __init nouveau_init(void)
{
	driver.num_ioctls = nouveau_max_ioctl;

	if (nouveau_modeset == -1) {
#ifdef CONFIG_VGA_CONSOLE
		if (vgacon_text_force())
			nouveau_modeset = 0;
		else
#endif
			nouveau_modeset = 1;
	}

	if (!nouveau_modeset)
		return 0;

	nouveau_register_dsm_handler();
	return drm_init(&driver);
}

static void __exit nouveau_exit(void)
{
	if (!nouveau_modeset)
		return;

	drm_exit(&driver);
	nouveau_unregister_dsm_handler();
}

module_init(nouveau_init);
module_exit(nouveau_exit);

MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#include <linux/console.h>
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "drm_crtc_helper.h"
	30	#include "nouveau_drv.h"
	31	#include "nouveau_hw.h"
	32	#include "nouveau_fb.h"
	33	#include "nouveau_fbcon.h"
64f1c11a	34	#include "nouveau_pm.h"
6ee73861 BS	35	#include "nv50_display.h"
	36
	37	#include "drm_pciids.h"
	38
de5899bd FJ	39	MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
	40	int nouveau_agpmode = -1;
	41	module_param_named(agpmode, nouveau_agpmode, int, 0400);
6ee73861 BS	42
	43	MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
	44	static int nouveau_modeset = -1; /* kms */
	45	module_param_named(modeset, nouveau_modeset, int, 0400);
	46
	47	MODULE_PARM_DESC(vbios, "Override default VBIOS location");
	48	char *nouveau_vbios;
	49	module_param_named(vbios, nouveau_vbios, charp, 0400);
	50
	51	MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
	52	int nouveau_vram_pushbuf;
	53	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	54
	55	MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
2dfe36b1	56	int nouveau_vram_notify = 0;
6ee73861 BS	57	module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
	58
	59	MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
	60	int nouveau_duallink = 1;
	61	module_param_named(duallink, nouveau_duallink, int, 0400);
	62
	63	MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
	64	int nouveau_uscript_lvds = -1;
	65	module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
	66
	67	MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
	68	int nouveau_uscript_tmds = -1;
	69	module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
	70
a1470890 BS	71	MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
	72	int nouveau_ignorelid = 0;
	73	module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
	74
81e2d422	75	MODULE_PARM_DESC(noaccel, "Disable all acceleration");
a32ed69d MK	76	int nouveau_noaccel = 0;
	77	module_param_named(noaccel, nouveau_noaccel, int, 0400);
	78
81e2d422	79	MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
a32ed69d MK	80	int nouveau_nofbaccel = 0;
	81	module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
	82
0cba1b76 MK	83	MODULE_PARM_DESC(force_post, "Force POST");
	84	int nouveau_force_post = 0;
	85	module_param_named(force_post, nouveau_force_post, int, 0400);
	86
da647d5b BS	87	MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
	88	int nouveau_override_conntype = 0;
	89	module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
	90
f4053509 BS	91	MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
	92	int nouveau_tv_disable = 0;
	93	module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
	94
6ee73861 BS	95	MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
	96	"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
	97	"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
	98	"\t\tDefault: PAL\n"
	99	"\t\tNOTE Ignored for cards with external TV encoders.");
	100	char *nouveau_tv_norm;
	101	module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
	102
	103	MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
	104	"\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
	105	"\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
	106	"\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
	107	int nouveau_reg_debug;
	108	module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
	109
6f876986 BS	110	MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n");
	111	char *nouveau_perflvl;
	112	module_param_named(perflvl, nouveau_perflvl, charp, 0400);
	113
	114	MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n");
	115	int nouveau_perflvl_wr;
	116	module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
	117
35fa2f2a BS	118	MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n");
	119	int nouveau_msi;
	120	module_param_named(msi, nouveau_msi, int, 0400);
	121
6ee73861 BS	122	int nouveau_fbpercrtc;
	123	#if 0
	124	module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
	125	#endif
	126
	127	static struct pci_device_id pciidlist[] = {
	128	{
	129	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
	130	.class = PCI_BASE_CLASS_DISPLAY << 16,
	131	.class_mask = 0xff << 16,
	132	},
	133	{
	134	PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
	135	.class = PCI_BASE_CLASS_DISPLAY << 16,
	136	.class_mask = 0xff << 16,
	137	},
	138	{}
	139	};
	140
	141	MODULE_DEVICE_TABLE(pci, pciidlist);
	142
	143	static struct drm_driver driver;
	144
	145	static int __devinit
	146	nouveau_pci_probe(struct pci_dev pdev, const struct pci_device_id ent)
	147	{
dcdb1674	148	return drm_get_pci_dev(pdev, ent, &driver);
6ee73861 BS	149	}
	150
	151	static void
	152	nouveau_pci_remove(struct pci_dev *pdev)
	153	{
	154	struct drm_device *dev = pci_get_drvdata(pdev);
	155
	156	drm_put_dev(dev);
	157	}
	158
6a9ee8af	159	int
6ee73861 BS	160	nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
	161	{
	162	struct drm_device *dev = pci_get_drvdata(pdev);
	163	struct drm_nouveau_private *dev_priv = dev->dev_private;
	164	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	165	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	166	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	167	struct nouveau_channel *chan;
	168	struct drm_crtc *crtc;
6ee73861 BS	169	int ret, i;
6ee73861 BS	170
6ee73861 BS	171	if (pm_state.event == PM_EVENT_PRETHAW)
	172	return 0;
	173
5bcf719b DA	174	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	175	return 0;
	176
81441570	177	NV_INFO(dev, "Disabling fbcon acceleration...\n");
38651674	178	nouveau_fbcon_save_disable_accel(dev);
6ee73861	179
81441570	180	NV_INFO(dev, "Unpinning framebuffer(s)...\n");
6ee73861 BS	181	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	182	struct nouveau_framebuffer *nouveau_fb;
	183
	184	nouveau_fb = nouveau_framebuffer(crtc->fb);
	185	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	186	continue;
	187
	188	nouveau_bo_unpin(nouveau_fb->nvbo);
	189	}
	190
b334f2b3 MM	191	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	192	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	193
	194	nouveau_bo_unmap(nv_crtc->cursor.nvbo);
	195	nouveau_bo_unpin(nv_crtc->cursor.nvbo);
	196	}
	197
6ee73861 BS	198	NV_INFO(dev, "Evicting buffers...\n");
	199	ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
	200
	201	NV_INFO(dev, "Idling channels...\n");
	202	for (i = 0; i < pfifo->channels; i++) {
cff5c133	203	chan = dev_priv->channels.ptr[i];
6ee73861	204
6dccd311 FJ	205	if (chan && chan->pushbuf_bo)
6dccd311 FJ	206	nouveau_channel_idle(chan);
6ee73861 BS	207	}
	208
	209	pgraph->fifo_access(dev, false);
	210	nouveau_wait_for_idle(dev);
	211	pfifo->reassign(dev, false);
	212	pfifo->disable(dev);
	213	pfifo->unload_context(dev);
	214	pgraph->unload_context(dev);
	215
dc1e5c0d	216	ret = pinstmem->suspend(dev);
6ee73861 BS	217	if (ret) {
	218	NV_ERROR(dev, "... failed: %d\n", ret);
	219	goto out_abort;
	220	}
	221
dc1e5c0d BS	222	NV_INFO(dev, "Suspending GPU objects...\n");
dc1e5c0d BS	223	ret = nouveau_gpuobj_suspend(dev);
6ee73861 BS	224	if (ret) {
6ee73861 BS	225	NV_ERROR(dev, "... failed: %d\n", ret);
dc1e5c0d	226	pinstmem->resume(dev);
6ee73861 BS	227	goto out_abort;
	228	}
	229
	230	NV_INFO(dev, "And we're gone!\n");
	231	pci_save_state(pdev);
	232	if (pm_state.event == PM_EVENT_SUSPEND) {
	233	pci_disable_device(pdev);
	234	pci_set_power_state(pdev, PCI_D3hot);
	235	}
	236
ac751efa	237	console_lock();
38651674	238	nouveau_fbcon_set_suspend(dev, 1);
ac751efa	239	console_unlock();
38651674	240	nouveau_fbcon_restore_accel(dev);
6ee73861 BS	241	return 0;
	242
	243	out_abort:
	244	NV_INFO(dev, "Re-enabling acceleration..\n");
	245	pfifo->enable(dev);
	246	pfifo->reassign(dev, true);
	247	pgraph->fifo_access(dev, true);
	248	return ret;
	249	}
	250
6a9ee8af	251	int
6ee73861 BS	252	nouveau_pci_resume(struct pci_dev *pdev)
	253	{
	254	struct drm_device *dev = pci_get_drvdata(pdev);
	255	struct drm_nouveau_private *dev_priv = dev->dev_private;
	256	struct nouveau_engine *engine = &dev_priv->engine;
	257	struct drm_crtc *crtc;
6ee73861 BS	258	int ret, i;
6ee73861 BS	259
5bcf719b DA	260	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
	261	return 0;
	262
38651674	263	nouveau_fbcon_save_disable_accel(dev);
6ee73861 BS	264
	265	NV_INFO(dev, "We're back, enabling device...\n");
	266	pci_set_power_state(pdev, PCI_D0);
	267	pci_restore_state(pdev);
	268	if (pci_enable_device(pdev))
	269	return -1;
	270	pci_set_master(dev->pdev);
	271
e04d8e82 FJ	272	/* Make sure the AGP controller is in a consistent state */
	273	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	274	nouveau_mem_reset_agp(dev);
	275
c88c2e06 FJ	276	/* Make the CRTCs accessible */
	277	engine->display.early_init(dev);
	278
6ee73861 BS	279	NV_INFO(dev, "POSTing device...\n");
	280	ret = nouveau_run_vbios_init(dev);
	281	if (ret)
	282	return ret;
	283
64f1c11a BS	284	nouveau_pm_resume(dev);
64f1c11a BS	285
6ee73861 BS	286	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
	287	ret = nouveau_mem_init_agp(dev);
	288	if (ret) {
	289	NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
	290	return ret;
	291	}
	292	}
	293
dc1e5c0d BS	294	NV_INFO(dev, "Restoring GPU objects...\n");
	295	nouveau_gpuobj_resume(dev);
	296
6ee73861 BS	297	NV_INFO(dev, "Reinitialising engines...\n");
	298	engine->instmem.resume(dev);
	299	engine->mc.init(dev);
	300	engine->timer.init(dev);
	301	engine->fb.init(dev);
	302	engine->graph.init(dev);
bd2e597d	303	engine->crypt.init(dev);
6ee73861 BS	304	engine->fifo.init(dev);
6ee73861 BS	305
6ee73861 BS	306	nouveau_irq_postinstall(dev);
	307
	308	/* Re-write SKIPS, they'll have been lost over the suspend */
	309	if (nouveau_vram_pushbuf) {
	310	struct nouveau_channel *chan;
	311	int j;
	312
	313	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
cff5c133	314	chan = dev_priv->channels.ptr[i];
3c8868d3	315	if (!chan \|\| !chan->pushbuf_bo)
6ee73861 BS	316	continue;
	317
	318	for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
	319	nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
	320	}
	321	}
	322
	323	NV_INFO(dev, "Restoring mode...\n");
	324	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	325	struct nouveau_framebuffer *nouveau_fb;
	326
	327	nouveau_fb = nouveau_framebuffer(crtc->fb);
	328	if (!nouveau_fb \|\| !nouveau_fb->nvbo)
	329	continue;
	330
	331	nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
	332	}
	333
b334f2b3 MM	334	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	335	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
b334f2b3 MM	336
	337	ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
	338	if (!ret)
	339	ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
	340	if (ret)
	341	NV_ERROR(dev, "Could not pin/map cursor.\n");
	342	}
	343
c88c2e06	344	engine->display.init(dev);
6ee73861	345
b334f2b3 MM	346	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
b334f2b3 MM	347	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
4c136142	348	u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT;
b334f2b3	349
4c136142	350	nv_crtc->cursor.set_offset(nv_crtc, offset);
b334f2b3	351	nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
4c136142	352	nv_crtc->cursor_saved_y);
b334f2b3 MM	353	}
b334f2b3 MM	354
6ee73861 BS	355	/* Force CLUT to get re-loaded during modeset */
	356	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	357	struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
	358
	359	nv_crtc->lut.depth = 0;
	360	}
	361
ac751efa	362	console_lock();
38651674	363	nouveau_fbcon_set_suspend(dev, 0);
ac751efa	364	console_unlock();
6ee73861	365
38651674	366	nouveau_fbcon_zfill_all(dev);
6ee73861 BS	367
6ee73861 BS	368	drm_helper_resume_force_mode(dev);
38651674 DA	369
38651674 DA	370	nouveau_fbcon_restore_accel(dev);
6ee73861 BS	371	return 0;
	372	}
	373
	374	static struct drm_driver driver = {
	375	.driver_features =
	376	DRIVER_USE_AGP \| DRIVER_PCI_DMA \| DRIVER_SG \|
cd0b072f BS	377	DRIVER_HAVE_IRQ \| DRIVER_IRQ_SHARED \| DRIVER_GEM \|
cd0b072f BS	378	DRIVER_MODESET,
6ee73861 BS	379	.load = nouveau_load,
	380	.firstopen = nouveau_firstopen,
	381	.lastclose = nouveau_lastclose,
	382	.unload = nouveau_unload,
	383	.preclose = nouveau_preclose,
	384	#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
	385	.debugfs_init = nouveau_debugfs_init,
	386	.debugfs_cleanup = nouveau_debugfs_takedown,
	387	#endif
	388	.irq_preinstall = nouveau_irq_preinstall,
	389	.irq_postinstall = nouveau_irq_postinstall,
	390	.irq_uninstall = nouveau_irq_uninstall,
	391	.irq_handler = nouveau_irq_handler,
042206c0 FJ	392	.get_vblank_counter = drm_vblank_count,
	393	.enable_vblank = nouveau_vblank_enable,
	394	.disable_vblank = nouveau_vblank_disable,
6ee73861	395	.reclaim_buffers = drm_core_reclaim_buffers,
6ee73861 BS	396	.ioctls = nouveau_ioctls,
	397	.fops = {
	398	.owner = THIS_MODULE,
	399	.open = drm_open,
	400	.release = drm_release,
ed8b6704	401	.unlocked_ioctl = drm_ioctl,
6ee73861 BS	402	.mmap = nouveau_ttm_mmap,
	403	.poll = drm_poll,
	404	.fasync = drm_fasync,
042206c0	405	.read = drm_read,
6ee73861 BS	406	#if defined(CONFIG_COMPAT)
	407	.compat_ioctl = nouveau_compat_ioctl,
	408	#endif
dc880abe	409	.llseek = noop_llseek,
6ee73861 BS	410	},
	411	.pci_driver = {
	412	.name = DRIVER_NAME,
	413	.id_table = pciidlist,
	414	.probe = nouveau_pci_probe,
	415	.remove = nouveau_pci_remove,
	416	.suspend = nouveau_pci_suspend,
	417	.resume = nouveau_pci_resume
	418	},
	419
	420	.gem_init_object = nouveau_gem_object_new,
	421	.gem_free_object = nouveau_gem_object_del,
	422
	423	.name = DRIVER_NAME,
	424	.desc = DRIVER_DESC,
	425	#ifdef GIT_REVISION
	426	.date = GIT_REVISION,
	427	#else
	428	.date = DRIVER_DATE,
	429	#endif
	430	.major = DRIVER_MAJOR,
	431	.minor = DRIVER_MINOR,
	432	.patchlevel = DRIVER_PATCHLEVEL,
	433	};
	434
	435	static int __init nouveau_init(void)
	436	{
	437	driver.num_ioctls = nouveau_max_ioctl;
	438
	439	if (nouveau_modeset == -1) {
	440	#ifdef CONFIG_VGA_CONSOLE
	441	if (vgacon_text_force())
	442	nouveau_modeset = 0;
	443	else
	444	#endif
	445	nouveau_modeset = 1;
	446	}
	447
cd0b072f BS	448	if (!nouveau_modeset)
cd0b072f BS	449	return 0;
6ee73861	450
cd0b072f	451	nouveau_register_dsm_handler();
6ee73861 BS	452	return drm_init(&driver);
	453	}
	454
	455	static void __exit nouveau_exit(void)
	456	{
cd0b072f BS	457	if (!nouveau_modeset)
	458	return;
	459
6ee73861	460	drm_exit(&driver);
6a9ee8af	461	nouveau_unregister_dsm_handler();
6ee73861 BS	462	}
	463
	464	module_init(nouveau_init);
	465	module_exit(nouveau_exit);
	466
	467	MODULE_AUTHOR(DRIVER_AUTHOR);
	468	MODULE_DESCRIPTION(DRIVER_DESC);
	469	MODULE_LICENSE("GPL and additional rights");