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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
6ee73861
BS		 99 int pin_refcnt;
100};
101
f13b3263
FJ		 102#define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
104
6ee73861
BS		 105static inline struct nouveau_bo *
106nouveau_bo(struct ttm_buffer_object *bo)
107{
108 return container_of(bo, struct nouveau_bo, bo);
109}
110
111static inline struct nouveau_bo *
112nouveau_gem_object(struct drm_gem_object *gem)
113{
114 return gem ? gem->driver_private : NULL;
115}
116
117/* TODO: submit equivalent to TTM generic API upstream? */
118static inline void __iomem *
119nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120{
121 bool is_iomem;
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
125 return ioptr;
126}
127
6ee73861
BS		 128enum nouveau_flags {
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
131};
132
133#define NVOBJ_ENGINE_SW 0
134#define NVOBJ_ENGINE_GR 1
135#define NVOBJ_ENGINE_DISPLAY 2
136#define NVOBJ_ENGINE_INT 0xdeadbeef
137
6ee73861
BS		 138#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
139#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 140struct nouveau_gpuobj {
b3beb167 141 struct drm_device *dev;
eb9bcbdc 142 struct kref refcount;
6ee73861
BS		 143 struct list_head list;
144
b833ac26 145 struct drm_mm_node *im_pramin;
6ee73861 146 struct nouveau_bo *im_backing;
6ee73861
BS		 147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
6ee73861 151
43efc9ce 152 u32 size;
de3a6c0a
BS		 153 u32 pinst;
154 u32 cinst;
155 u64 vinst;
156
6ee73861
BS		 157 uint32_t engine;
158 uint32_t class;
159
160 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
161 void *priv;
162};
163
6ee73861
BS		 164struct nouveau_channel {
165 struct drm_device *dev;
166 int id;
167
f091a3d4
FJ		 168 /* references to the channel data structure */
169 struct kref ref;
170 /* users of the hardware channel resources, the hardware
171 * context will be kicked off when it reaches zero. */
172 atomic_t users;
6a6b73f2
BS		 173 struct mutex mutex;
174
6ee73861
BS		 175 /* owner of this fifo */
176 struct drm_file *file_priv;
177 /* mapping of the fifo itself */
178 struct drm_local_map *map;
179
180 /* mapping of the regs controling the fifo */
181 void __iomem *user;
182 uint32_t user_get;
183 uint32_t user_put;
184
185 /* Fencing */
186 struct {
187 /* lock protects the pending list only */
188 spinlock_t lock;
189 struct list_head pending;
190 uint32_t sequence;
191 uint32_t sequence_ack;
047d1d3c 192 atomic_t last_sequence_irq;
6ee73861
BS		 193 } fence;
194
195 /* DMA push buffer */
a8eaebc6
BS		 196 struct nouveau_gpuobj *pushbuf;
197 struct nouveau_bo *pushbuf_bo;
198 uint32_t pushbuf_base;
6ee73861
BS		 199
200 /* Notifier memory */
201 struct nouveau_bo *notifier_bo;
b833ac26 202 struct drm_mm notifier_heap;
6ee73861
BS		 203
204 /* PFIFO context */
a8eaebc6
BS		 205 struct nouveau_gpuobj *ramfc;
206 struct nouveau_gpuobj *cache;
6ee73861
BS		 207
208 /* PGRAPH context */
209 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 210 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 211 void *pgraph_ctx;
212
213 /* NV50 VM */
a8eaebc6
BS		 214 struct nouveau_gpuobj *vm_pd;
215 struct nouveau_gpuobj *vm_gart_pt;
216 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 217
218 /* Objects */
a8eaebc6
BS		 219 struct nouveau_gpuobj *ramin; /* Private instmem */
220 struct drm_mm ramin_heap; /* Private PRAMIN heap */
221 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 222
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
224 uint32_t m2mf_ntfy;
225 uint32_t vram_handle;
226 uint32_t gart_handle;
227 bool accel_done;
228
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
230 struct {
231 int max;
232 int free;
233 int cur;
234 int put;
235 /* access via pushbuf_bo */
9a391ad8
BS		 236
237 int ib_base;
238 int ib_max;
239 int ib_free;
240 int ib_put;
6ee73861
BS		 241 } dma;
242
243 uint32_t sw_subchannel[8];
244
245 struct {
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
250 } nvsw;
251
252 struct {
253 bool active;
254 char name[32];
255 struct drm_info_list info;
256 } debugfs;
257};
258
259struct nouveau_instmem_engine {
260 void *priv;
261
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
266
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
268 uint32_t *size);
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 272 void (*flush)(struct drm_device *);
6ee73861
BS		 273};
274
275struct nouveau_mc_engine {
276 int (*init)(struct drm_device *dev);
277 void (*takedown)(struct drm_device *dev);
278};
279
280struct nouveau_timer_engine {
281 int (*init)(struct drm_device *dev);
282 void (*takedown)(struct drm_device *dev);
283 uint64_t (*read)(struct drm_device *dev);
284};
285
286struct nouveau_fb_engine {
cb00f7c1
FJ		 287 int num_tiles;
288
6ee73861
BS		 289 int (*init)(struct drm_device *dev);
290 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 291
292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
293 uint32_t size, uint32_t pitch);
6ee73861
BS		 294};
295
296struct nouveau_fifo_engine {
6ee73861
BS		 297 int channels;
298
a8eaebc6 299 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 300 int cur_playlist;
301
6ee73861
BS		 302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
304
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 308 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 309
310 int (*channel_id)(struct drm_device *);
311
312 int (*create_context)(struct nouveau_channel *);
313 void (*destroy_context)(struct nouveau_channel *);
314 int (*load_context)(struct nouveau_channel *);
315 int (*unload_context)(struct drm_device *);
56ac7475 316 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 317};
318
319struct nouveau_pgraph_object_method {
320 int id;
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
322 uint32_t data);
323};
324
325struct nouveau_pgraph_object_class {
326 int id;
327 bool software;
328 struct nouveau_pgraph_object_method *methods;
329};
330
331struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
333 bool accel_blocked;
054b93e4 334 int grctx_size;
6ee73861 335
c50a5681 336 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 337 struct nouveau_gpuobj *ctx_table;
c50a5681 338
6ee73861
BS		 339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
341
342 void (*fifo_access)(struct drm_device *, bool);
343
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
56ac7475 349 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1
FJ		 350
351 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
352 uint32_t size, uint32_t pitch);
6ee73861
BS		 353};
354
c88c2e06
FJ		 355struct nouveau_display_engine {
356 int (*early_init)(struct drm_device *);
357 void (*late_takedown)(struct drm_device *);
358 int (*create)(struct drm_device *);
359 int (*init)(struct drm_device *);
360 void (*destroy)(struct drm_device *);
361};
362
ee2e0131
BS		 363struct nouveau_gpio_engine {
364 int (*init)(struct drm_device *);
365 void (*takedown)(struct drm_device *);
366
367 int (*get)(struct drm_device *, enum dcb_gpio_tag);
368 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
369
370 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
371};
372
330c5988
BS		 373struct nouveau_pm_voltage_level {
374 u8 voltage;
375 u8 vid;
376};
377
378struct nouveau_pm_voltage {
379 bool supported;
380 u8 vid_mask;
381
382 struct nouveau_pm_voltage_level *level;
383 int nr_level;
384};
385
386#define NOUVEAU_PM_MAX_LEVEL 8
387struct nouveau_pm_level {
388 struct device_attribute dev_attr;
389 char name[32];
390 int id;
391
392 u32 core;
393 u32 memory;
394 u32 shader;
395 u32 unk05;
396
397 u8 voltage;
398 u8 fanspeed;
aee582de
BS		 399
400 u16 memscript;
330c5988
BS		 401};
402
34e9d85a
MP		 403struct nouveau_pm_temp_sensor_constants {
404 u16 offset_constant;
405 s16 offset_mult;
406 u16 offset_div;
407 u16 slope_mult;
408 u16 slope_div;
409};
410
411struct nouveau_pm_threshold_temp {
412 s16 critical;
413 s16 down_clock;
414 s16 fan_boost;
415};
416
7760fcb0
RS		 417struct nouveau_pm_memtiming {
418 u32 reg_100220;
419 u32 reg_100224;
420 u32 reg_100228;
421 u32 reg_10022c;
422 u32 reg_100230;
423 u32 reg_100234;
424 u32 reg_100238;
425 u32 reg_10023c;
426};
427
428struct nouveau_pm_memtimings {
429 bool supported;
430 struct nouveau_pm_memtiming *timing;
431 int nr_timing;
432};
433
330c5988
BS		 434struct nouveau_pm_engine {
435 struct nouveau_pm_voltage voltage;
436 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
437 int nr_perflvl;
7760fcb0 438 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 439 struct nouveau_pm_temp_sensor_constants sensor_constants;
440 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 441
442 struct nouveau_pm_level boot;
443 struct nouveau_pm_level *cur;
444
8155cac4 445 struct device *hwmon;
6032649d 446 struct notifier_block acpi_nb;
8155cac4 447
330c5988 448 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 449 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
450 u32 id, int khz);
330c5988
BS		 451 void (*clock_set)(struct drm_device *, void *);
452 int (*voltage_get)(struct drm_device *);
453 int (*voltage_set)(struct drm_device *, int voltage);
454 int (*fanspeed_get)(struct drm_device *);
455 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 456 int (*temp_get)(struct drm_device *);
330c5988
BS		 457};
458
6ee73861
BS		 459struct nouveau_engine {
460 struct nouveau_instmem_engine instmem;
461 struct nouveau_mc_engine mc;
462 struct nouveau_timer_engine timer;
463 struct nouveau_fb_engine fb;
464 struct nouveau_pgraph_engine graph;
465 struct nouveau_fifo_engine fifo;
c88c2e06 466 struct nouveau_display_engine display;
ee2e0131 467 struct nouveau_gpio_engine gpio;
330c5988 468 struct nouveau_pm_engine pm;
6ee73861
BS		 469};
470
471struct nouveau_pll_vals {
472 union {
473 struct {
474#ifdef __BIG_ENDIAN
475 uint8_t N1, M1, N2, M2;
476#else
477 uint8_t M1, N1, M2, N2;
478#endif
479 };
480 struct {
481 uint16_t NM1, NM2;
482 } __attribute__((packed));
483 };
484 int log2P;
485
486 int refclk;
487};
488
489enum nv04_fp_display_regs {
490 FP_DISPLAY_END,
491 FP_TOTAL,
492 FP_CRTC,
493 FP_SYNC_START,
494 FP_SYNC_END,
495 FP_VALID_START,
496 FP_VALID_END
497};
498
499struct nv04_crtc_reg {
cbab95db 500 unsigned char MiscOutReg;
4a9f822f 501 uint8_t CRTC[0xa0];
6ee73861
BS		 502 uint8_t CR58[0x10];
503 uint8_t Sequencer[5];
504 uint8_t Graphics[9];
505 uint8_t Attribute[21];
cbab95db 506 unsigned char DAC[768];
6ee73861
BS		 507
508 /* PCRTC regs */
509 uint32_t fb_start;
510 uint32_t crtc_cfg;
511 uint32_t cursor_cfg;
512 uint32_t gpio_ext;
513 uint32_t crtc_830;
514 uint32_t crtc_834;
515 uint32_t crtc_850;
516 uint32_t crtc_eng_ctrl;
517
518 /* PRAMDAC regs */
519 uint32_t nv10_cursync;
520 struct nouveau_pll_vals pllvals;
521 uint32_t ramdac_gen_ctrl;
522 uint32_t ramdac_630;
523 uint32_t ramdac_634;
524 uint32_t tv_setup;
525 uint32_t tv_vtotal;
526 uint32_t tv_vskew;
527 uint32_t tv_vsync_delay;
528 uint32_t tv_htotal;
529 uint32_t tv_hskew;
530 uint32_t tv_hsync_delay;
531 uint32_t tv_hsync_delay2;
532 uint32_t fp_horiz_regs[7];
533 uint32_t fp_vert_regs[7];
534 uint32_t dither;
535 uint32_t fp_control;
536 uint32_t dither_regs[6];
537 uint32_t fp_debug_0;
538 uint32_t fp_debug_1;
539 uint32_t fp_debug_2;
540 uint32_t fp_margin_color;
541 uint32_t ramdac_8c0;
542 uint32_t ramdac_a20;
543 uint32_t ramdac_a24;
544 uint32_t ramdac_a34;
545 uint32_t ctv_regs[38];
546};
547
548struct nv04_output_reg {
549 uint32_t output;
550 int head;
551};
552
553struct nv04_mode_state {
cbab95db 554 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 555 uint32_t pllsel;
556 uint32_t sel_clk;
6ee73861
BS		 557};
558
559enum nouveau_card_type {
560 NV_04 = 0x00,
561 NV_10 = 0x10,
562 NV_20 = 0x20,
563 NV_30 = 0x30,
564 NV_40 = 0x40,
565 NV_50 = 0x50,
4b223eef 566 NV_C0 = 0xc0,
6ee73861
BS		 567};
568
569struct drm_nouveau_private {
570 struct drm_device *dev;
6ee73861
BS		 571
572 /* the card type, takes NV_* as values */
573 enum nouveau_card_type card_type;
574 /* exact chipset, derived from NV_PMC_BOOT_0 */
575 int chipset;
576 int flags;
577
578 void __iomem *mmio;
5125bfd8 579
e05d7eae 580 spinlock_t ramin_lock;
6ee73861 581 void __iomem *ramin;
5125bfd8
BS		 582 u32 ramin_size;
583 u32 ramin_base;
584 bool ramin_available;
e05d7eae
BS		 585 struct drm_mm ramin_heap;
586 struct list_head gpuobj_list;
6ee73861 587
ac8fb975
BS		 588 struct nouveau_bo *vga_ram;
589
6ee73861
BS		 590 struct workqueue_struct *wq;
591 struct work_struct irq_work;
a5acac66 592 struct work_struct hpd_work;
6ee73861 593
ab838338
AL		 594 struct {
595 spinlock_t lock;
596 uint32_t hpd0_bits;
597 uint32_t hpd1_bits;
598 } hpd_state;
599
6ee73861
BS		 600 struct list_head vbl_waiting;
601
602 struct {
ba4420c2 603 struct drm_global_reference mem_global_ref;
6ee73861
BS		 604 struct ttm_bo_global_ref bo_global_ref;
605 struct ttm_bo_device bdev;
6ee73861
BS		 606 atomic_t validate_sequence;
607 } ttm;
608
0c6c1c2f
FJ		 609 struct {
610 spinlock_t lock;
611 struct drm_mm heap;
612 struct nouveau_bo *bo;
613 } fence;
614
cff5c133
BS		 615 struct {
616 spinlock_t lock;
617 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
618 } channels;
6ee73861
BS		 619
620 struct nouveau_engine engine;
621 struct nouveau_channel *channel;
622
ff9e5279
MM		 623 /* For PFIFO and PGRAPH. */
624 spinlock_t context_switch_lock;
625
6ee73861 626 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 627 struct nouveau_ramht *ramht;
628 struct nouveau_gpuobj *ramfc;
629 struct nouveau_gpuobj *ramro;
630
6ee73861 631 uint32_t ramin_rsvd_vram;
6ee73861 632
6ee73861
BS		 633 struct {
634 enum {
635 NOUVEAU_GART_NONE = 0,
636 NOUVEAU_GART_AGP,
637 NOUVEAU_GART_SGDMA
638 } type;
639 uint64_t aper_base;
640 uint64_t aper_size;
641 uint64_t aper_free;
642
643 struct nouveau_gpuobj *sg_ctxdma;
644 struct page *sg_dummy_page;
645 dma_addr_t sg_dummy_bus;
6ee73861
BS		 646 } gart_info;
647
a0af9add 648 /* nv10-nv40 tiling regions */
9f56b126 649 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 650
a76fb4e8
BS		 651 /* VRAM/fb configuration */
652 uint64_t vram_size;
653 uint64_t vram_sys_base;
6c3d7ef2 654 u32 vram_rblock_size;
a76fb4e8
BS		 655
656 uint64_t fb_phys;
657 uint64_t fb_available_size;
658 uint64_t fb_mappable_pages;
659 uint64_t fb_aper_free;
660 int fb_mtrr;
661
6ee73861
BS		 662 /* G8x/G9x virtual address space */
663 uint64_t vm_gart_base;
664 uint64_t vm_gart_size;
665 uint64_t vm_vram_base;
666 uint64_t vm_vram_size;
667 uint64_t vm_end;
668 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
669 int vm_vram_pt_nr;
6ee73861 670
04a39c57 671 struct nvbios vbios;
6ee73861
BS		 672
673 struct nv04_mode_state mode_reg;
674 struct nv04_mode_state saved_reg;
675 uint32_t saved_vga_font[4][16384];
676 uint32_t crtc_owner;
677 uint32_t dac_users[4];
678
679 struct nouveau_suspend_resume {
6ee73861 680 uint32_t *ramin_copy;
6ee73861
BS		 681 } susres;
682
683 struct backlight_device *backlight;
6ee73861
BS		 684
685 struct nouveau_channel *evo;
87c0e0e5
BS		 686 struct {
687 struct dcb_entry *dcb;
688 u16 script;
689 u32 pclk;
690 } evo_irq;
6ee73861
BS		 691
692 struct {
693 struct dentry *channel_root;
694 } debugfs;
38651674 695
8be48d92 696 struct nouveau_fbdev *nfbdev;
06415c56 697 struct apertures_struct *apertures;
6ee73861
BS		 698};
699
2730723b
FJ		 700static inline struct drm_nouveau_private *
701nouveau_private(struct drm_device *dev)
702{
703 return dev->dev_private;
704}
705
6ee73861
BS		 706static inline struct drm_nouveau_private *
707nouveau_bdev(struct ttm_bo_device *bd)
708{
709 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
710}
711
712static inline int
713nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
714{
715 struct nouveau_bo *prev;
716
717 if (!pnvbo)
718 return -EINVAL;
719 prev = *pnvbo;
720
721 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
722 if (prev) {
723 struct ttm_buffer_object *bo = &prev->bo;
724
725 ttm_bo_unref(&bo);
726 }
727
728 return 0;
729}
730
6ee73861 731/* nouveau_drv.c */
de5899bd 732extern int nouveau_agpmode;
6ee73861
BS		 733extern int nouveau_duallink;
734extern int nouveau_uscript_lvds;
735extern int nouveau_uscript_tmds;
736extern int nouveau_vram_pushbuf;
737extern int nouveau_vram_notify;
738extern int nouveau_fbpercrtc;
f4053509 739extern int nouveau_tv_disable;
6ee73861
BS		 740extern char *nouveau_tv_norm;
741extern int nouveau_reg_debug;
742extern char *nouveau_vbios;
a1470890 743extern int nouveau_ignorelid;
a32ed69d
MK		 744extern int nouveau_nofbaccel;
745extern int nouveau_noaccel;
0cba1b76 746extern int nouveau_force_post;
da647d5b 747extern int nouveau_override_conntype;
6f876986
BS		 748extern char *nouveau_perflvl;
749extern int nouveau_perflvl_wr;
6ee73861 750
6a9ee8af
DA		 751extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
752extern int nouveau_pci_resume(struct pci_dev *pdev);
753
6ee73861
BS		 754/* nouveau_state.c */
755extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
756extern int nouveau_load(struct drm_device *, unsigned long flags);
757extern int nouveau_firstopen(struct drm_device *);
758extern void nouveau_lastclose(struct drm_device *);
759extern int nouveau_unload(struct drm_device *);
760extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
761 struct drm_file *);
762extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
763 struct drm_file *);
764extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
765 uint32_t reg, uint32_t mask, uint32_t val);
766extern bool nouveau_wait_for_idle(struct drm_device *);
767extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 768
769/* nouveau_mem.c */
fbd2895e
BS		 770extern int nouveau_mem_vram_init(struct drm_device *);
771extern void nouveau_mem_vram_fini(struct drm_device *);
772extern int nouveau_mem_gart_init(struct drm_device *);
773extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 774extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 775extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 776extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 777extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
778 uint32_t addr,
779 uint32_t size,
780 uint32_t pitch);
781extern void nv10_mem_expire_tiling(struct drm_device *dev,
782 struct nouveau_tile_reg *tile,
783 struct nouveau_fence *fence);
6ee73861
BS		 784extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
785 uint32_t size, uint32_t flags,
786 uint64_t phys);
787extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
788 uint32_t size);
789
790/* nouveau_notifier.c */
791extern int nouveau_notifier_init_channel(struct nouveau_channel *);
792extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
793extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
794 int cout, uint32_t *offset);
795extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
796extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
797 struct drm_file *);
798extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
799 struct drm_file *);
800
801/* nouveau_channel.c */
802extern struct drm_ioctl_desc nouveau_ioctls[];
803extern int nouveau_max_ioctl;
804extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 805extern int nouveau_channel_alloc(struct drm_device *dev,
806 struct nouveau_channel **chan,
807 struct drm_file *file_priv,
808 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 809extern struct nouveau_channel *
feeb0aec
FJ		 810nouveau_channel_get_unlocked(struct nouveau_channel *);
811extern struct nouveau_channel *
cff5c133 812nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 813extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 814extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 815extern void nouveau_channel_ref(struct nouveau_channel *chan,
816 struct nouveau_channel **pchan);
6ee73861
BS		 817
818/* nouveau_object.c */
819extern int nouveau_gpuobj_early_init(struct drm_device *);
820extern int nouveau_gpuobj_init(struct drm_device *);
821extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 822extern int nouveau_gpuobj_suspend(struct drm_device *dev);
823extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
824extern void nouveau_gpuobj_resume(struct drm_device *dev);
825extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
826 uint32_t vram_h, uint32_t tt_h);
827extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
828extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
829 uint32_t size, int align, uint32_t flags,
830 struct nouveau_gpuobj **);
a8eaebc6
BS		 831extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
832 struct nouveau_gpuobj **);
43efc9ce
BS		 833extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
834 u32 size, u32 flags,
a8eaebc6 835 struct nouveau_gpuobj **);
6ee73861
BS		 836extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
837 uint64_t offset, uint64_t size, int access,
838 int target, struct nouveau_gpuobj **);
839extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
840 uint64_t offset, uint64_t size,
841 int access, struct nouveau_gpuobj **,
842 uint32_t *o_ret);
843extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
844 struct nouveau_gpuobj **);
f03a314b
FJ		 845extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
846 struct nouveau_gpuobj **);
6ee73861
BS		 847extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
848 struct drm_file *);
849extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
850 struct drm_file *);
851
852/* nouveau_irq.c */
853extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
854extern void nouveau_irq_preinstall(struct drm_device *);
855extern int nouveau_irq_postinstall(struct drm_device *);
856extern void nouveau_irq_uninstall(struct drm_device *);
857
858/* nouveau_sgdma.c */
859extern int nouveau_sgdma_init(struct drm_device *);
860extern void nouveau_sgdma_takedown(struct drm_device *);
861extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
862 uint32_t *page);
863extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
864
865/* nouveau_debugfs.c */
866#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
867extern int nouveau_debugfs_init(struct drm_minor *);
868extern void nouveau_debugfs_takedown(struct drm_minor *);
869extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
870extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
871#else
872static inline int
873nouveau_debugfs_init(struct drm_minor *minor)
874{
875 return 0;
876}
877
878static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
879{
880}
881
882static inline int
883nouveau_debugfs_channel_init(struct nouveau_channel *chan)
884{
885 return 0;
886}
887
888static inline void
889nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
890{
891}
892#endif
893
894/* nouveau_dma.c */
75c99da6 895extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 896extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 897extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 898
899/* nouveau_acpi.c */
afeb3e11 900#define ROM_BIOS_PAGE 4096
2f41a7f1 901#if defined(CONFIG_ACPI)
6a9ee8af
DA		 902void nouveau_register_dsm_handler(void);
903void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 904int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
905bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 906int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 907#else
908static inline void nouveau_register_dsm_handler(void) {}
909static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 910static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
911static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 912static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 913#endif
6ee73861
BS		 914
915/* nouveau_backlight.c */
916#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
917extern int nouveau_backlight_init(struct drm_device *);
918extern void nouveau_backlight_exit(struct drm_device *);
919#else
920static inline int nouveau_backlight_init(struct drm_device *dev)
921{
922 return 0;
923}
924
925static inline void nouveau_backlight_exit(struct drm_device *dev) { }
926#endif
927
928/* nouveau_bios.c */
929extern int nouveau_bios_init(struct drm_device *);
930extern void nouveau_bios_takedown(struct drm_device *dev);
931extern int nouveau_run_vbios_init(struct drm_device *);
932extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
933 struct dcb_entry *);
934extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
935 enum dcb_gpio_tag);
936extern struct dcb_connector_table_entry *
937nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 938extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 939extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
940 struct pll_lims *);
941extern int nouveau_bios_run_display_table(struct drm_device *,
942 struct dcb_entry *,
943 uint32_t script, int pxclk);
944extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
945 int *length);
946extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
947extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
948extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
949 bool *dl, bool *if_is_24bit);
950extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
951 int head, int pxclk);
952extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
953 enum LVDS_script, int pxclk);
954
955/* nouveau_ttm.c */
956int nouveau_ttm_global_init(struct drm_nouveau_private *);
957void nouveau_ttm_global_release(struct drm_nouveau_private *);
958int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
959
960/* nouveau_dp.c */
961int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
962 uint8_t *data, int data_nr);
963bool nouveau_dp_detect(struct drm_encoder *);
964bool nouveau_dp_link_train(struct drm_encoder *);
965
966/* nv04_fb.c */
967extern int nv04_fb_init(struct drm_device *);
968extern void nv04_fb_takedown(struct drm_device *);
969
970/* nv10_fb.c */
971extern int nv10_fb_init(struct drm_device *);
972extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 973extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
974 uint32_t, uint32_t);
6ee73861 975
8bded189
FJ		 976/* nv30_fb.c */
977extern int nv30_fb_init(struct drm_device *);
978extern void nv30_fb_takedown(struct drm_device *);
979
6ee73861
BS		 980/* nv40_fb.c */
981extern int nv40_fb_init(struct drm_device *);
982extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 983extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
984 uint32_t, uint32_t);
304424e1
MK		 985/* nv50_fb.c */
986extern int nv50_fb_init(struct drm_device *);
987extern void nv50_fb_takedown(struct drm_device *);
d96773e7 988extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 989
4b223eef
BS		 990/* nvc0_fb.c */
991extern int nvc0_fb_init(struct drm_device *);
992extern void nvc0_fb_takedown(struct drm_device *);
993
6ee73861
BS		 994/* nv04_fifo.c */
995extern int nv04_fifo_init(struct drm_device *);
996extern void nv04_fifo_disable(struct drm_device *);
997extern void nv04_fifo_enable(struct drm_device *);
998extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 999extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1000extern int nv04_fifo_channel_id(struct drm_device *);
1001extern int nv04_fifo_create_context(struct nouveau_channel *);
1002extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1003extern int nv04_fifo_load_context(struct nouveau_channel *);
1004extern int nv04_fifo_unload_context(struct drm_device *);
1005
1006/* nv10_fifo.c */
1007extern int nv10_fifo_init(struct drm_device *);
1008extern int nv10_fifo_channel_id(struct drm_device *);
1009extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1010extern int nv10_fifo_load_context(struct nouveau_channel *);
1011extern int nv10_fifo_unload_context(struct drm_device *);
1012
1013/* nv40_fifo.c */
1014extern int nv40_fifo_init(struct drm_device *);
1015extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1016extern int nv40_fifo_load_context(struct nouveau_channel *);
1017extern int nv40_fifo_unload_context(struct drm_device *);
1018
1019/* nv50_fifo.c */
1020extern int nv50_fifo_init(struct drm_device *);
1021extern void nv50_fifo_takedown(struct drm_device *);
1022extern int nv50_fifo_channel_id(struct drm_device *);
1023extern int nv50_fifo_create_context(struct nouveau_channel *);
1024extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1025extern int nv50_fifo_load_context(struct nouveau_channel *);
1026extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1027extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1028
4b223eef
BS		 1029/* nvc0_fifo.c */
1030extern int nvc0_fifo_init(struct drm_device *);
1031extern void nvc0_fifo_takedown(struct drm_device *);
1032extern void nvc0_fifo_disable(struct drm_device *);
1033extern void nvc0_fifo_enable(struct drm_device *);
1034extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1035extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1036extern int nvc0_fifo_channel_id(struct drm_device *);
1037extern int nvc0_fifo_create_context(struct nouveau_channel *);
1038extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1039extern int nvc0_fifo_load_context(struct nouveau_channel *);
1040extern int nvc0_fifo_unload_context(struct drm_device *);
1041
6ee73861
BS		 1042/* nv04_graph.c */
1043extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1044extern int nv04_graph_init(struct drm_device *);
1045extern void nv04_graph_takedown(struct drm_device *);
1046extern void nv04_graph_fifo_access(struct drm_device *, bool);
1047extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1048extern int nv04_graph_create_context(struct nouveau_channel *);
1049extern void nv04_graph_destroy_context(struct nouveau_channel *);
1050extern int nv04_graph_load_context(struct nouveau_channel *);
1051extern int nv04_graph_unload_context(struct drm_device *);
1052extern void nv04_graph_context_switch(struct drm_device *);
1053
1054/* nv10_graph.c */
1055extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1056extern int nv10_graph_init(struct drm_device *);
1057extern void nv10_graph_takedown(struct drm_device *);
1058extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1059extern int nv10_graph_create_context(struct nouveau_channel *);
1060extern void nv10_graph_destroy_context(struct nouveau_channel *);
1061extern int nv10_graph_load_context(struct nouveau_channel *);
1062extern int nv10_graph_unload_context(struct drm_device *);
1063extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1064extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1065 uint32_t, uint32_t);
6ee73861
BS		 1066
1067/* nv20_graph.c */
1068extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1069extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1070extern int nv20_graph_create_context(struct nouveau_channel *);
1071extern void nv20_graph_destroy_context(struct nouveau_channel *);
1072extern int nv20_graph_load_context(struct nouveau_channel *);
1073extern int nv20_graph_unload_context(struct drm_device *);
1074extern int nv20_graph_init(struct drm_device *);
1075extern void nv20_graph_takedown(struct drm_device *);
1076extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1077extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1078 uint32_t, uint32_t);
6ee73861
BS		 1079
1080/* nv40_graph.c */
1081extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1082extern int nv40_graph_init(struct drm_device *);
1083extern void nv40_graph_takedown(struct drm_device *);
1084extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1085extern int nv40_graph_create_context(struct nouveau_channel *);
1086extern void nv40_graph_destroy_context(struct nouveau_channel *);
1087extern int nv40_graph_load_context(struct nouveau_channel *);
1088extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1089extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1090extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1091 uint32_t, uint32_t);
6ee73861
BS		 1092
1093/* nv50_graph.c */
1094extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1095extern int nv50_graph_init(struct drm_device *);
1096extern void nv50_graph_takedown(struct drm_device *);
1097extern void nv50_graph_fifo_access(struct drm_device *, bool);
1098extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1099extern int nv50_graph_create_context(struct nouveau_channel *);
1100extern void nv50_graph_destroy_context(struct nouveau_channel *);
1101extern int nv50_graph_load_context(struct nouveau_channel *);
1102extern int nv50_graph_unload_context(struct drm_device *);
1103extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1104extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1105extern void nv50_graph_tlb_flush(struct drm_device *dev);
1106extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1107
4b223eef
BS		 1108/* nvc0_graph.c */
1109extern int nvc0_graph_init(struct drm_device *);
1110extern void nvc0_graph_takedown(struct drm_device *);
1111extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1112extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1113extern int nvc0_graph_create_context(struct nouveau_channel *);
1114extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1115extern int nvc0_graph_load_context(struct nouveau_channel *);
1116extern int nvc0_graph_unload_context(struct drm_device *);
1117
6ee73861
BS		 1118/* nv04_instmem.c */
1119extern int nv04_instmem_init(struct drm_device *);
1120extern void nv04_instmem_takedown(struct drm_device *);
1121extern int nv04_instmem_suspend(struct drm_device *);
1122extern void nv04_instmem_resume(struct drm_device *);
1123extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1124 uint32_t *size);
1125extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1126extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1127extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1128extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1129
1130/* nv50_instmem.c */
1131extern int nv50_instmem_init(struct drm_device *);
1132extern void nv50_instmem_takedown(struct drm_device *);
1133extern int nv50_instmem_suspend(struct drm_device *);
1134extern void nv50_instmem_resume(struct drm_device *);
1135extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1136 uint32_t *size);
1137extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1138extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1139extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1140extern void nv50_instmem_flush(struct drm_device *);
734ee835 1141extern void nv84_instmem_flush(struct drm_device *);
63187215 1142extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1143
4b223eef
BS		 1144/* nvc0_instmem.c */
1145extern int nvc0_instmem_init(struct drm_device *);
1146extern void nvc0_instmem_takedown(struct drm_device *);
1147extern int nvc0_instmem_suspend(struct drm_device *);
1148extern void nvc0_instmem_resume(struct drm_device *);
1149extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1150 uint32_t *size);
1151extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1152extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1153extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1154extern void nvc0_instmem_flush(struct drm_device *);
1155
6ee73861
BS		 1156/* nv04_mc.c */
1157extern int nv04_mc_init(struct drm_device *);
1158extern void nv04_mc_takedown(struct drm_device *);
1159
1160/* nv40_mc.c */
1161extern int nv40_mc_init(struct drm_device *);
1162extern void nv40_mc_takedown(struct drm_device *);
1163
1164/* nv50_mc.c */
1165extern int nv50_mc_init(struct drm_device *);
1166extern void nv50_mc_takedown(struct drm_device *);
1167
1168/* nv04_timer.c */
1169extern int nv04_timer_init(struct drm_device *);
1170extern uint64_t nv04_timer_read(struct drm_device *);
1171extern void nv04_timer_takedown(struct drm_device *);
1172
1173extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1174 unsigned long arg);
1175
1176/* nv04_dac.c */
8f1a6086 1177extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1178extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1179extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1180extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1181extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1182
1183/* nv04_dfp.c */
8f1a6086 1184extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1185extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1186extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1187 int head, bool dl);
1188extern void nv04_dfp_disable(struct drm_device *dev, int head);
1189extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1190
1191/* nv04_tv.c */
1192extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1193extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1194
1195/* nv17_tv.c */
8f1a6086 1196extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1197
1198/* nv04_display.c */
c88c2e06
FJ		 1199extern int nv04_display_early_init(struct drm_device *);
1200extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1201extern int nv04_display_create(struct drm_device *);
c88c2e06 1202extern int nv04_display_init(struct drm_device *);
6ee73861 1203extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1204
1205/* nv04_crtc.c */
1206extern int nv04_crtc_create(struct drm_device *, int index);
1207
1208/* nouveau_bo.c */
1209extern struct ttm_bo_driver nouveau_bo_driver;
1210extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1211 int size, int align, uint32_t flags,
1212 uint32_t tile_mode, uint32_t tile_flags,
1213 bool no_vm, bool mappable, struct nouveau_bo **);
1214extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1215extern int nouveau_bo_unpin(struct nouveau_bo *);
1216extern int nouveau_bo_map(struct nouveau_bo *);
1217extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1218extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1219 uint32_t busy);
6ee73861
BS		 1220extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1221extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1222extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1223extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1224
1225/* nouveau_fence.c */
1226struct nouveau_fence;
0c6c1c2f
FJ		 1227extern int nouveau_fence_init(struct drm_device *);
1228extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1229extern int nouveau_fence_channel_init(struct nouveau_channel *);
1230extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1231extern void nouveau_fence_update(struct nouveau_channel *);
1232extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1233 bool emit);
1234extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1235extern void nouveau_fence_work(struct nouveau_fence *fence,
1236 void (*work)(void *priv, bool signalled),
1237 void *priv);
6ee73861
BS		 1238struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1239extern bool nouveau_fence_signalled(void *obj, void *arg);
1240extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
2730723b 1241extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
6ee73861
BS		 1242extern int nouveau_fence_flush(void *obj, void *arg);
1243extern void nouveau_fence_unref(void **obj);
1244extern void *nouveau_fence_ref(void *obj);
6ee73861
BS		 1245
1246/* nouveau_gem.c */
1247extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1248 int size, int align, uint32_t flags,
1249 uint32_t tile_mode, uint32_t tile_flags,
1250 bool no_vm, bool mappable, struct nouveau_bo **);
1251extern int nouveau_gem_object_new(struct drm_gem_object *);
1252extern void nouveau_gem_object_del(struct drm_gem_object *);
1253extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1254 struct drm_file *);
1255extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1256 struct drm_file *);
6ee73861
BS		 1257extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1258 struct drm_file *);
1259extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1260 struct drm_file *);
1261extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1262 struct drm_file *);
1263
ee2e0131
BS		 1264/* nv10_gpio.c */
1265int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1266int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1267
45284162 1268/* nv50_gpio.c */
ee2e0131 1269int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1270int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1271int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1272void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1273
e9ebb68b
BS		 1274/* nv50_calc. */
1275int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1276 int *N1, int *M1, int *N2, int *M2, int *P);
1277int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1278 int clk, int *N, int *fN, int *M, int *P);
1279
6ee73861
BS		 1280#ifndef ioread32_native
1281#ifdef __BIG_ENDIAN
1282#define ioread16_native ioread16be
1283#define iowrite16_native iowrite16be
1284#define ioread32_native ioread32be
1285#define iowrite32_native iowrite32be
1286#else /* def __BIG_ENDIAN */
1287#define ioread16_native ioread16
1288#define iowrite16_native iowrite16
1289#define ioread32_native ioread32
1290#define iowrite32_native iowrite32
1291#endif /* def __BIG_ENDIAN else */
1292#endif /* !ioread32_native */
1293
1294/* channel control reg access */
1295static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1296{
1297 return ioread32_native(chan->user + reg);
1298}
1299
1300static inline void nvchan_wr32(struct nouveau_channel *chan,
1301 unsigned reg, u32 val)
1302{
1303 iowrite32_native(val, chan->user + reg);
1304}
1305
1306/* register access */
1307static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1308{
1309 struct drm_nouveau_private *dev_priv = dev->dev_private;
1310 return ioread32_native(dev_priv->mmio + reg);
1311}
1312
1313static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1314{
1315 struct drm_nouveau_private *dev_priv = dev->dev_private;
1316 iowrite32_native(val, dev_priv->mmio + reg);
1317}
1318
2a7fdb2b 1319static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1320{
1321 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1322 nv_wr32(dev, reg, (tmp & ~mask) | val);
1323 return tmp;
49eed80a
BS		 1324}
1325
6ee73861
BS		 1326static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1327{
1328 struct drm_nouveau_private *dev_priv = dev->dev_private;
1329 return ioread8(dev_priv->mmio + reg);
1330}
1331
1332static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1333{
1334 struct drm_nouveau_private *dev_priv = dev->dev_private;
1335 iowrite8(val, dev_priv->mmio + reg);
1336}
1337
4b5c152a 1338#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1339 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1340
1341/* PRAMIN access */
1342static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1343{
1344 struct drm_nouveau_private *dev_priv = dev->dev_private;
1345 return ioread32_native(dev_priv->ramin + offset);
1346}
1347
1348static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1349{
1350 struct drm_nouveau_private *dev_priv = dev->dev_private;
1351 iowrite32_native(val, dev_priv->ramin + offset);
1352}
1353
1354/* object access */
b3beb167
BS		 1355extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1356extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1357
1358/*
1359 * Logging
1360 * Argument d is (struct drm_device *).
1361 */
1362#define NV_PRINTK(level, d, fmt, arg...) \
1363 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1364 pci_name(d->pdev), ##arg)
1365#ifndef NV_DEBUG_NOTRACE
1366#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1367 if (drm_debug & DRM_UT_DRIVER) { \
1368 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1369 __LINE__, ##arg); \
1370 } \
1371} while (0)
1372#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1373 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1374 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1375 __LINE__, ##arg); \
1376 } \
1377} while (0)
1378#else
1379#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1380 if (drm_debug & DRM_UT_DRIVER) \
1381 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1382} while (0)
1383#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1384 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1385 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1386} while (0)
1387#endif
1388#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1389#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1390#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1391#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1392#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1393
1394/* nouveau_reg_debug bitmask */
1395enum {
1396 NOUVEAU_REG_DEBUG_MC = 0x1,
1397 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1398 NOUVEAU_REG_DEBUG_FB = 0x4,
1399 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1400 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1401 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1402 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1403 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1404 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1405 NOUVEAU_REG_DEBUG_EVO = 0x200,
1406};
1407
1408#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1409 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1410 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1411} while (0)
1412
1413static inline bool
1414nv_two_heads(struct drm_device *dev)
1415{
1416 struct drm_nouveau_private *dev_priv = dev->dev_private;
1417 const int impl = dev->pci_device & 0x0ff0;
1418
1419 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1420 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1421 return true;
1422
1423 return false;
1424}
1425
1426static inline bool
1427nv_gf4_disp_arch(struct drm_device *dev)
1428{
1429 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1430}
1431
1432static inline bool
1433nv_two_reg_pll(struct drm_device *dev)
1434{
1435 struct drm_nouveau_private *dev_priv = dev->dev_private;
1436 const int impl = dev->pci_device & 0x0ff0;
1437
1438 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1439 return true;
1440 return false;
1441}
1442
acae116c
FJ		 1443static inline bool
1444nv_match_device(struct drm_device *dev, unsigned device,
1445 unsigned sub_vendor, unsigned sub_device)
1446{
1447 return dev->pdev->device == device &&
1448 dev->pdev->subsystem_vendor == sub_vendor &&
1449 dev->pdev->subsystem_device == sub_device;
1450}
1451
f03a314b
FJ		 1452#define NV_SW 0x0000506e
1453#define NV_SW_DMA_SEMAPHORE 0x00000060
1454#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1455#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1456#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1457#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1458#define NV_SW_DMA_VBLSEM 0x0000018c
1459#define NV_SW_VBLSEM_OFFSET 0x00000400
1460#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1461#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1462
1463#endif /* __NOUVEAU_DRV_H__ */
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