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drm/nv50: Keep track of the head a channel is vsync'ing to.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
6ee73861
BS		 99 int pin_refcnt;
100};
101
f13b3263
FJ		 102#define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
104
6ee73861
BS		 105static inline struct nouveau_bo *
106nouveau_bo(struct ttm_buffer_object *bo)
107{
108 return container_of(bo, struct nouveau_bo, bo);
109}
110
111static inline struct nouveau_bo *
112nouveau_gem_object(struct drm_gem_object *gem)
113{
114 return gem ? gem->driver_private : NULL;
115}
116
117/* TODO: submit equivalent to TTM generic API upstream? */
118static inline void __iomem *
119nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120{
121 bool is_iomem;
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
125 return ioptr;
126}
127
6ee73861
BS		 128enum nouveau_flags {
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
131};
132
133#define NVOBJ_ENGINE_SW 0
134#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 135#define NVOBJ_ENGINE_PPP 2
136#define NVOBJ_ENGINE_COPY 3
137#define NVOBJ_ENGINE_VP 4
138#define NVOBJ_ENGINE_CRYPT 5
139#define NVOBJ_ENGINE_BSP 6
50536946 140#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 141#define NVOBJ_ENGINE_INT 0xdeadbeef
142
6ee73861
BS		 143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 145struct nouveau_gpuobj {
b3beb167 146 struct drm_device *dev;
eb9bcbdc 147 struct kref refcount;
6ee73861
BS		 148 struct list_head list;
149
b833ac26 150 struct drm_mm_node *im_pramin;
6ee73861 151 struct nouveau_bo *im_backing;
6ee73861
BS		 152 uint32_t *im_backing_suspend;
153 int im_bound;
154
155 uint32_t flags;
6ee73861 156
43efc9ce 157 u32 size;
de3a6c0a
BS		 158 u32 pinst;
159 u32 cinst;
160 u64 vinst;
161
6ee73861
BS		 162 uint32_t engine;
163 uint32_t class;
164
165 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
166 void *priv;
167};
168
332b242f
FJ		 169struct nouveau_page_flip_state {
170 struct list_head head;
171 struct drm_pending_vblank_event *event;
172 int crtc, bpp, pitch, x, y;
173 uint64_t offset;
174};
175
6ee73861
BS		 176struct nouveau_channel {
177 struct drm_device *dev;
178 int id;
179
f091a3d4
FJ		 180 /* references to the channel data structure */
181 struct kref ref;
182 /* users of the hardware channel resources, the hardware
183 * context will be kicked off when it reaches zero. */
184 atomic_t users;
6a6b73f2
BS		 185 struct mutex mutex;
186
6ee73861
BS		 187 /* owner of this fifo */
188 struct drm_file *file_priv;
189 /* mapping of the fifo itself */
190 struct drm_local_map *map;
191
192 /* mapping of the regs controling the fifo */
193 void __iomem *user;
194 uint32_t user_get;
195 uint32_t user_put;
196
197 /* Fencing */
198 struct {
199 /* lock protects the pending list only */
200 spinlock_t lock;
201 struct list_head pending;
202 uint32_t sequence;
203 uint32_t sequence_ack;
047d1d3c 204 atomic_t last_sequence_irq;
6ee73861
BS		 205 } fence;
206
207 /* DMA push buffer */
a8eaebc6
BS		 208 struct nouveau_gpuobj *pushbuf;
209 struct nouveau_bo *pushbuf_bo;
210 uint32_t pushbuf_base;
6ee73861
BS		 211
212 /* Notifier memory */
213 struct nouveau_bo *notifier_bo;
b833ac26 214 struct drm_mm notifier_heap;
6ee73861
BS		 215
216 /* PFIFO context */
a8eaebc6
BS		 217 struct nouveau_gpuobj *ramfc;
218 struct nouveau_gpuobj *cache;
6ee73861
BS		 219
220 /* PGRAPH context */
221 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 222 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 223 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 224 void *pgraph_ctx;
225
226 /* NV50 VM */
a8eaebc6
BS		 227 struct nouveau_gpuobj *vm_pd;
228 struct nouveau_gpuobj *vm_gart_pt;
229 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 230
231 /* Objects */
a8eaebc6
BS		 232 struct nouveau_gpuobj *ramin; /* Private instmem */
233 struct drm_mm ramin_heap; /* Private PRAMIN heap */
234 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 235
236 /* GPU object info for stuff used in-kernel (mm_enabled) */
237 uint32_t m2mf_ntfy;
238 uint32_t vram_handle;
239 uint32_t gart_handle;
240 bool accel_done;
241
242 /* Push buffer state (only for drm's channel on !mm_enabled) */
243 struct {
244 int max;
245 int free;
246 int cur;
247 int put;
248 /* access via pushbuf_bo */
9a391ad8
BS		 249
250 int ib_base;
251 int ib_max;
252 int ib_free;
253 int ib_put;
6ee73861
BS		 254 } dma;
255
256 uint32_t sw_subchannel[8];
257
258 struct {
259 struct nouveau_gpuobj *vblsem;
1f6d2de2 260 uint32_t vblsem_head;
6ee73861
BS		 261 uint32_t vblsem_offset;
262 uint32_t vblsem_rval;
263 struct list_head vbl_wait;
332b242f 264 struct list_head flip;
6ee73861
BS		 265 } nvsw;
266
267 struct {
268 bool active;
269 char name[32];
270 struct drm_info_list info;
271 } debugfs;
272};
273
274struct nouveau_instmem_engine {
275 void *priv;
276
277 int (*init)(struct drm_device *dev);
278 void (*takedown)(struct drm_device *dev);
279 int (*suspend)(struct drm_device *dev);
280 void (*resume)(struct drm_device *dev);
281
282 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
9100468d 283 u32 *size, u32 align);
6ee73861
BS		 284 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
285 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
286 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 287 void (*flush)(struct drm_device *);
6ee73861
BS		 288};
289
290struct nouveau_mc_engine {
291 int (*init)(struct drm_device *dev);
292 void (*takedown)(struct drm_device *dev);
293};
294
295struct nouveau_timer_engine {
296 int (*init)(struct drm_device *dev);
297 void (*takedown)(struct drm_device *dev);
298 uint64_t (*read)(struct drm_device *dev);
299};
300
301struct nouveau_fb_engine {
cb00f7c1
FJ		 302 int num_tiles;
303
6ee73861
BS		 304 int (*init)(struct drm_device *dev);
305 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 306
307 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
308 uint32_t size, uint32_t pitch);
6ee73861
BS		 309};
310
311struct nouveau_fifo_engine {
6ee73861
BS		 312 int channels;
313
a8eaebc6 314 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 315 int cur_playlist;
316
6ee73861
BS		 317 int (*init)(struct drm_device *);
318 void (*takedown)(struct drm_device *);
319
320 void (*disable)(struct drm_device *);
321 void (*enable)(struct drm_device *);
322 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 323 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 324
325 int (*channel_id)(struct drm_device *);
326
327 int (*create_context)(struct nouveau_channel *);
328 void (*destroy_context)(struct nouveau_channel *);
329 int (*load_context)(struct nouveau_channel *);
330 int (*unload_context)(struct drm_device *);
56ac7475 331 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 332};
333
6ee73861 334struct nouveau_pgraph_engine {
6ee73861 335 bool accel_blocked;
b8c157d3 336 bool registered;
054b93e4 337 int grctx_size;
6ee73861 338
c50a5681 339 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 340 struct nouveau_gpuobj *ctx_table;
c50a5681 341
6ee73861
BS		 342 int (*init)(struct drm_device *);
343 void (*takedown)(struct drm_device *);
344
345 void (*fifo_access)(struct drm_device *, bool);
346
347 struct nouveau_channel *(*channel)(struct drm_device *);
348 int (*create_context)(struct nouveau_channel *);
349 void (*destroy_context)(struct nouveau_channel *);
350 int (*load_context)(struct nouveau_channel *);
351 int (*unload_context)(struct drm_device *);
56ac7475 352 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1
FJ		 353
354 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
355 uint32_t size, uint32_t pitch);
6ee73861
BS		 356};
357
c88c2e06
FJ		 358struct nouveau_display_engine {
359 int (*early_init)(struct drm_device *);
360 void (*late_takedown)(struct drm_device *);
361 int (*create)(struct drm_device *);
362 int (*init)(struct drm_device *);
363 void (*destroy)(struct drm_device *);
364};
365
ee2e0131
BS		 366struct nouveau_gpio_engine {
367 int (*init)(struct drm_device *);
368 void (*takedown)(struct drm_device *);
369
370 int (*get)(struct drm_device *, enum dcb_gpio_tag);
371 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
372
373 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
374};
375
330c5988
BS		 376struct nouveau_pm_voltage_level {
377 u8 voltage;
378 u8 vid;
379};
380
381struct nouveau_pm_voltage {
382 bool supported;
383 u8 vid_mask;
384
385 struct nouveau_pm_voltage_level *level;
386 int nr_level;
387};
388
389#define NOUVEAU_PM_MAX_LEVEL 8
390struct nouveau_pm_level {
391 struct device_attribute dev_attr;
392 char name[32];
393 int id;
394
395 u32 core;
396 u32 memory;
397 u32 shader;
398 u32 unk05;
399
400 u8 voltage;
401 u8 fanspeed;
aee582de
BS		 402
403 u16 memscript;
330c5988
BS		 404};
405
34e9d85a
MP		 406struct nouveau_pm_temp_sensor_constants {
407 u16 offset_constant;
408 s16 offset_mult;
409 u16 offset_div;
410 u16 slope_mult;
411 u16 slope_div;
412};
413
414struct nouveau_pm_threshold_temp {
415 s16 critical;
416 s16 down_clock;
417 s16 fan_boost;
418};
419
7760fcb0
RS		 420struct nouveau_pm_memtiming {
421 u32 reg_100220;
422 u32 reg_100224;
423 u32 reg_100228;
424 u32 reg_10022c;
425 u32 reg_100230;
426 u32 reg_100234;
427 u32 reg_100238;
428 u32 reg_10023c;
429};
430
431struct nouveau_pm_memtimings {
432 bool supported;
433 struct nouveau_pm_memtiming *timing;
434 int nr_timing;
435};
436
330c5988
BS		 437struct nouveau_pm_engine {
438 struct nouveau_pm_voltage voltage;
439 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
440 int nr_perflvl;
7760fcb0 441 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 442 struct nouveau_pm_temp_sensor_constants sensor_constants;
443 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 444
445 struct nouveau_pm_level boot;
446 struct nouveau_pm_level *cur;
447
8155cac4 448 struct device *hwmon;
6032649d 449 struct notifier_block acpi_nb;
8155cac4 450
330c5988 451 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 452 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
453 u32 id, int khz);
330c5988
BS		 454 void (*clock_set)(struct drm_device *, void *);
455 int (*voltage_get)(struct drm_device *);
456 int (*voltage_set)(struct drm_device *, int voltage);
457 int (*fanspeed_get)(struct drm_device *);
458 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 459 int (*temp_get)(struct drm_device *);
330c5988
BS		 460};
461
bd2e597d
BS		 462struct nouveau_crypt_engine {
463 bool registered;
464
465 int (*init)(struct drm_device *);
466 void (*takedown)(struct drm_device *);
467 int (*create_context)(struct nouveau_channel *);
468 void (*destroy_context)(struct nouveau_channel *);
469 void (*tlb_flush)(struct drm_device *dev);
470};
471
6ee73861
BS		 472struct nouveau_engine {
473 struct nouveau_instmem_engine instmem;
474 struct nouveau_mc_engine mc;
475 struct nouveau_timer_engine timer;
476 struct nouveau_fb_engine fb;
477 struct nouveau_pgraph_engine graph;
478 struct nouveau_fifo_engine fifo;
c88c2e06 479 struct nouveau_display_engine display;
ee2e0131 480 struct nouveau_gpio_engine gpio;
330c5988 481 struct nouveau_pm_engine pm;
bd2e597d 482 struct nouveau_crypt_engine crypt;
6ee73861
BS		 483};
484
485struct nouveau_pll_vals {
486 union {
487 struct {
488#ifdef __BIG_ENDIAN
489 uint8_t N1, M1, N2, M2;
490#else
491 uint8_t M1, N1, M2, N2;
492#endif
493 };
494 struct {
495 uint16_t NM1, NM2;
496 } __attribute__((packed));
497 };
498 int log2P;
499
500 int refclk;
501};
502
503enum nv04_fp_display_regs {
504 FP_DISPLAY_END,
505 FP_TOTAL,
506 FP_CRTC,
507 FP_SYNC_START,
508 FP_SYNC_END,
509 FP_VALID_START,
510 FP_VALID_END
511};
512
513struct nv04_crtc_reg {
cbab95db 514 unsigned char MiscOutReg;
4a9f822f 515 uint8_t CRTC[0xa0];
6ee73861
BS		 516 uint8_t CR58[0x10];
517 uint8_t Sequencer[5];
518 uint8_t Graphics[9];
519 uint8_t Attribute[21];
cbab95db 520 unsigned char DAC[768];
6ee73861
BS		 521
522 /* PCRTC regs */
523 uint32_t fb_start;
524 uint32_t crtc_cfg;
525 uint32_t cursor_cfg;
526 uint32_t gpio_ext;
527 uint32_t crtc_830;
528 uint32_t crtc_834;
529 uint32_t crtc_850;
530 uint32_t crtc_eng_ctrl;
531
532 /* PRAMDAC regs */
533 uint32_t nv10_cursync;
534 struct nouveau_pll_vals pllvals;
535 uint32_t ramdac_gen_ctrl;
536 uint32_t ramdac_630;
537 uint32_t ramdac_634;
538 uint32_t tv_setup;
539 uint32_t tv_vtotal;
540 uint32_t tv_vskew;
541 uint32_t tv_vsync_delay;
542 uint32_t tv_htotal;
543 uint32_t tv_hskew;
544 uint32_t tv_hsync_delay;
545 uint32_t tv_hsync_delay2;
546 uint32_t fp_horiz_regs[7];
547 uint32_t fp_vert_regs[7];
548 uint32_t dither;
549 uint32_t fp_control;
550 uint32_t dither_regs[6];
551 uint32_t fp_debug_0;
552 uint32_t fp_debug_1;
553 uint32_t fp_debug_2;
554 uint32_t fp_margin_color;
555 uint32_t ramdac_8c0;
556 uint32_t ramdac_a20;
557 uint32_t ramdac_a24;
558 uint32_t ramdac_a34;
559 uint32_t ctv_regs[38];
560};
561
562struct nv04_output_reg {
563 uint32_t output;
564 int head;
565};
566
567struct nv04_mode_state {
cbab95db 568 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 569 uint32_t pllsel;
570 uint32_t sel_clk;
6ee73861
BS		 571};
572
573enum nouveau_card_type {
574 NV_04 = 0x00,
575 NV_10 = 0x10,
576 NV_20 = 0x20,
577 NV_30 = 0x30,
578 NV_40 = 0x40,
579 NV_50 = 0x50,
4b223eef 580 NV_C0 = 0xc0,
6ee73861
BS		 581};
582
583struct drm_nouveau_private {
584 struct drm_device *dev;
6ee73861
BS		 585
586 /* the card type, takes NV_* as values */
587 enum nouveau_card_type card_type;
588 /* exact chipset, derived from NV_PMC_BOOT_0 */
589 int chipset;
590 int flags;
591
592 void __iomem *mmio;
5125bfd8 593
e05d7eae 594 spinlock_t ramin_lock;
6ee73861 595 void __iomem *ramin;
5125bfd8
BS		 596 u32 ramin_size;
597 u32 ramin_base;
598 bool ramin_available;
e05d7eae
BS		 599 struct drm_mm ramin_heap;
600 struct list_head gpuobj_list;
b8c157d3 601 struct list_head classes;
6ee73861 602
ac8fb975
BS		 603 struct nouveau_bo *vga_ram;
604
35fa2f2a
BS		 605 /* interrupt handling */
606 bool msi_enabled;
6ee73861
BS		 607 struct workqueue_struct *wq;
608 struct work_struct irq_work;
a5acac66 609 struct work_struct hpd_work;
6ee73861 610
ab838338
AL		 611 struct {
612 spinlock_t lock;
613 uint32_t hpd0_bits;
614 uint32_t hpd1_bits;
615 } hpd_state;
616
6ee73861
BS		 617 struct list_head vbl_waiting;
618
619 struct {
ba4420c2 620 struct drm_global_reference mem_global_ref;
6ee73861
BS		 621 struct ttm_bo_global_ref bo_global_ref;
622 struct ttm_bo_device bdev;
6ee73861
BS		 623 atomic_t validate_sequence;
624 } ttm;
625
0c6c1c2f
FJ		 626 struct {
627 spinlock_t lock;
628 struct drm_mm heap;
629 struct nouveau_bo *bo;
630 } fence;
631
cff5c133
BS		 632 struct {
633 spinlock_t lock;
634 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
635 } channels;
6ee73861
BS		 636
637 struct nouveau_engine engine;
638 struct nouveau_channel *channel;
639
ff9e5279
MM		 640 /* For PFIFO and PGRAPH. */
641 spinlock_t context_switch_lock;
642
6ee73861 643 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 644 struct nouveau_ramht *ramht;
645 struct nouveau_gpuobj *ramfc;
646 struct nouveau_gpuobj *ramro;
647
6ee73861 648 uint32_t ramin_rsvd_vram;
6ee73861 649
6ee73861
BS		 650 struct {
651 enum {
652 NOUVEAU_GART_NONE = 0,
653 NOUVEAU_GART_AGP,
654 NOUVEAU_GART_SGDMA
655 } type;
656 uint64_t aper_base;
657 uint64_t aper_size;
658 uint64_t aper_free;
659
660 struct nouveau_gpuobj *sg_ctxdma;
661 struct page *sg_dummy_page;
662 dma_addr_t sg_dummy_bus;
6ee73861
BS		 663 } gart_info;
664
a0af9add 665 /* nv10-nv40 tiling regions */
9f56b126 666 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 667
a76fb4e8
BS		 668 /* VRAM/fb configuration */
669 uint64_t vram_size;
670 uint64_t vram_sys_base;
6c3d7ef2 671 u32 vram_rblock_size;
a76fb4e8
BS		 672
673 uint64_t fb_phys;
674 uint64_t fb_available_size;
675 uint64_t fb_mappable_pages;
676 uint64_t fb_aper_free;
677 int fb_mtrr;
678
6ee73861
BS		 679 /* G8x/G9x virtual address space */
680 uint64_t vm_gart_base;
681 uint64_t vm_gart_size;
682 uint64_t vm_vram_base;
683 uint64_t vm_vram_size;
684 uint64_t vm_end;
685 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
686 int vm_vram_pt_nr;
6ee73861 687
04a39c57 688 struct nvbios vbios;
6ee73861
BS		 689
690 struct nv04_mode_state mode_reg;
691 struct nv04_mode_state saved_reg;
692 uint32_t saved_vga_font[4][16384];
693 uint32_t crtc_owner;
694 uint32_t dac_users[4];
695
696 struct nouveau_suspend_resume {
6ee73861 697 uint32_t *ramin_copy;
6ee73861
BS		 698 } susres;
699
700 struct backlight_device *backlight;
6ee73861
BS		 701
702 struct nouveau_channel *evo;
1e96268a 703 u32 evo_alloc;
87c0e0e5
BS		 704 struct {
705 struct dcb_entry *dcb;
706 u16 script;
707 u32 pclk;
708 } evo_irq;
6ee73861
BS		 709
710 struct {
711 struct dentry *channel_root;
712 } debugfs;
38651674 713
8be48d92 714 struct nouveau_fbdev *nfbdev;
06415c56 715 struct apertures_struct *apertures;
6ee73861
BS		 716};
717
2730723b
FJ		 718static inline struct drm_nouveau_private *
719nouveau_private(struct drm_device *dev)
720{
721 return dev->dev_private;
722}
723
6ee73861
BS		 724static inline struct drm_nouveau_private *
725nouveau_bdev(struct ttm_bo_device *bd)
726{
727 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
728}
729
730static inline int
731nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
732{
733 struct nouveau_bo *prev;
734
735 if (!pnvbo)
736 return -EINVAL;
737 prev = *pnvbo;
738
739 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
740 if (prev) {
741 struct ttm_buffer_object *bo = &prev->bo;
742
743 ttm_bo_unref(&bo);
744 }
745
746 return 0;
747}
748
6ee73861 749/* nouveau_drv.c */
de5899bd 750extern int nouveau_agpmode;
6ee73861
BS		 751extern int nouveau_duallink;
752extern int nouveau_uscript_lvds;
753extern int nouveau_uscript_tmds;
754extern int nouveau_vram_pushbuf;
755extern int nouveau_vram_notify;
756extern int nouveau_fbpercrtc;
f4053509 757extern int nouveau_tv_disable;
6ee73861
BS		 758extern char *nouveau_tv_norm;
759extern int nouveau_reg_debug;
760extern char *nouveau_vbios;
a1470890 761extern int nouveau_ignorelid;
a32ed69d
MK		 762extern int nouveau_nofbaccel;
763extern int nouveau_noaccel;
0cba1b76 764extern int nouveau_force_post;
da647d5b 765extern int nouveau_override_conntype;
6f876986
BS		 766extern char *nouveau_perflvl;
767extern int nouveau_perflvl_wr;
35fa2f2a 768extern int nouveau_msi;
6ee73861 769
6a9ee8af
DA		 770extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
771extern int nouveau_pci_resume(struct pci_dev *pdev);
772
6ee73861
BS		 773/* nouveau_state.c */
774extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
775extern int nouveau_load(struct drm_device *, unsigned long flags);
776extern int nouveau_firstopen(struct drm_device *);
777extern void nouveau_lastclose(struct drm_device *);
778extern int nouveau_unload(struct drm_device *);
779extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
780 struct drm_file *);
781extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
782 struct drm_file *);
783extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
784 uint32_t reg, uint32_t mask, uint32_t val);
785extern bool nouveau_wait_for_idle(struct drm_device *);
786extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 787
788/* nouveau_mem.c */
fbd2895e
BS		 789extern int nouveau_mem_vram_init(struct drm_device *);
790extern void nouveau_mem_vram_fini(struct drm_device *);
791extern int nouveau_mem_gart_init(struct drm_device *);
792extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 793extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 794extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 795extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 796extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
797 uint32_t addr,
798 uint32_t size,
799 uint32_t pitch);
800extern void nv10_mem_expire_tiling(struct drm_device *dev,
801 struct nouveau_tile_reg *tile,
802 struct nouveau_fence *fence);
6ee73861
BS		 803extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
804 uint32_t size, uint32_t flags,
805 uint64_t phys);
806extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
807 uint32_t size);
808
809/* nouveau_notifier.c */
810extern int nouveau_notifier_init_channel(struct nouveau_channel *);
811extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
812extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
813 int cout, uint32_t *offset);
814extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
815extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
816 struct drm_file *);
817extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
818 struct drm_file *);
819
820/* nouveau_channel.c */
821extern struct drm_ioctl_desc nouveau_ioctls[];
822extern int nouveau_max_ioctl;
823extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 824extern int nouveau_channel_alloc(struct drm_device *dev,
825 struct nouveau_channel **chan,
826 struct drm_file *file_priv,
827 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 828extern struct nouveau_channel *
feeb0aec
FJ		 829nouveau_channel_get_unlocked(struct nouveau_channel *);
830extern struct nouveau_channel *
cff5c133 831nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 832extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 833extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 834extern void nouveau_channel_ref(struct nouveau_channel *chan,
835 struct nouveau_channel **pchan);
6ee73861
BS		 836
837/* nouveau_object.c */
b8c157d3
BS		 838#define NVOBJ_CLASS(d,c,e) do { \
839 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
840 if (ret) \
841 return ret; \
842} while(0)
843
844#define NVOBJ_MTHD(d,c,m,e) do { \
845 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
846 if (ret) \
847 return ret; \
848} while(0)
849
6ee73861
BS		 850extern int nouveau_gpuobj_early_init(struct drm_device *);
851extern int nouveau_gpuobj_init(struct drm_device *);
852extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 853extern int nouveau_gpuobj_suspend(struct drm_device *dev);
854extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
855extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 856extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
857extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
858 int (*exec)(struct nouveau_channel *,
859 u32 class, u32 mthd, u32 data));
860extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
6ee73861
BS		 861extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
862 uint32_t vram_h, uint32_t tt_h);
863extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
864extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
865 uint32_t size, int align, uint32_t flags,
866 struct nouveau_gpuobj **);
a8eaebc6
BS		 867extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
868 struct nouveau_gpuobj **);
43efc9ce
BS		 869extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
870 u32 size, u32 flags,
a8eaebc6 871 struct nouveau_gpuobj **);
6ee73861
BS		 872extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
873 uint64_t offset, uint64_t size, int access,
874 int target, struct nouveau_gpuobj **);
875extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
876 uint64_t offset, uint64_t size,
877 int access, struct nouveau_gpuobj **,
878 uint32_t *o_ret);
879extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
880 struct nouveau_gpuobj **);
881extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
882 struct drm_file *);
883extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
884 struct drm_file *);
885
886/* nouveau_irq.c */
35fa2f2a
BS		 887extern int nouveau_irq_init(struct drm_device *);
888extern void nouveau_irq_fini(struct drm_device *);
6ee73861
BS		 889extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
890extern void nouveau_irq_preinstall(struct drm_device *);
891extern int nouveau_irq_postinstall(struct drm_device *);
892extern void nouveau_irq_uninstall(struct drm_device *);
893
894/* nouveau_sgdma.c */
895extern int nouveau_sgdma_init(struct drm_device *);
896extern void nouveau_sgdma_takedown(struct drm_device *);
897extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
898 uint32_t *page);
899extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
900
901/* nouveau_debugfs.c */
902#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
903extern int nouveau_debugfs_init(struct drm_minor *);
904extern void nouveau_debugfs_takedown(struct drm_minor *);
905extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
906extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
907#else
908static inline int
909nouveau_debugfs_init(struct drm_minor *minor)
910{
911 return 0;
912}
913
914static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
915{
916}
917
918static inline int
919nouveau_debugfs_channel_init(struct nouveau_channel *chan)
920{
921 return 0;
922}
923
924static inline void
925nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
926{
927}
928#endif
929
930/* nouveau_dma.c */
75c99da6 931extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 932extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 933extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 934
935/* nouveau_acpi.c */
afeb3e11 936#define ROM_BIOS_PAGE 4096
2f41a7f1 937#if defined(CONFIG_ACPI)
6a9ee8af
DA		 938void nouveau_register_dsm_handler(void);
939void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 940int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
941bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 942int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 943#else
944static inline void nouveau_register_dsm_handler(void) {}
945static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 946static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
947static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 948static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 949#endif
6ee73861
BS		 950
951/* nouveau_backlight.c */
952#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
953extern int nouveau_backlight_init(struct drm_device *);
954extern void nouveau_backlight_exit(struct drm_device *);
955#else
956static inline int nouveau_backlight_init(struct drm_device *dev)
957{
958 return 0;
959}
960
961static inline void nouveau_backlight_exit(struct drm_device *dev) { }
962#endif
963
964/* nouveau_bios.c */
965extern int nouveau_bios_init(struct drm_device *);
966extern void nouveau_bios_takedown(struct drm_device *dev);
967extern int nouveau_run_vbios_init(struct drm_device *);
968extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
969 struct dcb_entry *);
970extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
971 enum dcb_gpio_tag);
972extern struct dcb_connector_table_entry *
973nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 974extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 975extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
976 struct pll_lims *);
977extern int nouveau_bios_run_display_table(struct drm_device *,
978 struct dcb_entry *,
979 uint32_t script, int pxclk);
980extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
981 int *length);
982extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
983extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
984extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
985 bool *dl, bool *if_is_24bit);
986extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
987 int head, int pxclk);
988extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
989 enum LVDS_script, int pxclk);
990
991/* nouveau_ttm.c */
992int nouveau_ttm_global_init(struct drm_nouveau_private *);
993void nouveau_ttm_global_release(struct drm_nouveau_private *);
994int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
995
996/* nouveau_dp.c */
997int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
998 uint8_t *data, int data_nr);
999bool nouveau_dp_detect(struct drm_encoder *);
1000bool nouveau_dp_link_train(struct drm_encoder *);
1001
1002/* nv04_fb.c */
1003extern int nv04_fb_init(struct drm_device *);
1004extern void nv04_fb_takedown(struct drm_device *);
1005
1006/* nv10_fb.c */
1007extern int nv10_fb_init(struct drm_device *);
1008extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 1009extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
1010 uint32_t, uint32_t);
6ee73861 1011
8bded189
FJ		 1012/* nv30_fb.c */
1013extern int nv30_fb_init(struct drm_device *);
1014extern void nv30_fb_takedown(struct drm_device *);
1015
6ee73861
BS		 1016/* nv40_fb.c */
1017extern int nv40_fb_init(struct drm_device *);
1018extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 1019extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
1020 uint32_t, uint32_t);
304424e1
MK		 1021/* nv50_fb.c */
1022extern int nv50_fb_init(struct drm_device *);
1023extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1024extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1025
4b223eef
BS		 1026/* nvc0_fb.c */
1027extern int nvc0_fb_init(struct drm_device *);
1028extern void nvc0_fb_takedown(struct drm_device *);
1029
6ee73861
BS		 1030/* nv04_fifo.c */
1031extern int nv04_fifo_init(struct drm_device *);
1032extern void nv04_fifo_disable(struct drm_device *);
1033extern void nv04_fifo_enable(struct drm_device *);
1034extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1035extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1036extern int nv04_fifo_channel_id(struct drm_device *);
1037extern int nv04_fifo_create_context(struct nouveau_channel *);
1038extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1039extern int nv04_fifo_load_context(struct nouveau_channel *);
1040extern int nv04_fifo_unload_context(struct drm_device *);
1041
1042/* nv10_fifo.c */
1043extern int nv10_fifo_init(struct drm_device *);
1044extern int nv10_fifo_channel_id(struct drm_device *);
1045extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1046extern int nv10_fifo_load_context(struct nouveau_channel *);
1047extern int nv10_fifo_unload_context(struct drm_device *);
1048
1049/* nv40_fifo.c */
1050extern int nv40_fifo_init(struct drm_device *);
1051extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1052extern int nv40_fifo_load_context(struct nouveau_channel *);
1053extern int nv40_fifo_unload_context(struct drm_device *);
1054
1055/* nv50_fifo.c */
1056extern int nv50_fifo_init(struct drm_device *);
1057extern void nv50_fifo_takedown(struct drm_device *);
1058extern int nv50_fifo_channel_id(struct drm_device *);
1059extern int nv50_fifo_create_context(struct nouveau_channel *);
1060extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1061extern int nv50_fifo_load_context(struct nouveau_channel *);
1062extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1063extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1064
4b223eef
BS		 1065/* nvc0_fifo.c */
1066extern int nvc0_fifo_init(struct drm_device *);
1067extern void nvc0_fifo_takedown(struct drm_device *);
1068extern void nvc0_fifo_disable(struct drm_device *);
1069extern void nvc0_fifo_enable(struct drm_device *);
1070extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1071extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1072extern int nvc0_fifo_channel_id(struct drm_device *);
1073extern int nvc0_fifo_create_context(struct nouveau_channel *);
1074extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1075extern int nvc0_fifo_load_context(struct nouveau_channel *);
1076extern int nvc0_fifo_unload_context(struct drm_device *);
1077
6ee73861 1078/* nv04_graph.c */
6ee73861
BS		 1079extern int nv04_graph_init(struct drm_device *);
1080extern void nv04_graph_takedown(struct drm_device *);
1081extern void nv04_graph_fifo_access(struct drm_device *, bool);
1082extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1083extern int nv04_graph_create_context(struct nouveau_channel *);
1084extern void nv04_graph_destroy_context(struct nouveau_channel *);
1085extern int nv04_graph_load_context(struct nouveau_channel *);
1086extern int nv04_graph_unload_context(struct drm_device *);
1087extern void nv04_graph_context_switch(struct drm_device *);
332b242f
FJ		 1088extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1089 u32 class, u32 mthd, u32 data);
6ee73861
BS		 1090
1091/* nv10_graph.c */
6ee73861
BS		 1092extern int nv10_graph_init(struct drm_device *);
1093extern void nv10_graph_takedown(struct drm_device *);
1094extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1095extern int nv10_graph_create_context(struct nouveau_channel *);
1096extern void nv10_graph_destroy_context(struct nouveau_channel *);
1097extern int nv10_graph_load_context(struct nouveau_channel *);
1098extern int nv10_graph_unload_context(struct drm_device *);
1099extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1100extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1101 uint32_t, uint32_t);
6ee73861
BS		 1102
1103/* nv20_graph.c */
6ee73861
BS		 1104extern int nv20_graph_create_context(struct nouveau_channel *);
1105extern void nv20_graph_destroy_context(struct nouveau_channel *);
1106extern int nv20_graph_load_context(struct nouveau_channel *);
1107extern int nv20_graph_unload_context(struct drm_device *);
1108extern int nv20_graph_init(struct drm_device *);
1109extern void nv20_graph_takedown(struct drm_device *);
1110extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1111extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1112 uint32_t, uint32_t);
6ee73861
BS		 1113
1114/* nv40_graph.c */
6ee73861
BS		 1115extern int nv40_graph_init(struct drm_device *);
1116extern void nv40_graph_takedown(struct drm_device *);
1117extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1118extern int nv40_graph_create_context(struct nouveau_channel *);
1119extern void nv40_graph_destroy_context(struct nouveau_channel *);
1120extern int nv40_graph_load_context(struct nouveau_channel *);
1121extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1122extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1123extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1124 uint32_t, uint32_t);
6ee73861
BS		 1125
1126/* nv50_graph.c */
6ee73861
BS		 1127extern int nv50_graph_init(struct drm_device *);
1128extern void nv50_graph_takedown(struct drm_device *);
1129extern void nv50_graph_fifo_access(struct drm_device *, bool);
1130extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1131extern int nv50_graph_create_context(struct nouveau_channel *);
1132extern void nv50_graph_destroy_context(struct nouveau_channel *);
1133extern int nv50_graph_load_context(struct nouveau_channel *);
1134extern int nv50_graph_unload_context(struct drm_device *);
1135extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1136extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1137extern void nv50_graph_tlb_flush(struct drm_device *dev);
1138extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1139
4b223eef
BS		 1140/* nvc0_graph.c */
1141extern int nvc0_graph_init(struct drm_device *);
1142extern void nvc0_graph_takedown(struct drm_device *);
1143extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1144extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1145extern int nvc0_graph_create_context(struct nouveau_channel *);
1146extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1147extern int nvc0_graph_load_context(struct nouveau_channel *);
1148extern int nvc0_graph_unload_context(struct drm_device *);
1149
bd2e597d
BS		 1150/* nv84_crypt.c */
1151extern int nv84_crypt_init(struct drm_device *dev);
1152extern void nv84_crypt_fini(struct drm_device *dev);
1153extern int nv84_crypt_create_context(struct nouveau_channel *);
1154extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1155extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1156
6ee73861
BS		 1157/* nv04_instmem.c */
1158extern int nv04_instmem_init(struct drm_device *);
1159extern void nv04_instmem_takedown(struct drm_device *);
1160extern int nv04_instmem_suspend(struct drm_device *);
1161extern void nv04_instmem_resume(struct drm_device *);
1162extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1163 u32 *size, u32 align);
6ee73861
BS		 1164extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1165extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1166extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1167extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1168
1169/* nv50_instmem.c */
1170extern int nv50_instmem_init(struct drm_device *);
1171extern void nv50_instmem_takedown(struct drm_device *);
1172extern int nv50_instmem_suspend(struct drm_device *);
1173extern void nv50_instmem_resume(struct drm_device *);
1174extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1175 u32 *size, u32 align);
6ee73861
BS		 1176extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1177extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1178extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1179extern void nv50_instmem_flush(struct drm_device *);
734ee835 1180extern void nv84_instmem_flush(struct drm_device *);
63187215 1181extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1182
4b223eef
BS		 1183/* nvc0_instmem.c */
1184extern int nvc0_instmem_init(struct drm_device *);
1185extern void nvc0_instmem_takedown(struct drm_device *);
1186extern int nvc0_instmem_suspend(struct drm_device *);
1187extern void nvc0_instmem_resume(struct drm_device *);
1188extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1189 u32 *size, u32 align);
4b223eef
BS		 1190extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1191extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1192extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1193extern void nvc0_instmem_flush(struct drm_device *);
1194
6ee73861
BS		 1195/* nv04_mc.c */
1196extern int nv04_mc_init(struct drm_device *);
1197extern void nv04_mc_takedown(struct drm_device *);
1198
1199/* nv40_mc.c */
1200extern int nv40_mc_init(struct drm_device *);
1201extern void nv40_mc_takedown(struct drm_device *);
1202
1203/* nv50_mc.c */
1204extern int nv50_mc_init(struct drm_device *);
1205extern void nv50_mc_takedown(struct drm_device *);
1206
1207/* nv04_timer.c */
1208extern int nv04_timer_init(struct drm_device *);
1209extern uint64_t nv04_timer_read(struct drm_device *);
1210extern void nv04_timer_takedown(struct drm_device *);
1211
1212extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1213 unsigned long arg);
1214
1215/* nv04_dac.c */
8f1a6086 1216extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1217extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1218extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1219extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1220extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1221
1222/* nv04_dfp.c */
8f1a6086 1223extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1224extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1225extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1226 int head, bool dl);
1227extern void nv04_dfp_disable(struct drm_device *dev, int head);
1228extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1229
1230/* nv04_tv.c */
1231extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1232extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1233
1234/* nv17_tv.c */
8f1a6086 1235extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1236
1237/* nv04_display.c */
c88c2e06
FJ		 1238extern int nv04_display_early_init(struct drm_device *);
1239extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1240extern int nv04_display_create(struct drm_device *);
c88c2e06 1241extern int nv04_display_init(struct drm_device *);
6ee73861 1242extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1243
1244/* nv04_crtc.c */
1245extern int nv04_crtc_create(struct drm_device *, int index);
1246
1247/* nouveau_bo.c */
1248extern struct ttm_bo_driver nouveau_bo_driver;
1249extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1250 int size, int align, uint32_t flags,
1251 uint32_t tile_mode, uint32_t tile_flags,
1252 bool no_vm, bool mappable, struct nouveau_bo **);
1253extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1254extern int nouveau_bo_unpin(struct nouveau_bo *);
1255extern int nouveau_bo_map(struct nouveau_bo *);
1256extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1257extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1258 uint32_t busy);
6ee73861
BS		 1259extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1260extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1261extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1262extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1263extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
6ee73861
BS		 1264
1265/* nouveau_fence.c */
1266struct nouveau_fence;
0c6c1c2f
FJ		 1267extern int nouveau_fence_init(struct drm_device *);
1268extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1269extern int nouveau_fence_channel_init(struct nouveau_channel *);
1270extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1271extern void nouveau_fence_update(struct nouveau_channel *);
1272extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1273 bool emit);
1274extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1275extern void nouveau_fence_work(struct nouveau_fence *fence,
1276 void (*work)(void *priv, bool signalled),
1277 void *priv);
6ee73861 1278struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1279
1280extern bool __nouveau_fence_signalled(void *obj, void *arg);
1281extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1282extern int __nouveau_fence_flush(void *obj, void *arg);
1283extern void __nouveau_fence_unref(void **obj);
1284extern void *__nouveau_fence_ref(void *obj);
1285
1286static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1287{
1288 return __nouveau_fence_signalled(obj, NULL);
1289}
1290static inline int
1291nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1292{
1293 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1294}
2730723b 1295extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1296static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1297{
1298 return __nouveau_fence_flush(obj, NULL);
1299}
1300static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1301{
1302 __nouveau_fence_unref((void **)obj);
1303}
1304static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1305{
1306 return __nouveau_fence_ref(obj);
1307}
6ee73861
BS		 1308
1309/* nouveau_gem.c */
1310extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1311 int size, int align, uint32_t flags,
1312 uint32_t tile_mode, uint32_t tile_flags,
1313 bool no_vm, bool mappable, struct nouveau_bo **);
1314extern int nouveau_gem_object_new(struct drm_gem_object *);
1315extern void nouveau_gem_object_del(struct drm_gem_object *);
1316extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1317 struct drm_file *);
1318extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1319 struct drm_file *);
6ee73861
BS		 1320extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1321 struct drm_file *);
1322extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1323 struct drm_file *);
1324extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1325 struct drm_file *);
1326
042206c0
FJ		 1327/* nouveau_display.c */
1328int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1329void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1330int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1331 struct drm_pending_vblank_event *event);
1332int nouveau_finish_page_flip(struct nouveau_channel *,
1333 struct nouveau_page_flip_state *);
042206c0 1334
ee2e0131
BS		 1335/* nv10_gpio.c */
1336int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1337int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1338
45284162 1339/* nv50_gpio.c */
ee2e0131 1340int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1341int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1342int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1343void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1344
e9ebb68b
BS		 1345/* nv50_calc. */
1346int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1347 int *N1, int *M1, int *N2, int *M2, int *P);
1348int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1349 int clk, int *N, int *fN, int *M, int *P);
1350
6ee73861
BS		 1351#ifndef ioread32_native
1352#ifdef __BIG_ENDIAN
1353#define ioread16_native ioread16be
1354#define iowrite16_native iowrite16be
1355#define ioread32_native ioread32be
1356#define iowrite32_native iowrite32be
1357#else /* def __BIG_ENDIAN */
1358#define ioread16_native ioread16
1359#define iowrite16_native iowrite16
1360#define ioread32_native ioread32
1361#define iowrite32_native iowrite32
1362#endif /* def __BIG_ENDIAN else */
1363#endif /* !ioread32_native */
1364
1365/* channel control reg access */
1366static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1367{
1368 return ioread32_native(chan->user + reg);
1369}
1370
1371static inline void nvchan_wr32(struct nouveau_channel *chan,
1372 unsigned reg, u32 val)
1373{
1374 iowrite32_native(val, chan->user + reg);
1375}
1376
1377/* register access */
1378static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1379{
1380 struct drm_nouveau_private *dev_priv = dev->dev_private;
1381 return ioread32_native(dev_priv->mmio + reg);
1382}
1383
1384static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1385{
1386 struct drm_nouveau_private *dev_priv = dev->dev_private;
1387 iowrite32_native(val, dev_priv->mmio + reg);
1388}
1389
2a7fdb2b 1390static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1391{
1392 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1393 nv_wr32(dev, reg, (tmp & ~mask) | val);
1394 return tmp;
49eed80a
BS		 1395}
1396
6ee73861
BS		 1397static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1398{
1399 struct drm_nouveau_private *dev_priv = dev->dev_private;
1400 return ioread8(dev_priv->mmio + reg);
1401}
1402
1403static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1404{
1405 struct drm_nouveau_private *dev_priv = dev->dev_private;
1406 iowrite8(val, dev_priv->mmio + reg);
1407}
1408
4b5c152a 1409#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1410 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1411
1412/* PRAMIN access */
1413static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1414{
1415 struct drm_nouveau_private *dev_priv = dev->dev_private;
1416 return ioread32_native(dev_priv->ramin + offset);
1417}
1418
1419static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1420{
1421 struct drm_nouveau_private *dev_priv = dev->dev_private;
1422 iowrite32_native(val, dev_priv->ramin + offset);
1423}
1424
1425/* object access */
b3beb167
BS		 1426extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1427extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1428
1429/*
1430 * Logging
1431 * Argument d is (struct drm_device *).
1432 */
1433#define NV_PRINTK(level, d, fmt, arg...) \
1434 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1435 pci_name(d->pdev), ##arg)
1436#ifndef NV_DEBUG_NOTRACE
1437#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1438 if (drm_debug & DRM_UT_DRIVER) { \
1439 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1440 __LINE__, ##arg); \
1441 } \
1442} while (0)
1443#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1444 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1445 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1446 __LINE__, ##arg); \
1447 } \
1448} while (0)
1449#else
1450#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1451 if (drm_debug & DRM_UT_DRIVER) \
1452 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1453} while (0)
1454#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1455 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1456 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1457} while (0)
1458#endif
1459#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1460#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1461#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1462#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1463#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1464
1465/* nouveau_reg_debug bitmask */
1466enum {
1467 NOUVEAU_REG_DEBUG_MC = 0x1,
1468 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1469 NOUVEAU_REG_DEBUG_FB = 0x4,
1470 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1471 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1472 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1473 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1474 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1475 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1476 NOUVEAU_REG_DEBUG_EVO = 0x200,
1477};
1478
1479#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1480 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1481 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1482} while (0)
1483
1484static inline bool
1485nv_two_heads(struct drm_device *dev)
1486{
1487 struct drm_nouveau_private *dev_priv = dev->dev_private;
1488 const int impl = dev->pci_device & 0x0ff0;
1489
1490 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1491 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1492 return true;
1493
1494 return false;
1495}
1496
1497static inline bool
1498nv_gf4_disp_arch(struct drm_device *dev)
1499{
1500 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1501}
1502
1503static inline bool
1504nv_two_reg_pll(struct drm_device *dev)
1505{
1506 struct drm_nouveau_private *dev_priv = dev->dev_private;
1507 const int impl = dev->pci_device & 0x0ff0;
1508
1509 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1510 return true;
1511 return false;
1512}
1513
acae116c
FJ		 1514static inline bool
1515nv_match_device(struct drm_device *dev, unsigned device,
1516 unsigned sub_vendor, unsigned sub_device)
1517{
1518 return dev->pdev->device == device &&
1519 dev->pdev->subsystem_vendor == sub_vendor &&
1520 dev->pdev->subsystem_device == sub_device;
1521}
1522
f03a314b
FJ		 1523#define NV_SW 0x0000506e
1524#define NV_SW_DMA_SEMAPHORE 0x00000060
1525#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1526#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1527#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1528#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1529#define NV_SW_DMA_VBLSEM 0x0000018c
1530#define NV_SW_VBLSEM_OFFSET 0x00000400
1531#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1532#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1533#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1534
1535#endif /* __NOUVEAU_DRV_H__ */
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