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drm/nv50: implement DAC disconnect fix missed in earlier commit
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139#define NVOBJ_FLAG_FAKE (1 << 3)
140struct nouveau_gpuobj {
141 struct list_head list;
142
143 struct nouveau_channel *im_channel;
b833ac26 144 struct drm_mm_node *im_pramin;
6ee73861
BS		 145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151 int refcount;
152
153 uint32_t engine;
154 uint32_t class;
155
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 void *priv;
158};
159
160struct nouveau_gpuobj_ref {
161 struct list_head list;
162
163 struct nouveau_gpuobj *gpuobj;
164 uint32_t instance;
165
166 struct nouveau_channel *channel;
167 int handle;
168};
169
170struct nouveau_channel {
171 struct drm_device *dev;
172 int id;
173
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
178
179 /* mapping of the regs controling the fifo */
180 void __iomem *user;
181 uint32_t user_get;
182 uint32_t user_put;
183
184 /* Fencing */
185 struct {
186 /* lock protects the pending list only */
187 spinlock_t lock;
188 struct list_head pending;
189 uint32_t sequence;
190 uint32_t sequence_ack;
191 uint32_t last_sequence_irq;
192 } fence;
193
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
198
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
b833ac26 201 struct drm_mm notifier_heap;
6ee73861
BS		 202
203 /* PFIFO context */
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
206
207 /* PGRAPH context */
208 /* XXX may be merge 2 pointers as private data ??? */
209 struct nouveau_gpuobj_ref *ramin_grctx;
210 void *pgraph_ctx;
211
212 /* NV50 VM */
213 struct nouveau_gpuobj *vm_pd;
214 struct nouveau_gpuobj_ref *vm_gart_pt;
215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
216
217 /* Objects */
218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
b833ac26 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */
6ee73861
BS		 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */
221 struct list_head ramht_refs; /* Objects referenced by RAMHT */
222
223 /* GPU object info for stuff used in-kernel (mm_enabled) */
224 uint32_t m2mf_ntfy;
225 uint32_t vram_handle;
226 uint32_t gart_handle;
227 bool accel_done;
228
229 /* Push buffer state (only for drm's channel on !mm_enabled) */
230 struct {
231 int max;
232 int free;
233 int cur;
234 int put;
235 /* access via pushbuf_bo */
9a391ad8
BS		 236
237 int ib_base;
238 int ib_max;
239 int ib_free;
240 int ib_put;
6ee73861
BS		 241 } dma;
242
243 uint32_t sw_subchannel[8];
244
245 struct {
246 struct nouveau_gpuobj *vblsem;
247 uint32_t vblsem_offset;
248 uint32_t vblsem_rval;
249 struct list_head vbl_wait;
250 } nvsw;
251
252 struct {
253 bool active;
254 char name[32];
255 struct drm_info_list info;
256 } debugfs;
257};
258
259struct nouveau_instmem_engine {
260 void *priv;
261
262 int (*init)(struct drm_device *dev);
263 void (*takedown)(struct drm_device *dev);
264 int (*suspend)(struct drm_device *dev);
265 void (*resume)(struct drm_device *dev);
266
267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
268 uint32_t *size);
269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
272 void (*prepare_access)(struct drm_device *, bool write);
273 void (*finish_access)(struct drm_device *);
274};
275
276struct nouveau_mc_engine {
277 int (*init)(struct drm_device *dev);
278 void (*takedown)(struct drm_device *dev);
279};
280
281struct nouveau_timer_engine {
282 int (*init)(struct drm_device *dev);
283 void (*takedown)(struct drm_device *dev);
284 uint64_t (*read)(struct drm_device *dev);
285};
286
287struct nouveau_fb_engine {
cb00f7c1
FJ		 288 int num_tiles;
289
6ee73861
BS		 290 int (*init)(struct drm_device *dev);
291 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 292
293 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
294 uint32_t size, uint32_t pitch);
6ee73861
BS		 295};
296
297struct nouveau_fifo_engine {
298 void *priv;
299
300 int channels;
301
302 int (*init)(struct drm_device *);
303 void (*takedown)(struct drm_device *);
304
305 void (*disable)(struct drm_device *);
306 void (*enable)(struct drm_device *);
307 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 308 bool (*cache_flush)(struct drm_device *dev);
309 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 310
311 int (*channel_id)(struct drm_device *);
312
313 int (*create_context)(struct nouveau_channel *);
314 void (*destroy_context)(struct nouveau_channel *);
315 int (*load_context)(struct nouveau_channel *);
316 int (*unload_context)(struct drm_device *);
317};
318
319struct nouveau_pgraph_object_method {
320 int id;
321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
322 uint32_t data);
323};
324
325struct nouveau_pgraph_object_class {
326 int id;
327 bool software;
328 struct nouveau_pgraph_object_method *methods;
329};
330
331struct nouveau_pgraph_engine {
332 struct nouveau_pgraph_object_class *grclass;
333 bool accel_blocked;
334 void *ctxprog;
335 void *ctxvals;
054b93e4 336 int grctx_size;
6ee73861
BS		 337
338 int (*init)(struct drm_device *);
339 void (*takedown)(struct drm_device *);
340
341 void (*fifo_access)(struct drm_device *, bool);
342
343 struct nouveau_channel *(*channel)(struct drm_device *);
344 int (*create_context)(struct nouveau_channel *);
345 void (*destroy_context)(struct nouveau_channel *);
346 int (*load_context)(struct nouveau_channel *);
347 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 348
349 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
350 uint32_t size, uint32_t pitch);
6ee73861
BS		 351};
352
353struct nouveau_engine {
354 struct nouveau_instmem_engine instmem;
355 struct nouveau_mc_engine mc;
356 struct nouveau_timer_engine timer;
357 struct nouveau_fb_engine fb;
358 struct nouveau_pgraph_engine graph;
359 struct nouveau_fifo_engine fifo;
360};
361
362struct nouveau_pll_vals {
363 union {
364 struct {
365#ifdef __BIG_ENDIAN
366 uint8_t N1, M1, N2, M2;
367#else
368 uint8_t M1, N1, M2, N2;
369#endif
370 };
371 struct {
372 uint16_t NM1, NM2;
373 } __attribute__((packed));
374 };
375 int log2P;
376
377 int refclk;
378};
379
380enum nv04_fp_display_regs {
381 FP_DISPLAY_END,
382 FP_TOTAL,
383 FP_CRTC,
384 FP_SYNC_START,
385 FP_SYNC_END,
386 FP_VALID_START,
387 FP_VALID_END
388};
389
390struct nv04_crtc_reg {
391 unsigned char MiscOutReg; /* */
392 uint8_t CRTC[0x9f];
393 uint8_t CR58[0x10];
394 uint8_t Sequencer[5];
395 uint8_t Graphics[9];
396 uint8_t Attribute[21];
397 unsigned char DAC[768]; /* Internal Colorlookuptable */
398
399 /* PCRTC regs */
400 uint32_t fb_start;
401 uint32_t crtc_cfg;
402 uint32_t cursor_cfg;
403 uint32_t gpio_ext;
404 uint32_t crtc_830;
405 uint32_t crtc_834;
406 uint32_t crtc_850;
407 uint32_t crtc_eng_ctrl;
408
409 /* PRAMDAC regs */
410 uint32_t nv10_cursync;
411 struct nouveau_pll_vals pllvals;
412 uint32_t ramdac_gen_ctrl;
413 uint32_t ramdac_630;
414 uint32_t ramdac_634;
415 uint32_t tv_setup;
416 uint32_t tv_vtotal;
417 uint32_t tv_vskew;
418 uint32_t tv_vsync_delay;
419 uint32_t tv_htotal;
420 uint32_t tv_hskew;
421 uint32_t tv_hsync_delay;
422 uint32_t tv_hsync_delay2;
423 uint32_t fp_horiz_regs[7];
424 uint32_t fp_vert_regs[7];
425 uint32_t dither;
426 uint32_t fp_control;
427 uint32_t dither_regs[6];
428 uint32_t fp_debug_0;
429 uint32_t fp_debug_1;
430 uint32_t fp_debug_2;
431 uint32_t fp_margin_color;
432 uint32_t ramdac_8c0;
433 uint32_t ramdac_a20;
434 uint32_t ramdac_a24;
435 uint32_t ramdac_a34;
436 uint32_t ctv_regs[38];
437};
438
439struct nv04_output_reg {
440 uint32_t output;
441 int head;
442};
443
444struct nv04_mode_state {
445 uint32_t bpp;
446 uint32_t width;
447 uint32_t height;
448 uint32_t interlace;
449 uint32_t repaint0;
450 uint32_t repaint1;
451 uint32_t screen;
452 uint32_t scale;
453 uint32_t dither;
454 uint32_t extra;
455 uint32_t fifo;
456 uint32_t pixel;
457 uint32_t horiz;
458 int arbitration0;
459 int arbitration1;
460 uint32_t pll;
461 uint32_t pllB;
462 uint32_t vpll;
463 uint32_t vpll2;
464 uint32_t vpllB;
465 uint32_t vpll2B;
466 uint32_t pllsel;
467 uint32_t sel_clk;
468 uint32_t general;
469 uint32_t crtcOwner;
470 uint32_t head;
471 uint32_t head2;
472 uint32_t cursorConfig;
473 uint32_t cursor0;
474 uint32_t cursor1;
475 uint32_t cursor2;
476 uint32_t timingH;
477 uint32_t timingV;
478 uint32_t displayV;
479 uint32_t crtcSync;
480
481 struct nv04_crtc_reg crtc_reg[2];
482};
483
484enum nouveau_card_type {
485 NV_04 = 0x00,
486 NV_10 = 0x10,
487 NV_20 = 0x20,
488 NV_30 = 0x30,
489 NV_40 = 0x40,
490 NV_50 = 0x50,
491};
492
493struct drm_nouveau_private {
494 struct drm_device *dev;
6ee73861
BS		 495
496 /* the card type, takes NV_* as values */
497 enum nouveau_card_type card_type;
498 /* exact chipset, derived from NV_PMC_BOOT_0 */
499 int chipset;
500 int flags;
501
502 void __iomem *mmio;
503 void __iomem *ramin;
504 uint32_t ramin_size;
505
ac8fb975
BS		 506 struct nouveau_bo *vga_ram;
507
6ee73861
BS		 508 struct workqueue_struct *wq;
509 struct work_struct irq_work;
a5acac66 510 struct work_struct hpd_work;
6ee73861
BS		 511
512 struct list_head vbl_waiting;
513
514 struct {
515 struct ttm_global_reference mem_global_ref;
516 struct ttm_bo_global_ref bo_global_ref;
517 struct ttm_bo_device bdev;
518 spinlock_t bo_list_lock;
519 struct list_head bo_list;
520 atomic_t validate_sequence;
521 } ttm;
522
523 struct fb_info *fbdev_info;
524
525 int fifo_alloc_count;
526 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
527
528 struct nouveau_engine engine;
529 struct nouveau_channel *channel;
530
ff9e5279
MM		 531 /* For PFIFO and PGRAPH. */
532 spinlock_t context_switch_lock;
533
6ee73861
BS		 534 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
535 struct nouveau_gpuobj *ramht;
536 uint32_t ramin_rsvd_vram;
537 uint32_t ramht_offset;
538 uint32_t ramht_size;
539 uint32_t ramht_bits;
540 uint32_t ramfc_offset;
541 uint32_t ramfc_size;
542 uint32_t ramro_offset;
543 uint32_t ramro_size;
544
6ee73861
BS		 545 struct {
546 enum {
547 NOUVEAU_GART_NONE = 0,
548 NOUVEAU_GART_AGP,
549 NOUVEAU_GART_SGDMA
550 } type;
551 uint64_t aper_base;
552 uint64_t aper_size;
553 uint64_t aper_free;
554
555 struct nouveau_gpuobj *sg_ctxdma;
556 struct page *sg_dummy_page;
557 dma_addr_t sg_dummy_bus;
6ee73861
BS		 558 } gart_info;
559
a0af9add
FJ		 560 /* nv10-nv40 tiling regions */
561 struct {
562 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
563 spinlock_t lock;
564 } tile;
565
a76fb4e8
BS		 566 /* VRAM/fb configuration */
567 uint64_t vram_size;
568 uint64_t vram_sys_base;
569
570 uint64_t fb_phys;
571 uint64_t fb_available_size;
572 uint64_t fb_mappable_pages;
573 uint64_t fb_aper_free;
574 int fb_mtrr;
575
6ee73861
BS		 576 /* G8x/G9x virtual address space */
577 uint64_t vm_gart_base;
578 uint64_t vm_gart_size;
579 uint64_t vm_vram_base;
580 uint64_t vm_vram_size;
581 uint64_t vm_end;
582 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
583 int vm_vram_pt_nr;
6ee73861 584
b833ac26 585 struct drm_mm ramin_heap;
6ee73861
BS		 586
587 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
588 uint32_t ctx_table_size;
589 struct nouveau_gpuobj_ref *ctx_table;
590
591 struct list_head gpuobj_list;
592
04a39c57 593 struct nvbios vbios;
6ee73861
BS		 594
595 struct nv04_mode_state mode_reg;
596 struct nv04_mode_state saved_reg;
597 uint32_t saved_vga_font[4][16384];
598 uint32_t crtc_owner;
599 uint32_t dac_users[4];
600
601 struct nouveau_suspend_resume {
6ee73861 602 uint32_t *ramin_copy;
6ee73861
BS		 603 } susres;
604
605 struct backlight_device *backlight;
6ee73861
BS		 606
607 struct nouveau_channel *evo;
87c0e0e5
BS		 608 struct {
609 struct dcb_entry *dcb;
610 u16 script;
611 u32 pclk;
612 } evo_irq;
6ee73861
BS		 613
614 struct {
615 struct dentry *channel_root;
616 } debugfs;
38651674 617
8be48d92 618 struct nouveau_fbdev *nfbdev;
06415c56 619 struct apertures_struct *apertures;
6ee73861
BS		 620};
621
622static inline struct drm_nouveau_private *
623nouveau_bdev(struct ttm_bo_device *bd)
624{
625 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
626}
627
628static inline int
629nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
630{
631 struct nouveau_bo *prev;
632
633 if (!pnvbo)
634 return -EINVAL;
635 prev = *pnvbo;
636
637 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
638 if (prev) {
639 struct ttm_buffer_object *bo = &prev->bo;
640
641 ttm_bo_unref(&bo);
642 }
643
644 return 0;
645}
646
6ee73861
BS		 647#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
648 struct drm_nouveau_private *nv = dev->dev_private; \
649 if (!nouveau_channel_owner(dev, (cl), (id))) { \
650 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
651 DRM_CURRENTPID, (id)); \
652 return -EPERM; \
653 } \
654 (ch) = nv->fifos[(id)]; \
655} while (0)
656
657/* nouveau_drv.c */
658extern int nouveau_noagp;
659extern int nouveau_duallink;
660extern int nouveau_uscript_lvds;
661extern int nouveau_uscript_tmds;
662extern int nouveau_vram_pushbuf;
663extern int nouveau_vram_notify;
664extern int nouveau_fbpercrtc;
f4053509 665extern int nouveau_tv_disable;
6ee73861
BS		 666extern char *nouveau_tv_norm;
667extern int nouveau_reg_debug;
668extern char *nouveau_vbios;
054b93e4 669extern int nouveau_ctxfw;
a1470890 670extern int nouveau_ignorelid;
a32ed69d
MK		 671extern int nouveau_nofbaccel;
672extern int nouveau_noaccel;
da647d5b 673extern int nouveau_override_conntype;
6ee73861 674
6a9ee8af
DA		 675extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
676extern int nouveau_pci_resume(struct pci_dev *pdev);
677
6ee73861
BS		 678/* nouveau_state.c */
679extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
680extern int nouveau_load(struct drm_device *, unsigned long flags);
681extern int nouveau_firstopen(struct drm_device *);
682extern void nouveau_lastclose(struct drm_device *);
683extern int nouveau_unload(struct drm_device *);
684extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
685 struct drm_file *);
686extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
687 struct drm_file *);
688extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
689 uint32_t reg, uint32_t mask, uint32_t val);
690extern bool nouveau_wait_for_idle(struct drm_device *);
691extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 692
693/* nouveau_mem.c */
a76fb4e8 694extern int nouveau_mem_detect(struct drm_device *dev);
6ee73861
BS		 695extern int nouveau_mem_init(struct drm_device *);
696extern int nouveau_mem_init_agp(struct drm_device *);
697extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 698extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
699 uint32_t addr,
700 uint32_t size,
701 uint32_t pitch);
702extern void nv10_mem_expire_tiling(struct drm_device *dev,
703 struct nouveau_tile_reg *tile,
704 struct nouveau_fence *fence);
6ee73861
BS		 705extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
706 uint32_t size, uint32_t flags,
707 uint64_t phys);
708extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
709 uint32_t size);
710
711/* nouveau_notifier.c */
712extern int nouveau_notifier_init_channel(struct nouveau_channel *);
713extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
714extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
715 int cout, uint32_t *offset);
716extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
717extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
718 struct drm_file *);
719extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
720 struct drm_file *);
721
722/* nouveau_channel.c */
723extern struct drm_ioctl_desc nouveau_ioctls[];
724extern int nouveau_max_ioctl;
725extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
726extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
727 int channel);
728extern int nouveau_channel_alloc(struct drm_device *dev,
729 struct nouveau_channel **chan,
730 struct drm_file *file_priv,
731 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
732extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 733
734/* nouveau_object.c */
735extern int nouveau_gpuobj_early_init(struct drm_device *);
736extern int nouveau_gpuobj_init(struct drm_device *);
737extern void nouveau_gpuobj_takedown(struct drm_device *);
738extern void nouveau_gpuobj_late_takedown(struct drm_device *);
739extern int nouveau_gpuobj_suspend(struct drm_device *dev);
740extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
741extern void nouveau_gpuobj_resume(struct drm_device *dev);
742extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
743 uint32_t vram_h, uint32_t tt_h);
744extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
745extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
746 uint32_t size, int align, uint32_t flags,
747 struct nouveau_gpuobj **);
748extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
749extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
750 uint32_t handle, struct nouveau_gpuobj *,
751 struct nouveau_gpuobj_ref **);
752extern int nouveau_gpuobj_ref_del(struct drm_device *,
753 struct nouveau_gpuobj_ref **);
754extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
755 struct nouveau_gpuobj_ref **ref_ret);
756extern int nouveau_gpuobj_new_ref(struct drm_device *,
757 struct nouveau_channel *alloc_chan,
758 struct nouveau_channel *ref_chan,
759 uint32_t handle, uint32_t size, int align,
760 uint32_t flags, struct nouveau_gpuobj_ref **);
761extern int nouveau_gpuobj_new_fake(struct drm_device *,
762 uint32_t p_offset, uint32_t b_offset,
763 uint32_t size, uint32_t flags,
764 struct nouveau_gpuobj **,
765 struct nouveau_gpuobj_ref**);
766extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
767 uint64_t offset, uint64_t size, int access,
768 int target, struct nouveau_gpuobj **);
769extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
770 uint64_t offset, uint64_t size,
771 int access, struct nouveau_gpuobj **,
772 uint32_t *o_ret);
773extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
774 struct nouveau_gpuobj **);
f03a314b
FJ		 775extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
776 struct nouveau_gpuobj **);
6ee73861
BS		 777extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
778 struct drm_file *);
779extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
780 struct drm_file *);
781
782/* nouveau_irq.c */
783extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
784extern void nouveau_irq_preinstall(struct drm_device *);
785extern int nouveau_irq_postinstall(struct drm_device *);
786extern void nouveau_irq_uninstall(struct drm_device *);
787
788/* nouveau_sgdma.c */
789extern int nouveau_sgdma_init(struct drm_device *);
790extern void nouveau_sgdma_takedown(struct drm_device *);
791extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
792 uint32_t *page);
793extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
794
795/* nouveau_debugfs.c */
796#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
797extern int nouveau_debugfs_init(struct drm_minor *);
798extern void nouveau_debugfs_takedown(struct drm_minor *);
799extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
800extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
801#else
802static inline int
803nouveau_debugfs_init(struct drm_minor *minor)
804{
805 return 0;
806}
807
808static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
809{
810}
811
812static inline int
813nouveau_debugfs_channel_init(struct nouveau_channel *chan)
814{
815 return 0;
816}
817
818static inline void
819nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
820{
821}
822#endif
823
824/* nouveau_dma.c */
75c99da6 825extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 826extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 827extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 828
829/* nouveau_acpi.c */
afeb3e11 830#define ROM_BIOS_PAGE 4096
2f41a7f1 831#if defined(CONFIG_ACPI)
6a9ee8af
DA		 832void nouveau_register_dsm_handler(void);
833void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 834int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
835bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
8edb381d
DA		 836#else
837static inline void nouveau_register_dsm_handler(void) {}
838static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 839static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
840static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
8edb381d 841#endif
6ee73861
BS		 842
843/* nouveau_backlight.c */
844#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
845extern int nouveau_backlight_init(struct drm_device *);
846extern void nouveau_backlight_exit(struct drm_device *);
847#else
848static inline int nouveau_backlight_init(struct drm_device *dev)
849{
850 return 0;
851}
852
853static inline void nouveau_backlight_exit(struct drm_device *dev) { }
854#endif
855
856/* nouveau_bios.c */
857extern int nouveau_bios_init(struct drm_device *);
858extern void nouveau_bios_takedown(struct drm_device *dev);
859extern int nouveau_run_vbios_init(struct drm_device *);
860extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
861 struct dcb_entry *);
862extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
863 enum dcb_gpio_tag);
864extern struct dcb_connector_table_entry *
865nouveau_bios_connector_entry(struct drm_device *, int index);
866extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
867 struct pll_lims *);
868extern int nouveau_bios_run_display_table(struct drm_device *,
869 struct dcb_entry *,
870 uint32_t script, int pxclk);
871extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
872 int *length);
873extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
874extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
875extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
876 bool *dl, bool *if_is_24bit);
877extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
878 int head, int pxclk);
879extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
880 enum LVDS_script, int pxclk);
881
882/* nouveau_ttm.c */
883int nouveau_ttm_global_init(struct drm_nouveau_private *);
884void nouveau_ttm_global_release(struct drm_nouveau_private *);
885int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
886
887/* nouveau_dp.c */
888int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
889 uint8_t *data, int data_nr);
890bool nouveau_dp_detect(struct drm_encoder *);
891bool nouveau_dp_link_train(struct drm_encoder *);
892
893/* nv04_fb.c */
894extern int nv04_fb_init(struct drm_device *);
895extern void nv04_fb_takedown(struct drm_device *);
896
897/* nv10_fb.c */
898extern int nv10_fb_init(struct drm_device *);
899extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 900extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
901 uint32_t, uint32_t);
6ee73861
BS		 902
903/* nv40_fb.c */
904extern int nv40_fb_init(struct drm_device *);
905extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 906extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
907 uint32_t, uint32_t);
6ee73861 908
304424e1
MK		 909/* nv50_fb.c */
910extern int nv50_fb_init(struct drm_device *);
911extern void nv50_fb_takedown(struct drm_device *);
912
6ee73861
BS		 913/* nv04_fifo.c */
914extern int nv04_fifo_init(struct drm_device *);
915extern void nv04_fifo_disable(struct drm_device *);
916extern void nv04_fifo_enable(struct drm_device *);
917extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 918extern bool nv04_fifo_cache_flush(struct drm_device *);
919extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 920extern int nv04_fifo_channel_id(struct drm_device *);
921extern int nv04_fifo_create_context(struct nouveau_channel *);
922extern void nv04_fifo_destroy_context(struct nouveau_channel *);
923extern int nv04_fifo_load_context(struct nouveau_channel *);
924extern int nv04_fifo_unload_context(struct drm_device *);
925
926/* nv10_fifo.c */
927extern int nv10_fifo_init(struct drm_device *);
928extern int nv10_fifo_channel_id(struct drm_device *);
929extern int nv10_fifo_create_context(struct nouveau_channel *);
930extern void nv10_fifo_destroy_context(struct nouveau_channel *);
931extern int nv10_fifo_load_context(struct nouveau_channel *);
932extern int nv10_fifo_unload_context(struct drm_device *);
933
934/* nv40_fifo.c */
935extern int nv40_fifo_init(struct drm_device *);
936extern int nv40_fifo_create_context(struct nouveau_channel *);
937extern void nv40_fifo_destroy_context(struct nouveau_channel *);
938extern int nv40_fifo_load_context(struct nouveau_channel *);
939extern int nv40_fifo_unload_context(struct drm_device *);
940
941/* nv50_fifo.c */
942extern int nv50_fifo_init(struct drm_device *);
943extern void nv50_fifo_takedown(struct drm_device *);
944extern int nv50_fifo_channel_id(struct drm_device *);
945extern int nv50_fifo_create_context(struct nouveau_channel *);
946extern void nv50_fifo_destroy_context(struct nouveau_channel *);
947extern int nv50_fifo_load_context(struct nouveau_channel *);
948extern int nv50_fifo_unload_context(struct drm_device *);
949
950/* nv04_graph.c */
951extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
952extern int nv04_graph_init(struct drm_device *);
953extern void nv04_graph_takedown(struct drm_device *);
954extern void nv04_graph_fifo_access(struct drm_device *, bool);
955extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
956extern int nv04_graph_create_context(struct nouveau_channel *);
957extern void nv04_graph_destroy_context(struct nouveau_channel *);
958extern int nv04_graph_load_context(struct nouveau_channel *);
959extern int nv04_graph_unload_context(struct drm_device *);
960extern void nv04_graph_context_switch(struct drm_device *);
961
962/* nv10_graph.c */
963extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
964extern int nv10_graph_init(struct drm_device *);
965extern void nv10_graph_takedown(struct drm_device *);
966extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
967extern int nv10_graph_create_context(struct nouveau_channel *);
968extern void nv10_graph_destroy_context(struct nouveau_channel *);
969extern int nv10_graph_load_context(struct nouveau_channel *);
970extern int nv10_graph_unload_context(struct drm_device *);
971extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 972extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
973 uint32_t, uint32_t);
6ee73861
BS		 974
975/* nv20_graph.c */
976extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
977extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
978extern int nv20_graph_create_context(struct nouveau_channel *);
979extern void nv20_graph_destroy_context(struct nouveau_channel *);
980extern int nv20_graph_load_context(struct nouveau_channel *);
981extern int nv20_graph_unload_context(struct drm_device *);
982extern int nv20_graph_init(struct drm_device *);
983extern void nv20_graph_takedown(struct drm_device *);
984extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 985extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
986 uint32_t, uint32_t);
6ee73861
BS		 987
988/* nv40_graph.c */
989extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
990extern int nv40_graph_init(struct drm_device *);
991extern void nv40_graph_takedown(struct drm_device *);
992extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
993extern int nv40_graph_create_context(struct nouveau_channel *);
994extern void nv40_graph_destroy_context(struct nouveau_channel *);
995extern int nv40_graph_load_context(struct nouveau_channel *);
996extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 997extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 998extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
999 uint32_t, uint32_t);
6ee73861
BS		 1000
1001/* nv50_graph.c */
1002extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1003extern int nv50_graph_init(struct drm_device *);
1004extern void nv50_graph_takedown(struct drm_device *);
1005extern void nv50_graph_fifo_access(struct drm_device *, bool);
1006extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1007extern int nv50_graph_create_context(struct nouveau_channel *);
1008extern void nv50_graph_destroy_context(struct nouveau_channel *);
1009extern int nv50_graph_load_context(struct nouveau_channel *);
1010extern int nv50_graph_unload_context(struct drm_device *);
1011extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1012extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1013
054b93e4
BS		 1014/* nouveau_grctx.c */
1015extern int nouveau_grctx_prog_load(struct drm_device *);
1016extern void nouveau_grctx_vals_load(struct drm_device *,
1017 struct nouveau_gpuobj *);
1018extern void nouveau_grctx_fini(struct drm_device *);
1019
6ee73861
BS		 1020/* nv04_instmem.c */
1021extern int nv04_instmem_init(struct drm_device *);
1022extern void nv04_instmem_takedown(struct drm_device *);
1023extern int nv04_instmem_suspend(struct drm_device *);
1024extern void nv04_instmem_resume(struct drm_device *);
1025extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1026 uint32_t *size);
1027extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1028extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1029extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1030extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1031extern void nv04_instmem_finish_access(struct drm_device *);
1032
1033/* nv50_instmem.c */
1034extern int nv50_instmem_init(struct drm_device *);
1035extern void nv50_instmem_takedown(struct drm_device *);
1036extern int nv50_instmem_suspend(struct drm_device *);
1037extern void nv50_instmem_resume(struct drm_device *);
1038extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1039 uint32_t *size);
1040extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1041extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1042extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1043extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1044extern void nv50_instmem_finish_access(struct drm_device *);
1045
1046/* nv04_mc.c */
1047extern int nv04_mc_init(struct drm_device *);
1048extern void nv04_mc_takedown(struct drm_device *);
1049
1050/* nv40_mc.c */
1051extern int nv40_mc_init(struct drm_device *);
1052extern void nv40_mc_takedown(struct drm_device *);
1053
1054/* nv50_mc.c */
1055extern int nv50_mc_init(struct drm_device *);
1056extern void nv50_mc_takedown(struct drm_device *);
1057
1058/* nv04_timer.c */
1059extern int nv04_timer_init(struct drm_device *);
1060extern uint64_t nv04_timer_read(struct drm_device *);
1061extern void nv04_timer_takedown(struct drm_device *);
1062
1063extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1064 unsigned long arg);
1065
1066/* nv04_dac.c */
8f1a6086 1067extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1068extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1069extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1070extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1071extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1072
1073/* nv04_dfp.c */
8f1a6086 1074extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1075extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1076extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1077 int head, bool dl);
1078extern void nv04_dfp_disable(struct drm_device *dev, int head);
1079extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1080
1081/* nv04_tv.c */
1082extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1083extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1084
1085/* nv17_tv.c */
8f1a6086 1086extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1087
1088/* nv04_display.c */
1089extern int nv04_display_create(struct drm_device *);
1090extern void nv04_display_destroy(struct drm_device *);
1091extern void nv04_display_restore(struct drm_device *);
1092
1093/* nv04_crtc.c */
1094extern int nv04_crtc_create(struct drm_device *, int index);
1095
1096/* nouveau_bo.c */
1097extern struct ttm_bo_driver nouveau_bo_driver;
1098extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1099 int size, int align, uint32_t flags,
1100 uint32_t tile_mode, uint32_t tile_flags,
1101 bool no_vm, bool mappable, struct nouveau_bo **);
1102extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1103extern int nouveau_bo_unpin(struct nouveau_bo *);
1104extern int nouveau_bo_map(struct nouveau_bo *);
1105extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1106extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1107 uint32_t busy);
6ee73861
BS		 1108extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1109extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1110extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1111extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1112
1113/* nouveau_fence.c */
1114struct nouveau_fence;
1115extern int nouveau_fence_init(struct nouveau_channel *);
1116extern void nouveau_fence_fini(struct nouveau_channel *);
1117extern void nouveau_fence_update(struct nouveau_channel *);
1118extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1119 bool emit);
1120extern int nouveau_fence_emit(struct nouveau_fence *);
1121struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1122extern bool nouveau_fence_signalled(void *obj, void *arg);
1123extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1124extern int nouveau_fence_flush(void *obj, void *arg);
1125extern void nouveau_fence_unref(void **obj);
1126extern void *nouveau_fence_ref(void *obj);
1127extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1128
1129/* nouveau_gem.c */
1130extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1131 int size, int align, uint32_t flags,
1132 uint32_t tile_mode, uint32_t tile_flags,
1133 bool no_vm, bool mappable, struct nouveau_bo **);
1134extern int nouveau_gem_object_new(struct drm_gem_object *);
1135extern void nouveau_gem_object_del(struct drm_gem_object *);
1136extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1137 struct drm_file *);
1138extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1139 struct drm_file *);
6ee73861
BS		 1140extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1141 struct drm_file *);
1142extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1143 struct drm_file *);
1144extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1145 struct drm_file *);
1146
1147/* nv17_gpio.c */
1148int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1149int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1150
45284162
BS		 1151/* nv50_gpio.c */
1152int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1153int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1154
e9ebb68b
BS		 1155/* nv50_calc. */
1156int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1157 int *N1, int *M1, int *N2, int *M2, int *P);
1158int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1159 int clk, int *N, int *fN, int *M, int *P);
1160
6ee73861
BS		 1161#ifndef ioread32_native
1162#ifdef __BIG_ENDIAN
1163#define ioread16_native ioread16be
1164#define iowrite16_native iowrite16be
1165#define ioread32_native ioread32be
1166#define iowrite32_native iowrite32be
1167#else /* def __BIG_ENDIAN */
1168#define ioread16_native ioread16
1169#define iowrite16_native iowrite16
1170#define ioread32_native ioread32
1171#define iowrite32_native iowrite32
1172#endif /* def __BIG_ENDIAN else */
1173#endif /* !ioread32_native */
1174
1175/* channel control reg access */
1176static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1177{
1178 return ioread32_native(chan->user + reg);
1179}
1180
1181static inline void nvchan_wr32(struct nouveau_channel *chan,
1182 unsigned reg, u32 val)
1183{
1184 iowrite32_native(val, chan->user + reg);
1185}
1186
1187/* register access */
1188static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1189{
1190 struct drm_nouveau_private *dev_priv = dev->dev_private;
1191 return ioread32_native(dev_priv->mmio + reg);
1192}
1193
1194static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1195{
1196 struct drm_nouveau_private *dev_priv = dev->dev_private;
1197 iowrite32_native(val, dev_priv->mmio + reg);
1198}
1199
1200static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1201{
1202 struct drm_nouveau_private *dev_priv = dev->dev_private;
1203 return ioread8(dev_priv->mmio + reg);
1204}
1205
1206static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1207{
1208 struct drm_nouveau_private *dev_priv = dev->dev_private;
1209 iowrite8(val, dev_priv->mmio + reg);
1210}
1211
1212#define nv_wait(reg, mask, val) \
1213 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1214
1215/* PRAMIN access */
1216static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1217{
1218 struct drm_nouveau_private *dev_priv = dev->dev_private;
1219 return ioread32_native(dev_priv->ramin + offset);
1220}
1221
1222static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1223{
1224 struct drm_nouveau_private *dev_priv = dev->dev_private;
1225 iowrite32_native(val, dev_priv->ramin + offset);
1226}
1227
1228/* object access */
1229static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1230 unsigned index)
1231{
1232 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1233}
1234
1235static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1236 unsigned index, u32 val)
1237{
1238 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1239}
1240
1241/*
1242 * Logging
1243 * Argument d is (struct drm_device *).
1244 */
1245#define NV_PRINTK(level, d, fmt, arg...) \
1246 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1247 pci_name(d->pdev), ##arg)
1248#ifndef NV_DEBUG_NOTRACE
1249#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1250 if (drm_debug & DRM_UT_DRIVER) { \
1251 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1252 __LINE__, ##arg); \
1253 } \
1254} while (0)
1255#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1256 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1257 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1258 __LINE__, ##arg); \
1259 } \
1260} while (0)
1261#else
1262#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1263 if (drm_debug & DRM_UT_DRIVER) \
1264 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1265} while (0)
1266#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1267 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1268 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1269} while (0)
1270#endif
1271#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1272#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1273#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1274#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1275#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1276
1277/* nouveau_reg_debug bitmask */
1278enum {
1279 NOUVEAU_REG_DEBUG_MC = 0x1,
1280 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1281 NOUVEAU_REG_DEBUG_FB = 0x4,
1282 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1283 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1284 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1285 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1286 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1287 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1288 NOUVEAU_REG_DEBUG_EVO = 0x200,
1289};
1290
1291#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1292 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1293 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1294} while (0)
1295
1296static inline bool
1297nv_two_heads(struct drm_device *dev)
1298{
1299 struct drm_nouveau_private *dev_priv = dev->dev_private;
1300 const int impl = dev->pci_device & 0x0ff0;
1301
1302 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1303 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1304 return true;
1305
1306 return false;
1307}
1308
1309static inline bool
1310nv_gf4_disp_arch(struct drm_device *dev)
1311{
1312 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1313}
1314
1315static inline bool
1316nv_two_reg_pll(struct drm_device *dev)
1317{
1318 struct drm_nouveau_private *dev_priv = dev->dev_private;
1319 const int impl = dev->pci_device & 0x0ff0;
1320
1321 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1322 return true;
1323 return false;
1324}
1325
f03a314b
FJ		 1326#define NV_SW 0x0000506e
1327#define NV_SW_DMA_SEMAPHORE 0x00000060
1328#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1329#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1330#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1331#define NV_SW_DMA_VBLSEM 0x0000018c
1332#define NV_SW_VBLSEM_OFFSET 0x00000400
1333#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1334#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1335
1336#endif /* __NOUVEAU_DRV_H__ */
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