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Merge commit 'v2.6.37-rc7' into x86/security
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
f13b3263
FJ		 103#define nouveau_bo_tile_layout(nvbo) \
104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105
6ee73861
BS		 106static inline struct nouveau_bo *
107nouveau_bo(struct ttm_buffer_object *bo)
108{
109 return container_of(bo, struct nouveau_bo, bo);
110}
111
112static inline struct nouveau_bo *
113nouveau_gem_object(struct drm_gem_object *gem)
114{
115 return gem ? gem->driver_private : NULL;
116}
117
118/* TODO: submit equivalent to TTM generic API upstream? */
119static inline void __iomem *
120nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
121{
122 bool is_iomem;
123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
124 &nvbo->kmap, &is_iomem);
125 WARN_ON_ONCE(ioptr && !is_iomem);
126 return ioptr;
127}
128
6ee73861
BS		 129enum nouveau_flags {
130 NV_NFORCE = 0x10000000,
131 NV_NFORCE2 = 0x20000000
132};
133
134#define NVOBJ_ENGINE_SW 0
135#define NVOBJ_ENGINE_GR 1
136#define NVOBJ_ENGINE_DISPLAY 2
137#define NVOBJ_ENGINE_INT 0xdeadbeef
138
6ee73861
BS		 139#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
140#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 141struct nouveau_gpuobj {
b3beb167 142 struct drm_device *dev;
eb9bcbdc 143 struct kref refcount;
6ee73861
BS		 144 struct list_head list;
145
b833ac26 146 struct drm_mm_node *im_pramin;
6ee73861 147 struct nouveau_bo *im_backing;
6ee73861
BS		 148 uint32_t *im_backing_suspend;
149 int im_bound;
150
151 uint32_t flags;
6ee73861 152
43efc9ce 153 u32 size;
de3a6c0a
BS		 154 u32 pinst;
155 u32 cinst;
156 u64 vinst;
157
6ee73861
BS		 158 uint32_t engine;
159 uint32_t class;
160
161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
162 void *priv;
163};
164
6ee73861
BS		 165struct nouveau_channel {
166 struct drm_device *dev;
167 int id;
168
169 /* owner of this fifo */
170 struct drm_file *file_priv;
171 /* mapping of the fifo itself */
172 struct drm_local_map *map;
173
174 /* mapping of the regs controling the fifo */
175 void __iomem *user;
176 uint32_t user_get;
177 uint32_t user_put;
178
179 /* Fencing */
180 struct {
181 /* lock protects the pending list only */
182 spinlock_t lock;
183 struct list_head pending;
184 uint32_t sequence;
185 uint32_t sequence_ack;
047d1d3c 186 atomic_t last_sequence_irq;
6ee73861
BS		 187 } fence;
188
189 /* DMA push buffer */
a8eaebc6
BS		 190 struct nouveau_gpuobj *pushbuf;
191 struct nouveau_bo *pushbuf_bo;
192 uint32_t pushbuf_base;
6ee73861
BS		 193
194 /* Notifier memory */
195 struct nouveau_bo *notifier_bo;
b833ac26 196 struct drm_mm notifier_heap;
6ee73861
BS		 197
198 /* PFIFO context */
a8eaebc6
BS		 199 struct nouveau_gpuobj *ramfc;
200 struct nouveau_gpuobj *cache;
6ee73861
BS		 201
202 /* PGRAPH context */
203 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 204 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 205 void *pgraph_ctx;
206
207 /* NV50 VM */
a8eaebc6
BS		 208 struct nouveau_gpuobj *vm_pd;
209 struct nouveau_gpuobj *vm_gart_pt;
210 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 211
212 /* Objects */
a8eaebc6
BS		 213 struct nouveau_gpuobj *ramin; /* Private instmem */
214 struct drm_mm ramin_heap; /* Private PRAMIN heap */
215 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 216
217 /* GPU object info for stuff used in-kernel (mm_enabled) */
218 uint32_t m2mf_ntfy;
219 uint32_t vram_handle;
220 uint32_t gart_handle;
221 bool accel_done;
222
223 /* Push buffer state (only for drm's channel on !mm_enabled) */
224 struct {
225 int max;
226 int free;
227 int cur;
228 int put;
229 /* access via pushbuf_bo */
9a391ad8
BS		 230
231 int ib_base;
232 int ib_max;
233 int ib_free;
234 int ib_put;
6ee73861
BS		 235 } dma;
236
237 uint32_t sw_subchannel[8];
238
239 struct {
240 struct nouveau_gpuobj *vblsem;
241 uint32_t vblsem_offset;
242 uint32_t vblsem_rval;
243 struct list_head vbl_wait;
244 } nvsw;
245
246 struct {
247 bool active;
248 char name[32];
249 struct drm_info_list info;
250 } debugfs;
251};
252
253struct nouveau_instmem_engine {
254 void *priv;
255
256 int (*init)(struct drm_device *dev);
257 void (*takedown)(struct drm_device *dev);
258 int (*suspend)(struct drm_device *dev);
259 void (*resume)(struct drm_device *dev);
260
261 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
262 uint32_t *size);
263 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
264 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
265 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 266 void (*flush)(struct drm_device *);
6ee73861
BS		 267};
268
269struct nouveau_mc_engine {
270 int (*init)(struct drm_device *dev);
271 void (*takedown)(struct drm_device *dev);
272};
273
274struct nouveau_timer_engine {
275 int (*init)(struct drm_device *dev);
276 void (*takedown)(struct drm_device *dev);
277 uint64_t (*read)(struct drm_device *dev);
278};
279
280struct nouveau_fb_engine {
cb00f7c1
FJ		 281 int num_tiles;
282
6ee73861
BS		 283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 285
286 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
287 uint32_t size, uint32_t pitch);
6ee73861
BS		 288};
289
290struct nouveau_fifo_engine {
6ee73861
BS		 291 int channels;
292
a8eaebc6 293 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 294 int cur_playlist;
295
6ee73861
BS		 296 int (*init)(struct drm_device *);
297 void (*takedown)(struct drm_device *);
298
299 void (*disable)(struct drm_device *);
300 void (*enable)(struct drm_device *);
301 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 302 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 303
304 int (*channel_id)(struct drm_device *);
305
306 int (*create_context)(struct nouveau_channel *);
307 void (*destroy_context)(struct nouveau_channel *);
308 int (*load_context)(struct nouveau_channel *);
309 int (*unload_context)(struct drm_device *);
56ac7475 310 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 311};
312
313struct nouveau_pgraph_object_method {
314 int id;
315 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
316 uint32_t data);
317};
318
319struct nouveau_pgraph_object_class {
320 int id;
321 bool software;
322 struct nouveau_pgraph_object_method *methods;
323};
324
325struct nouveau_pgraph_engine {
326 struct nouveau_pgraph_object_class *grclass;
327 bool accel_blocked;
054b93e4 328 int grctx_size;
6ee73861 329
c50a5681 330 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 331 struct nouveau_gpuobj *ctx_table;
c50a5681 332
6ee73861
BS		 333 int (*init)(struct drm_device *);
334 void (*takedown)(struct drm_device *);
335
336 void (*fifo_access)(struct drm_device *, bool);
337
338 struct nouveau_channel *(*channel)(struct drm_device *);
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
56ac7475 343 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1
FJ		 344
345 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
346 uint32_t size, uint32_t pitch);
6ee73861
BS		 347};
348
c88c2e06
FJ		 349struct nouveau_display_engine {
350 int (*early_init)(struct drm_device *);
351 void (*late_takedown)(struct drm_device *);
352 int (*create)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*destroy)(struct drm_device *);
355};
356
ee2e0131
BS		 357struct nouveau_gpio_engine {
358 int (*init)(struct drm_device *);
359 void (*takedown)(struct drm_device *);
360
361 int (*get)(struct drm_device *, enum dcb_gpio_tag);
362 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
363
364 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
365};
366
330c5988
BS		 367struct nouveau_pm_voltage_level {
368 u8 voltage;
369 u8 vid;
370};
371
372struct nouveau_pm_voltage {
373 bool supported;
374 u8 vid_mask;
375
376 struct nouveau_pm_voltage_level *level;
377 int nr_level;
378};
379
380#define NOUVEAU_PM_MAX_LEVEL 8
381struct nouveau_pm_level {
382 struct device_attribute dev_attr;
383 char name[32];
384 int id;
385
386 u32 core;
387 u32 memory;
388 u32 shader;
389 u32 unk05;
390
391 u8 voltage;
392 u8 fanspeed;
aee582de
BS		 393
394 u16 memscript;
330c5988
BS		 395};
396
34e9d85a
MP		 397struct nouveau_pm_temp_sensor_constants {
398 u16 offset_constant;
399 s16 offset_mult;
400 u16 offset_div;
401 u16 slope_mult;
402 u16 slope_div;
403};
404
405struct nouveau_pm_threshold_temp {
406 s16 critical;
407 s16 down_clock;
408 s16 fan_boost;
409};
410
7760fcb0
RS		 411struct nouveau_pm_memtiming {
412 u32 reg_100220;
413 u32 reg_100224;
414 u32 reg_100228;
415 u32 reg_10022c;
416 u32 reg_100230;
417 u32 reg_100234;
418 u32 reg_100238;
419 u32 reg_10023c;
420};
421
422struct nouveau_pm_memtimings {
423 bool supported;
424 struct nouveau_pm_memtiming *timing;
425 int nr_timing;
426};
427
330c5988
BS		 428struct nouveau_pm_engine {
429 struct nouveau_pm_voltage voltage;
430 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
431 int nr_perflvl;
7760fcb0 432 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 433 struct nouveau_pm_temp_sensor_constants sensor_constants;
434 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 435
436 struct nouveau_pm_level boot;
437 struct nouveau_pm_level *cur;
438
8155cac4
FJ		 439 struct device *hwmon;
440
330c5988 441 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 442 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
443 u32 id, int khz);
330c5988
BS		 444 void (*clock_set)(struct drm_device *, void *);
445 int (*voltage_get)(struct drm_device *);
446 int (*voltage_set)(struct drm_device *, int voltage);
447 int (*fanspeed_get)(struct drm_device *);
448 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 449 int (*temp_get)(struct drm_device *);
330c5988
BS		 450};
451
6ee73861
BS		 452struct nouveau_engine {
453 struct nouveau_instmem_engine instmem;
454 struct nouveau_mc_engine mc;
455 struct nouveau_timer_engine timer;
456 struct nouveau_fb_engine fb;
457 struct nouveau_pgraph_engine graph;
458 struct nouveau_fifo_engine fifo;
c88c2e06 459 struct nouveau_display_engine display;
ee2e0131 460 struct nouveau_gpio_engine gpio;
330c5988 461 struct nouveau_pm_engine pm;
6ee73861
BS		 462};
463
464struct nouveau_pll_vals {
465 union {
466 struct {
467#ifdef __BIG_ENDIAN
468 uint8_t N1, M1, N2, M2;
469#else
470 uint8_t M1, N1, M2, N2;
471#endif
472 };
473 struct {
474 uint16_t NM1, NM2;
475 } __attribute__((packed));
476 };
477 int log2P;
478
479 int refclk;
480};
481
482enum nv04_fp_display_regs {
483 FP_DISPLAY_END,
484 FP_TOTAL,
485 FP_CRTC,
486 FP_SYNC_START,
487 FP_SYNC_END,
488 FP_VALID_START,
489 FP_VALID_END
490};
491
492struct nv04_crtc_reg {
cbab95db 493 unsigned char MiscOutReg;
4a9f822f 494 uint8_t CRTC[0xa0];
6ee73861
BS		 495 uint8_t CR58[0x10];
496 uint8_t Sequencer[5];
497 uint8_t Graphics[9];
498 uint8_t Attribute[21];
cbab95db 499 unsigned char DAC[768];
6ee73861
BS		 500
501 /* PCRTC regs */
502 uint32_t fb_start;
503 uint32_t crtc_cfg;
504 uint32_t cursor_cfg;
505 uint32_t gpio_ext;
506 uint32_t crtc_830;
507 uint32_t crtc_834;
508 uint32_t crtc_850;
509 uint32_t crtc_eng_ctrl;
510
511 /* PRAMDAC regs */
512 uint32_t nv10_cursync;
513 struct nouveau_pll_vals pllvals;
514 uint32_t ramdac_gen_ctrl;
515 uint32_t ramdac_630;
516 uint32_t ramdac_634;
517 uint32_t tv_setup;
518 uint32_t tv_vtotal;
519 uint32_t tv_vskew;
520 uint32_t tv_vsync_delay;
521 uint32_t tv_htotal;
522 uint32_t tv_hskew;
523 uint32_t tv_hsync_delay;
524 uint32_t tv_hsync_delay2;
525 uint32_t fp_horiz_regs[7];
526 uint32_t fp_vert_regs[7];
527 uint32_t dither;
528 uint32_t fp_control;
529 uint32_t dither_regs[6];
530 uint32_t fp_debug_0;
531 uint32_t fp_debug_1;
532 uint32_t fp_debug_2;
533 uint32_t fp_margin_color;
534 uint32_t ramdac_8c0;
535 uint32_t ramdac_a20;
536 uint32_t ramdac_a24;
537 uint32_t ramdac_a34;
538 uint32_t ctv_regs[38];
539};
540
541struct nv04_output_reg {
542 uint32_t output;
543 int head;
544};
545
546struct nv04_mode_state {
cbab95db 547 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 548 uint32_t pllsel;
549 uint32_t sel_clk;
6ee73861
BS		 550};
551
552enum nouveau_card_type {
553 NV_04 = 0x00,
554 NV_10 = 0x10,
555 NV_20 = 0x20,
556 NV_30 = 0x30,
557 NV_40 = 0x40,
558 NV_50 = 0x50,
4b223eef 559 NV_C0 = 0xc0,
6ee73861
BS		 560};
561
562struct drm_nouveau_private {
563 struct drm_device *dev;
6ee73861
BS		 564
565 /* the card type, takes NV_* as values */
566 enum nouveau_card_type card_type;
567 /* exact chipset, derived from NV_PMC_BOOT_0 */
568 int chipset;
569 int flags;
570
571 void __iomem *mmio;
5125bfd8 572
e05d7eae 573 spinlock_t ramin_lock;
6ee73861 574 void __iomem *ramin;
5125bfd8
BS		 575 u32 ramin_size;
576 u32 ramin_base;
577 bool ramin_available;
e05d7eae
BS		 578 struct drm_mm ramin_heap;
579 struct list_head gpuobj_list;
6ee73861 580
ac8fb975
BS		 581 struct nouveau_bo *vga_ram;
582
6ee73861
BS		 583 struct workqueue_struct *wq;
584 struct work_struct irq_work;
a5acac66 585 struct work_struct hpd_work;
6ee73861 586
ab838338
AL		 587 struct {
588 spinlock_t lock;
589 uint32_t hpd0_bits;
590 uint32_t hpd1_bits;
591 } hpd_state;
592
6ee73861
BS		 593 struct list_head vbl_waiting;
594
595 struct {
ba4420c2 596 struct drm_global_reference mem_global_ref;
6ee73861
BS		 597 struct ttm_bo_global_ref bo_global_ref;
598 struct ttm_bo_device bdev;
6ee73861
BS		 599 atomic_t validate_sequence;
600 } ttm;
601
0c6c1c2f
FJ		 602 struct {
603 spinlock_t lock;
604 struct drm_mm heap;
605 struct nouveau_bo *bo;
606 } fence;
607
6ee73861
BS		 608 int fifo_alloc_count;
609 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
610
611 struct nouveau_engine engine;
612 struct nouveau_channel *channel;
613
ff9e5279
MM		 614 /* For PFIFO and PGRAPH. */
615 spinlock_t context_switch_lock;
616
6ee73861 617 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 618 struct nouveau_ramht *ramht;
619 struct nouveau_gpuobj *ramfc;
620 struct nouveau_gpuobj *ramro;
621
6ee73861 622 uint32_t ramin_rsvd_vram;
6ee73861 623
6ee73861
BS		 624 struct {
625 enum {
626 NOUVEAU_GART_NONE = 0,
627 NOUVEAU_GART_AGP,
628 NOUVEAU_GART_SGDMA
629 } type;
630 uint64_t aper_base;
631 uint64_t aper_size;
632 uint64_t aper_free;
633
634 struct nouveau_gpuobj *sg_ctxdma;
635 struct page *sg_dummy_page;
636 dma_addr_t sg_dummy_bus;
6ee73861
BS		 637 } gart_info;
638
a0af9add 639 /* nv10-nv40 tiling regions */
9f56b126 640 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 641
a76fb4e8
BS		 642 /* VRAM/fb configuration */
643 uint64_t vram_size;
644 uint64_t vram_sys_base;
6c3d7ef2 645 u32 vram_rblock_size;
a76fb4e8
BS		 646
647 uint64_t fb_phys;
648 uint64_t fb_available_size;
649 uint64_t fb_mappable_pages;
650 uint64_t fb_aper_free;
651 int fb_mtrr;
652
6ee73861
BS		 653 /* G8x/G9x virtual address space */
654 uint64_t vm_gart_base;
655 uint64_t vm_gart_size;
656 uint64_t vm_vram_base;
657 uint64_t vm_vram_size;
658 uint64_t vm_end;
659 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
660 int vm_vram_pt_nr;
6ee73861 661
04a39c57 662 struct nvbios vbios;
6ee73861
BS		 663
664 struct nv04_mode_state mode_reg;
665 struct nv04_mode_state saved_reg;
666 uint32_t saved_vga_font[4][16384];
667 uint32_t crtc_owner;
668 uint32_t dac_users[4];
669
670 struct nouveau_suspend_resume {
6ee73861 671 uint32_t *ramin_copy;
6ee73861
BS		 672 } susres;
673
674 struct backlight_device *backlight;
6ee73861
BS		 675
676 struct nouveau_channel *evo;
87c0e0e5
BS		 677 struct {
678 struct dcb_entry *dcb;
679 u16 script;
680 u32 pclk;
681 } evo_irq;
6ee73861
BS		 682
683 struct {
684 struct dentry *channel_root;
685 } debugfs;
38651674 686
8be48d92 687 struct nouveau_fbdev *nfbdev;
06415c56 688 struct apertures_struct *apertures;
6ee73861
BS		 689};
690
2730723b
FJ		 691static inline struct drm_nouveau_private *
692nouveau_private(struct drm_device *dev)
693{
694 return dev->dev_private;
695}
696
6ee73861
BS		 697static inline struct drm_nouveau_private *
698nouveau_bdev(struct ttm_bo_device *bd)
699{
700 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
701}
702
703static inline int
704nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
705{
706 struct nouveau_bo *prev;
707
708 if (!pnvbo)
709 return -EINVAL;
710 prev = *pnvbo;
711
712 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
713 if (prev) {
714 struct ttm_buffer_object *bo = &prev->bo;
715
716 ttm_bo_unref(&bo);
717 }
718
719 return 0;
720}
721
6ee73861
BS		 722#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
723 struct drm_nouveau_private *nv = dev->dev_private; \
724 if (!nouveau_channel_owner(dev, (cl), (id))) { \
725 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
726 DRM_CURRENTPID, (id)); \
727 return -EPERM; \
728 } \
729 (ch) = nv->fifos[(id)]; \
730} while (0)
731
732/* nouveau_drv.c */
de5899bd 733extern int nouveau_agpmode;
6ee73861
BS		 734extern int nouveau_duallink;
735extern int nouveau_uscript_lvds;
736extern int nouveau_uscript_tmds;
737extern int nouveau_vram_pushbuf;
738extern int nouveau_vram_notify;
739extern int nouveau_fbpercrtc;
f4053509 740extern int nouveau_tv_disable;
6ee73861
BS		 741extern char *nouveau_tv_norm;
742extern int nouveau_reg_debug;
743extern char *nouveau_vbios;
a1470890 744extern int nouveau_ignorelid;
a32ed69d
MK		 745extern int nouveau_nofbaccel;
746extern int nouveau_noaccel;
0cba1b76 747extern int nouveau_force_post;
da647d5b 748extern int nouveau_override_conntype;
6f876986
BS		 749extern char *nouveau_perflvl;
750extern int nouveau_perflvl_wr;
6ee73861 751
6a9ee8af
DA		 752extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
753extern int nouveau_pci_resume(struct pci_dev *pdev);
754
6ee73861
BS		 755/* nouveau_state.c */
756extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
757extern int nouveau_load(struct drm_device *, unsigned long flags);
758extern int nouveau_firstopen(struct drm_device *);
759extern void nouveau_lastclose(struct drm_device *);
760extern int nouveau_unload(struct drm_device *);
761extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
762 struct drm_file *);
763extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
764 struct drm_file *);
765extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
766 uint32_t reg, uint32_t mask, uint32_t val);
767extern bool nouveau_wait_for_idle(struct drm_device *);
768extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 769
770/* nouveau_mem.c */
fbd2895e
BS		 771extern int nouveau_mem_vram_init(struct drm_device *);
772extern void nouveau_mem_vram_fini(struct drm_device *);
773extern int nouveau_mem_gart_init(struct drm_device *);
774extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 775extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 776extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 777extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 778extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
779 uint32_t addr,
780 uint32_t size,
781 uint32_t pitch);
782extern void nv10_mem_expire_tiling(struct drm_device *dev,
783 struct nouveau_tile_reg *tile,
784 struct nouveau_fence *fence);
6ee73861
BS		 785extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
786 uint32_t size, uint32_t flags,
787 uint64_t phys);
788extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
789 uint32_t size);
790
791/* nouveau_notifier.c */
792extern int nouveau_notifier_init_channel(struct nouveau_channel *);
793extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
794extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
795 int cout, uint32_t *offset);
796extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
797extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
798 struct drm_file *);
799extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
800 struct drm_file *);
801
802/* nouveau_channel.c */
803extern struct drm_ioctl_desc nouveau_ioctls[];
804extern int nouveau_max_ioctl;
805extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
806extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
807 int channel);
808extern int nouveau_channel_alloc(struct drm_device *dev,
809 struct nouveau_channel **chan,
810 struct drm_file *file_priv,
811 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
812extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 813
814/* nouveau_object.c */
815extern int nouveau_gpuobj_early_init(struct drm_device *);
816extern int nouveau_gpuobj_init(struct drm_device *);
817extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 818extern int nouveau_gpuobj_suspend(struct drm_device *dev);
819extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
820extern void nouveau_gpuobj_resume(struct drm_device *dev);
821extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
822 uint32_t vram_h, uint32_t tt_h);
823extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
824extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
825 uint32_t size, int align, uint32_t flags,
826 struct nouveau_gpuobj **);
a8eaebc6
BS		 827extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
828 struct nouveau_gpuobj **);
43efc9ce
BS		 829extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
830 u32 size, u32 flags,
a8eaebc6 831 struct nouveau_gpuobj **);
6ee73861
BS		 832extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
833 uint64_t offset, uint64_t size, int access,
834 int target, struct nouveau_gpuobj **);
835extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
836 uint64_t offset, uint64_t size,
837 int access, struct nouveau_gpuobj **,
838 uint32_t *o_ret);
839extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
840 struct nouveau_gpuobj **);
f03a314b
FJ		 841extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
842 struct nouveau_gpuobj **);
6ee73861
BS		 843extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
844 struct drm_file *);
845extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
846 struct drm_file *);
847
848/* nouveau_irq.c */
849extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
850extern void nouveau_irq_preinstall(struct drm_device *);
851extern int nouveau_irq_postinstall(struct drm_device *);
852extern void nouveau_irq_uninstall(struct drm_device *);
853
854/* nouveau_sgdma.c */
855extern int nouveau_sgdma_init(struct drm_device *);
856extern void nouveau_sgdma_takedown(struct drm_device *);
857extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
858 uint32_t *page);
859extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
860
861/* nouveau_debugfs.c */
862#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
863extern int nouveau_debugfs_init(struct drm_minor *);
864extern void nouveau_debugfs_takedown(struct drm_minor *);
865extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
866extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
867#else
868static inline int
869nouveau_debugfs_init(struct drm_minor *minor)
870{
871 return 0;
872}
873
874static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
875{
876}
877
878static inline int
879nouveau_debugfs_channel_init(struct nouveau_channel *chan)
880{
881 return 0;
882}
883
884static inline void
885nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
886{
887}
888#endif
889
890/* nouveau_dma.c */
75c99da6 891extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 892extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 893extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 894
895/* nouveau_acpi.c */
afeb3e11 896#define ROM_BIOS_PAGE 4096
2f41a7f1 897#if defined(CONFIG_ACPI)
6a9ee8af
DA		 898void nouveau_register_dsm_handler(void);
899void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 900int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
901bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 902int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 903#else
904static inline void nouveau_register_dsm_handler(void) {}
905static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 906static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
907static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 908static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 909#endif
6ee73861
BS		 910
911/* nouveau_backlight.c */
912#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
913extern int nouveau_backlight_init(struct drm_device *);
914extern void nouveau_backlight_exit(struct drm_device *);
915#else
916static inline int nouveau_backlight_init(struct drm_device *dev)
917{
918 return 0;
919}
920
921static inline void nouveau_backlight_exit(struct drm_device *dev) { }
922#endif
923
924/* nouveau_bios.c */
925extern int nouveau_bios_init(struct drm_device *);
926extern void nouveau_bios_takedown(struct drm_device *dev);
927extern int nouveau_run_vbios_init(struct drm_device *);
928extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
929 struct dcb_entry *);
930extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
931 enum dcb_gpio_tag);
932extern struct dcb_connector_table_entry *
933nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 934extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 935extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
936 struct pll_lims *);
937extern int nouveau_bios_run_display_table(struct drm_device *,
938 struct dcb_entry *,
939 uint32_t script, int pxclk);
940extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
941 int *length);
942extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
943extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
944extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
945 bool *dl, bool *if_is_24bit);
946extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
947 int head, int pxclk);
948extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
949 enum LVDS_script, int pxclk);
950
951/* nouveau_ttm.c */
952int nouveau_ttm_global_init(struct drm_nouveau_private *);
953void nouveau_ttm_global_release(struct drm_nouveau_private *);
954int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
955
956/* nouveau_dp.c */
957int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
958 uint8_t *data, int data_nr);
959bool nouveau_dp_detect(struct drm_encoder *);
960bool nouveau_dp_link_train(struct drm_encoder *);
961
962/* nv04_fb.c */
963extern int nv04_fb_init(struct drm_device *);
964extern void nv04_fb_takedown(struct drm_device *);
965
966/* nv10_fb.c */
967extern int nv10_fb_init(struct drm_device *);
968extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 969extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
970 uint32_t, uint32_t);
6ee73861 971
8bded189
FJ		 972/* nv30_fb.c */
973extern int nv30_fb_init(struct drm_device *);
974extern void nv30_fb_takedown(struct drm_device *);
975
6ee73861
BS		 976/* nv40_fb.c */
977extern int nv40_fb_init(struct drm_device *);
978extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 979extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
980 uint32_t, uint32_t);
304424e1
MK		 981/* nv50_fb.c */
982extern int nv50_fb_init(struct drm_device *);
983extern void nv50_fb_takedown(struct drm_device *);
d96773e7 984extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 985
4b223eef
BS		 986/* nvc0_fb.c */
987extern int nvc0_fb_init(struct drm_device *);
988extern void nvc0_fb_takedown(struct drm_device *);
989
6ee73861
BS		 990/* nv04_fifo.c */
991extern int nv04_fifo_init(struct drm_device *);
992extern void nv04_fifo_disable(struct drm_device *);
993extern void nv04_fifo_enable(struct drm_device *);
994extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 995extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 996extern int nv04_fifo_channel_id(struct drm_device *);
997extern int nv04_fifo_create_context(struct nouveau_channel *);
998extern void nv04_fifo_destroy_context(struct nouveau_channel *);
999extern int nv04_fifo_load_context(struct nouveau_channel *);
1000extern int nv04_fifo_unload_context(struct drm_device *);
1001
1002/* nv10_fifo.c */
1003extern int nv10_fifo_init(struct drm_device *);
1004extern int nv10_fifo_channel_id(struct drm_device *);
1005extern int nv10_fifo_create_context(struct nouveau_channel *);
1006extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1007extern int nv10_fifo_load_context(struct nouveau_channel *);
1008extern int nv10_fifo_unload_context(struct drm_device *);
1009
1010/* nv40_fifo.c */
1011extern int nv40_fifo_init(struct drm_device *);
1012extern int nv40_fifo_create_context(struct nouveau_channel *);
1013extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1014extern int nv40_fifo_load_context(struct nouveau_channel *);
1015extern int nv40_fifo_unload_context(struct drm_device *);
1016
1017/* nv50_fifo.c */
1018extern int nv50_fifo_init(struct drm_device *);
1019extern void nv50_fifo_takedown(struct drm_device *);
1020extern int nv50_fifo_channel_id(struct drm_device *);
1021extern int nv50_fifo_create_context(struct nouveau_channel *);
1022extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1023extern int nv50_fifo_load_context(struct nouveau_channel *);
1024extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1025extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1026
4b223eef
BS		 1027/* nvc0_fifo.c */
1028extern int nvc0_fifo_init(struct drm_device *);
1029extern void nvc0_fifo_takedown(struct drm_device *);
1030extern void nvc0_fifo_disable(struct drm_device *);
1031extern void nvc0_fifo_enable(struct drm_device *);
1032extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1033extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1034extern int nvc0_fifo_channel_id(struct drm_device *);
1035extern int nvc0_fifo_create_context(struct nouveau_channel *);
1036extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1037extern int nvc0_fifo_load_context(struct nouveau_channel *);
1038extern int nvc0_fifo_unload_context(struct drm_device *);
1039
6ee73861
BS		 1040/* nv04_graph.c */
1041extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1042extern int nv04_graph_init(struct drm_device *);
1043extern void nv04_graph_takedown(struct drm_device *);
1044extern void nv04_graph_fifo_access(struct drm_device *, bool);
1045extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1046extern int nv04_graph_create_context(struct nouveau_channel *);
1047extern void nv04_graph_destroy_context(struct nouveau_channel *);
1048extern int nv04_graph_load_context(struct nouveau_channel *);
1049extern int nv04_graph_unload_context(struct drm_device *);
1050extern void nv04_graph_context_switch(struct drm_device *);
1051
1052/* nv10_graph.c */
1053extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1054extern int nv10_graph_init(struct drm_device *);
1055extern void nv10_graph_takedown(struct drm_device *);
1056extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1057extern int nv10_graph_create_context(struct nouveau_channel *);
1058extern void nv10_graph_destroy_context(struct nouveau_channel *);
1059extern int nv10_graph_load_context(struct nouveau_channel *);
1060extern int nv10_graph_unload_context(struct drm_device *);
1061extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1062extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1063 uint32_t, uint32_t);
6ee73861
BS		 1064
1065/* nv20_graph.c */
1066extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1067extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1068extern int nv20_graph_create_context(struct nouveau_channel *);
1069extern void nv20_graph_destroy_context(struct nouveau_channel *);
1070extern int nv20_graph_load_context(struct nouveau_channel *);
1071extern int nv20_graph_unload_context(struct drm_device *);
1072extern int nv20_graph_init(struct drm_device *);
1073extern void nv20_graph_takedown(struct drm_device *);
1074extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1075extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1076 uint32_t, uint32_t);
6ee73861
BS		 1077
1078/* nv40_graph.c */
1079extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1080extern int nv40_graph_init(struct drm_device *);
1081extern void nv40_graph_takedown(struct drm_device *);
1082extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1083extern int nv40_graph_create_context(struct nouveau_channel *);
1084extern void nv40_graph_destroy_context(struct nouveau_channel *);
1085extern int nv40_graph_load_context(struct nouveau_channel *);
1086extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1087extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1088extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1089 uint32_t, uint32_t);
6ee73861
BS		 1090
1091/* nv50_graph.c */
1092extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1093extern int nv50_graph_init(struct drm_device *);
1094extern void nv50_graph_takedown(struct drm_device *);
1095extern void nv50_graph_fifo_access(struct drm_device *, bool);
1096extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1097extern int nv50_graph_create_context(struct nouveau_channel *);
1098extern void nv50_graph_destroy_context(struct nouveau_channel *);
1099extern int nv50_graph_load_context(struct nouveau_channel *);
1100extern int nv50_graph_unload_context(struct drm_device *);
1101extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1102extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1103extern void nv50_graph_tlb_flush(struct drm_device *dev);
1104extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1105
4b223eef
BS		 1106/* nvc0_graph.c */
1107extern int nvc0_graph_init(struct drm_device *);
1108extern void nvc0_graph_takedown(struct drm_device *);
1109extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1110extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1111extern int nvc0_graph_create_context(struct nouveau_channel *);
1112extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1113extern int nvc0_graph_load_context(struct nouveau_channel *);
1114extern int nvc0_graph_unload_context(struct drm_device *);
1115
6ee73861
BS		 1116/* nv04_instmem.c */
1117extern int nv04_instmem_init(struct drm_device *);
1118extern void nv04_instmem_takedown(struct drm_device *);
1119extern int nv04_instmem_suspend(struct drm_device *);
1120extern void nv04_instmem_resume(struct drm_device *);
1121extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1122 uint32_t *size);
1123extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1124extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1125extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1126extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1127
1128/* nv50_instmem.c */
1129extern int nv50_instmem_init(struct drm_device *);
1130extern void nv50_instmem_takedown(struct drm_device *);
1131extern int nv50_instmem_suspend(struct drm_device *);
1132extern void nv50_instmem_resume(struct drm_device *);
1133extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1134 uint32_t *size);
1135extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1136extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1137extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1138extern void nv50_instmem_flush(struct drm_device *);
734ee835 1139extern void nv84_instmem_flush(struct drm_device *);
63187215 1140extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1141
4b223eef
BS		 1142/* nvc0_instmem.c */
1143extern int nvc0_instmem_init(struct drm_device *);
1144extern void nvc0_instmem_takedown(struct drm_device *);
1145extern int nvc0_instmem_suspend(struct drm_device *);
1146extern void nvc0_instmem_resume(struct drm_device *);
1147extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1148 uint32_t *size);
1149extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1150extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1151extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1152extern void nvc0_instmem_flush(struct drm_device *);
1153
6ee73861
BS		 1154/* nv04_mc.c */
1155extern int nv04_mc_init(struct drm_device *);
1156extern void nv04_mc_takedown(struct drm_device *);
1157
1158/* nv40_mc.c */
1159extern int nv40_mc_init(struct drm_device *);
1160extern void nv40_mc_takedown(struct drm_device *);
1161
1162/* nv50_mc.c */
1163extern int nv50_mc_init(struct drm_device *);
1164extern void nv50_mc_takedown(struct drm_device *);
1165
1166/* nv04_timer.c */
1167extern int nv04_timer_init(struct drm_device *);
1168extern uint64_t nv04_timer_read(struct drm_device *);
1169extern void nv04_timer_takedown(struct drm_device *);
1170
1171extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1172 unsigned long arg);
1173
1174/* nv04_dac.c */
8f1a6086 1175extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1176extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1177extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1178extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1179extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1180
1181/* nv04_dfp.c */
8f1a6086 1182extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1183extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1184extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1185 int head, bool dl);
1186extern void nv04_dfp_disable(struct drm_device *dev, int head);
1187extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1188
1189/* nv04_tv.c */
1190extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1191extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1192
1193/* nv17_tv.c */
8f1a6086 1194extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1195
1196/* nv04_display.c */
c88c2e06
FJ		 1197extern int nv04_display_early_init(struct drm_device *);
1198extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1199extern int nv04_display_create(struct drm_device *);
c88c2e06 1200extern int nv04_display_init(struct drm_device *);
6ee73861 1201extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1202
1203/* nv04_crtc.c */
1204extern int nv04_crtc_create(struct drm_device *, int index);
1205
1206/* nouveau_bo.c */
1207extern struct ttm_bo_driver nouveau_bo_driver;
1208extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1209 int size, int align, uint32_t flags,
1210 uint32_t tile_mode, uint32_t tile_flags,
1211 bool no_vm, bool mappable, struct nouveau_bo **);
1212extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1213extern int nouveau_bo_unpin(struct nouveau_bo *);
1214extern int nouveau_bo_map(struct nouveau_bo *);
1215extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1216extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1217 uint32_t busy);
6ee73861
BS		 1218extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1219extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1220extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1221extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1222
1223/* nouveau_fence.c */
1224struct nouveau_fence;
0c6c1c2f
FJ		 1225extern int nouveau_fence_init(struct drm_device *);
1226extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1227extern int nouveau_fence_channel_init(struct nouveau_channel *);
1228extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1229extern void nouveau_fence_update(struct nouveau_channel *);
1230extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1231 bool emit);
1232extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1233extern void nouveau_fence_work(struct nouveau_fence *fence,
1234 void (*work)(void *priv, bool signalled),
1235 void *priv);
6ee73861
BS		 1236struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1237extern bool nouveau_fence_signalled(void *obj, void *arg);
1238extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
2730723b 1239extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
6ee73861
BS		 1240extern int nouveau_fence_flush(void *obj, void *arg);
1241extern void nouveau_fence_unref(void **obj);
1242extern void *nouveau_fence_ref(void *obj);
6ee73861
BS		 1243
1244/* nouveau_gem.c */
1245extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1246 int size, int align, uint32_t flags,
1247 uint32_t tile_mode, uint32_t tile_flags,
1248 bool no_vm, bool mappable, struct nouveau_bo **);
1249extern int nouveau_gem_object_new(struct drm_gem_object *);
1250extern void nouveau_gem_object_del(struct drm_gem_object *);
1251extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1252 struct drm_file *);
1253extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1254 struct drm_file *);
6ee73861
BS		 1255extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1256 struct drm_file *);
1257extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1258 struct drm_file *);
1259extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1260 struct drm_file *);
1261
ee2e0131
BS		 1262/* nv10_gpio.c */
1263int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1264int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1265
45284162 1266/* nv50_gpio.c */
ee2e0131 1267int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1268int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1269int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1270void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1271
e9ebb68b
BS		 1272/* nv50_calc. */
1273int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1274 int *N1, int *M1, int *N2, int *M2, int *P);
1275int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1276 int clk, int *N, int *fN, int *M, int *P);
1277
6ee73861
BS		 1278#ifndef ioread32_native
1279#ifdef __BIG_ENDIAN
1280#define ioread16_native ioread16be
1281#define iowrite16_native iowrite16be
1282#define ioread32_native ioread32be
1283#define iowrite32_native iowrite32be
1284#else /* def __BIG_ENDIAN */
1285#define ioread16_native ioread16
1286#define iowrite16_native iowrite16
1287#define ioread32_native ioread32
1288#define iowrite32_native iowrite32
1289#endif /* def __BIG_ENDIAN else */
1290#endif /* !ioread32_native */
1291
1292/* channel control reg access */
1293static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1294{
1295 return ioread32_native(chan->user + reg);
1296}
1297
1298static inline void nvchan_wr32(struct nouveau_channel *chan,
1299 unsigned reg, u32 val)
1300{
1301 iowrite32_native(val, chan->user + reg);
1302}
1303
1304/* register access */
1305static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1306{
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 return ioread32_native(dev_priv->mmio + reg);
1309}
1310
1311static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1312{
1313 struct drm_nouveau_private *dev_priv = dev->dev_private;
1314 iowrite32_native(val, dev_priv->mmio + reg);
1315}
1316
2a7fdb2b 1317static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1318{
1319 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1320 nv_wr32(dev, reg, (tmp & ~mask) | val);
1321 return tmp;
49eed80a
BS		 1322}
1323
6ee73861
BS		 1324static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1325{
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 return ioread8(dev_priv->mmio + reg);
1328}
1329
1330static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1331{
1332 struct drm_nouveau_private *dev_priv = dev->dev_private;
1333 iowrite8(val, dev_priv->mmio + reg);
1334}
1335
4b5c152a 1336#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1337 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1338
1339/* PRAMIN access */
1340static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1341{
1342 struct drm_nouveau_private *dev_priv = dev->dev_private;
1343 return ioread32_native(dev_priv->ramin + offset);
1344}
1345
1346static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1347{
1348 struct drm_nouveau_private *dev_priv = dev->dev_private;
1349 iowrite32_native(val, dev_priv->ramin + offset);
1350}
1351
1352/* object access */
b3beb167
BS		 1353extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1354extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1355
1356/*
1357 * Logging
1358 * Argument d is (struct drm_device *).
1359 */
1360#define NV_PRINTK(level, d, fmt, arg...) \
1361 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1362 pci_name(d->pdev), ##arg)
1363#ifndef NV_DEBUG_NOTRACE
1364#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1365 if (drm_debug & DRM_UT_DRIVER) { \
1366 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1367 __LINE__, ##arg); \
1368 } \
1369} while (0)
1370#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1371 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1372 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1373 __LINE__, ##arg); \
1374 } \
1375} while (0)
1376#else
1377#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1378 if (drm_debug & DRM_UT_DRIVER) \
1379 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1380} while (0)
1381#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1382 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1383 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1384} while (0)
1385#endif
1386#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1387#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1388#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1389#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1390#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1391
1392/* nouveau_reg_debug bitmask */
1393enum {
1394 NOUVEAU_REG_DEBUG_MC = 0x1,
1395 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1396 NOUVEAU_REG_DEBUG_FB = 0x4,
1397 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1398 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1399 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1400 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1401 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1402 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1403 NOUVEAU_REG_DEBUG_EVO = 0x200,
1404};
1405
1406#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1407 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1408 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1409} while (0)
1410
1411static inline bool
1412nv_two_heads(struct drm_device *dev)
1413{
1414 struct drm_nouveau_private *dev_priv = dev->dev_private;
1415 const int impl = dev->pci_device & 0x0ff0;
1416
1417 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1418 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1419 return true;
1420
1421 return false;
1422}
1423
1424static inline bool
1425nv_gf4_disp_arch(struct drm_device *dev)
1426{
1427 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1428}
1429
1430static inline bool
1431nv_two_reg_pll(struct drm_device *dev)
1432{
1433 struct drm_nouveau_private *dev_priv = dev->dev_private;
1434 const int impl = dev->pci_device & 0x0ff0;
1435
1436 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1437 return true;
1438 return false;
1439}
1440
acae116c
FJ		 1441static inline bool
1442nv_match_device(struct drm_device *dev, unsigned device,
1443 unsigned sub_vendor, unsigned sub_device)
1444{
1445 return dev->pdev->device == device &&
1446 dev->pdev->subsystem_vendor == sub_vendor &&
1447 dev->pdev->subsystem_device == sub_device;
1448}
1449
f03a314b
FJ		 1450#define NV_SW 0x0000506e
1451#define NV_SW_DMA_SEMAPHORE 0x00000060
1452#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1453#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1454#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1455#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1456#define NV_SW_DMA_VBLSEM 0x0000018c
1457#define NV_SW_VBLSEM_OFFSET 0x00000400
1458#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1459#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1460
1461#endif /* __NOUVEAU_DRV_H__ */
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