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drm/nv04-nv40: import initial pm backend
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
6ee73861
BS		 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 138struct nouveau_gpuobj {
b3beb167 139 struct drm_device *dev;
eb9bcbdc 140 struct kref refcount;
6ee73861
BS		 141 struct list_head list;
142
b833ac26 143 struct drm_mm_node *im_pramin;
6ee73861 144 struct nouveau_bo *im_backing;
6ee73861
BS		 145 uint32_t *im_backing_suspend;
146 int im_bound;
147
148 uint32_t flags;
6ee73861 149
43efc9ce 150 u32 size;
de3a6c0a
BS		 151 u32 pinst;
152 u32 cinst;
153 u64 vinst;
154
6ee73861
BS		 155 uint32_t engine;
156 uint32_t class;
157
158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
159 void *priv;
160};
161
6ee73861
BS		 162struct nouveau_channel {
163 struct drm_device *dev;
164 int id;
165
166 /* owner of this fifo */
167 struct drm_file *file_priv;
168 /* mapping of the fifo itself */
169 struct drm_local_map *map;
170
171 /* mapping of the regs controling the fifo */
172 void __iomem *user;
173 uint32_t user_get;
174 uint32_t user_put;
175
176 /* Fencing */
177 struct {
178 /* lock protects the pending list only */
179 spinlock_t lock;
180 struct list_head pending;
181 uint32_t sequence;
182 uint32_t sequence_ack;
047d1d3c 183 atomic_t last_sequence_irq;
6ee73861
BS		 184 } fence;
185
186 /* DMA push buffer */
a8eaebc6
BS		 187 struct nouveau_gpuobj *pushbuf;
188 struct nouveau_bo *pushbuf_bo;
189 uint32_t pushbuf_base;
6ee73861
BS		 190
191 /* Notifier memory */
192 struct nouveau_bo *notifier_bo;
b833ac26 193 struct drm_mm notifier_heap;
6ee73861
BS		 194
195 /* PFIFO context */
a8eaebc6
BS		 196 struct nouveau_gpuobj *ramfc;
197 struct nouveau_gpuobj *cache;
6ee73861
BS		 198
199 /* PGRAPH context */
200 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 201 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 202 void *pgraph_ctx;
203
204 /* NV50 VM */
a8eaebc6
BS		 205 struct nouveau_gpuobj *vm_pd;
206 struct nouveau_gpuobj *vm_gart_pt;
207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 208
209 /* Objects */
a8eaebc6
BS		 210 struct nouveau_gpuobj *ramin; /* Private instmem */
211 struct drm_mm ramin_heap; /* Private PRAMIN heap */
212 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 213
214 /* GPU object info for stuff used in-kernel (mm_enabled) */
215 uint32_t m2mf_ntfy;
216 uint32_t vram_handle;
217 uint32_t gart_handle;
218 bool accel_done;
219
220 /* Push buffer state (only for drm's channel on !mm_enabled) */
221 struct {
222 int max;
223 int free;
224 int cur;
225 int put;
226 /* access via pushbuf_bo */
9a391ad8
BS		 227
228 int ib_base;
229 int ib_max;
230 int ib_free;
231 int ib_put;
6ee73861
BS		 232 } dma;
233
234 uint32_t sw_subchannel[8];
235
236 struct {
237 struct nouveau_gpuobj *vblsem;
238 uint32_t vblsem_offset;
239 uint32_t vblsem_rval;
240 struct list_head vbl_wait;
241 } nvsw;
242
243 struct {
244 bool active;
245 char name[32];
246 struct drm_info_list info;
247 } debugfs;
248};
249
250struct nouveau_instmem_engine {
251 void *priv;
252
253 int (*init)(struct drm_device *dev);
254 void (*takedown)(struct drm_device *dev);
255 int (*suspend)(struct drm_device *dev);
256 void (*resume)(struct drm_device *dev);
257
258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
259 uint32_t *size);
260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 263 void (*flush)(struct drm_device *);
6ee73861
BS		 264};
265
266struct nouveau_mc_engine {
267 int (*init)(struct drm_device *dev);
268 void (*takedown)(struct drm_device *dev);
269};
270
271struct nouveau_timer_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
274 uint64_t (*read)(struct drm_device *dev);
275};
276
277struct nouveau_fb_engine {
cb00f7c1
FJ		 278 int num_tiles;
279
6ee73861
BS		 280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 282
283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
284 uint32_t size, uint32_t pitch);
6ee73861
BS		 285};
286
287struct nouveau_fifo_engine {
6ee73861
BS		 288 int channels;
289
a8eaebc6 290 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 291 int cur_playlist;
292
6ee73861
BS		 293 int (*init)(struct drm_device *);
294 void (*takedown)(struct drm_device *);
295
296 void (*disable)(struct drm_device *);
297 void (*enable)(struct drm_device *);
298 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 299 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 300
301 int (*channel_id)(struct drm_device *);
302
303 int (*create_context)(struct nouveau_channel *);
304 void (*destroy_context)(struct nouveau_channel *);
305 int (*load_context)(struct nouveau_channel *);
306 int (*unload_context)(struct drm_device *);
307};
308
309struct nouveau_pgraph_object_method {
310 int id;
311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
312 uint32_t data);
313};
314
315struct nouveau_pgraph_object_class {
316 int id;
317 bool software;
318 struct nouveau_pgraph_object_method *methods;
319};
320
321struct nouveau_pgraph_engine {
322 struct nouveau_pgraph_object_class *grclass;
323 bool accel_blocked;
054b93e4 324 int grctx_size;
6ee73861 325
c50a5681 326 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 327 struct nouveau_gpuobj *ctx_table;
c50a5681 328
6ee73861
BS		 329 int (*init)(struct drm_device *);
330 void (*takedown)(struct drm_device *);
331
332 void (*fifo_access)(struct drm_device *, bool);
333
334 struct nouveau_channel *(*channel)(struct drm_device *);
335 int (*create_context)(struct nouveau_channel *);
336 void (*destroy_context)(struct nouveau_channel *);
337 int (*load_context)(struct nouveau_channel *);
338 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 339
340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
341 uint32_t size, uint32_t pitch);
6ee73861
BS		 342};
343
c88c2e06
FJ		 344struct nouveau_display_engine {
345 int (*early_init)(struct drm_device *);
346 void (*late_takedown)(struct drm_device *);
347 int (*create)(struct drm_device *);
348 int (*init)(struct drm_device *);
349 void (*destroy)(struct drm_device *);
350};
351
ee2e0131
BS		 352struct nouveau_gpio_engine {
353 int (*init)(struct drm_device *);
354 void (*takedown)(struct drm_device *);
355
356 int (*get)(struct drm_device *, enum dcb_gpio_tag);
357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
358
359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
360};
361
330c5988
BS		 362struct nouveau_pm_voltage_level {
363 u8 voltage;
364 u8 vid;
365};
366
367struct nouveau_pm_voltage {
368 bool supported;
369 u8 vid_mask;
370
371 struct nouveau_pm_voltage_level *level;
372 int nr_level;
373};
374
375#define NOUVEAU_PM_MAX_LEVEL 8
376struct nouveau_pm_level {
377 struct device_attribute dev_attr;
378 char name[32];
379 int id;
380
381 u32 core;
382 u32 memory;
383 u32 shader;
384 u32 unk05;
385
386 u8 voltage;
387 u8 fanspeed;
388};
389
390struct nouveau_pm_engine {
391 struct nouveau_pm_voltage voltage;
392 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
393 int nr_perflvl;
394
395 struct nouveau_pm_level boot;
396 struct nouveau_pm_level *cur;
397
398 int (*clock_get)(struct drm_device *, u32 id);
399 void *(*clock_pre)(struct drm_device *, u32 id, int khz);
400 void (*clock_set)(struct drm_device *, void *);
401 int (*voltage_get)(struct drm_device *);
402 int (*voltage_set)(struct drm_device *, int voltage);
403 int (*fanspeed_get)(struct drm_device *);
404 int (*fanspeed_set)(struct drm_device *, int fanspeed);
405};
406
6ee73861
BS		 407struct nouveau_engine {
408 struct nouveau_instmem_engine instmem;
409 struct nouveau_mc_engine mc;
410 struct nouveau_timer_engine timer;
411 struct nouveau_fb_engine fb;
412 struct nouveau_pgraph_engine graph;
413 struct nouveau_fifo_engine fifo;
c88c2e06 414 struct nouveau_display_engine display;
ee2e0131 415 struct nouveau_gpio_engine gpio;
330c5988 416 struct nouveau_pm_engine pm;
6ee73861
BS		 417};
418
419struct nouveau_pll_vals {
420 union {
421 struct {
422#ifdef __BIG_ENDIAN
423 uint8_t N1, M1, N2, M2;
424#else
425 uint8_t M1, N1, M2, N2;
426#endif
427 };
428 struct {
429 uint16_t NM1, NM2;
430 } __attribute__((packed));
431 };
432 int log2P;
433
434 int refclk;
435};
436
437enum nv04_fp_display_regs {
438 FP_DISPLAY_END,
439 FP_TOTAL,
440 FP_CRTC,
441 FP_SYNC_START,
442 FP_SYNC_END,
443 FP_VALID_START,
444 FP_VALID_END
445};
446
447struct nv04_crtc_reg {
448 unsigned char MiscOutReg; /* */
4a9f822f 449 uint8_t CRTC[0xa0];
6ee73861
BS		 450 uint8_t CR58[0x10];
451 uint8_t Sequencer[5];
452 uint8_t Graphics[9];
453 uint8_t Attribute[21];
454 unsigned char DAC[768]; /* Internal Colorlookuptable */
455
456 /* PCRTC regs */
457 uint32_t fb_start;
458 uint32_t crtc_cfg;
459 uint32_t cursor_cfg;
460 uint32_t gpio_ext;
461 uint32_t crtc_830;
462 uint32_t crtc_834;
463 uint32_t crtc_850;
464 uint32_t crtc_eng_ctrl;
465
466 /* PRAMDAC regs */
467 uint32_t nv10_cursync;
468 struct nouveau_pll_vals pllvals;
469 uint32_t ramdac_gen_ctrl;
470 uint32_t ramdac_630;
471 uint32_t ramdac_634;
472 uint32_t tv_setup;
473 uint32_t tv_vtotal;
474 uint32_t tv_vskew;
475 uint32_t tv_vsync_delay;
476 uint32_t tv_htotal;
477 uint32_t tv_hskew;
478 uint32_t tv_hsync_delay;
479 uint32_t tv_hsync_delay2;
480 uint32_t fp_horiz_regs[7];
481 uint32_t fp_vert_regs[7];
482 uint32_t dither;
483 uint32_t fp_control;
484 uint32_t dither_regs[6];
485 uint32_t fp_debug_0;
486 uint32_t fp_debug_1;
487 uint32_t fp_debug_2;
488 uint32_t fp_margin_color;
489 uint32_t ramdac_8c0;
490 uint32_t ramdac_a20;
491 uint32_t ramdac_a24;
492 uint32_t ramdac_a34;
493 uint32_t ctv_regs[38];
494};
495
496struct nv04_output_reg {
497 uint32_t output;
498 int head;
499};
500
501struct nv04_mode_state {
502 uint32_t bpp;
503 uint32_t width;
504 uint32_t height;
505 uint32_t interlace;
506 uint32_t repaint0;
507 uint32_t repaint1;
508 uint32_t screen;
509 uint32_t scale;
510 uint32_t dither;
511 uint32_t extra;
512 uint32_t fifo;
513 uint32_t pixel;
514 uint32_t horiz;
515 int arbitration0;
516 int arbitration1;
517 uint32_t pll;
518 uint32_t pllB;
519 uint32_t vpll;
520 uint32_t vpll2;
521 uint32_t vpllB;
522 uint32_t vpll2B;
523 uint32_t pllsel;
524 uint32_t sel_clk;
525 uint32_t general;
526 uint32_t crtcOwner;
527 uint32_t head;
528 uint32_t head2;
529 uint32_t cursorConfig;
530 uint32_t cursor0;
531 uint32_t cursor1;
532 uint32_t cursor2;
533 uint32_t timingH;
534 uint32_t timingV;
535 uint32_t displayV;
536 uint32_t crtcSync;
537
538 struct nv04_crtc_reg crtc_reg[2];
539};
540
541enum nouveau_card_type {
542 NV_04 = 0x00,
543 NV_10 = 0x10,
544 NV_20 = 0x20,
545 NV_30 = 0x30,
546 NV_40 = 0x40,
547 NV_50 = 0x50,
4b223eef 548 NV_C0 = 0xc0,
6ee73861
BS		 549};
550
551struct drm_nouveau_private {
552 struct drm_device *dev;
6ee73861
BS		 553
554 /* the card type, takes NV_* as values */
555 enum nouveau_card_type card_type;
556 /* exact chipset, derived from NV_PMC_BOOT_0 */
557 int chipset;
558 int flags;
559
560 void __iomem *mmio;
5125bfd8 561
e05d7eae 562 spinlock_t ramin_lock;
6ee73861 563 void __iomem *ramin;
5125bfd8
BS		 564 u32 ramin_size;
565 u32 ramin_base;
566 bool ramin_available;
e05d7eae
BS		 567 struct drm_mm ramin_heap;
568 struct list_head gpuobj_list;
6ee73861 569
ac8fb975
BS		 570 struct nouveau_bo *vga_ram;
571
6ee73861
BS		 572 struct workqueue_struct *wq;
573 struct work_struct irq_work;
a5acac66 574 struct work_struct hpd_work;
6ee73861
BS		 575
576 struct list_head vbl_waiting;
577
578 struct {
ba4420c2 579 struct drm_global_reference mem_global_ref;
6ee73861
BS		 580 struct ttm_bo_global_ref bo_global_ref;
581 struct ttm_bo_device bdev;
6ee73861
BS		 582 atomic_t validate_sequence;
583 } ttm;
584
6ee73861
BS		 585 int fifo_alloc_count;
586 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
587
588 struct nouveau_engine engine;
589 struct nouveau_channel *channel;
590
ff9e5279
MM		 591 /* For PFIFO and PGRAPH. */
592 spinlock_t context_switch_lock;
593
6ee73861 594 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 595 struct nouveau_ramht *ramht;
596 struct nouveau_gpuobj *ramfc;
597 struct nouveau_gpuobj *ramro;
598
6ee73861 599 uint32_t ramin_rsvd_vram;
6ee73861 600
6ee73861
BS		 601 struct {
602 enum {
603 NOUVEAU_GART_NONE = 0,
604 NOUVEAU_GART_AGP,
605 NOUVEAU_GART_SGDMA
606 } type;
607 uint64_t aper_base;
608 uint64_t aper_size;
609 uint64_t aper_free;
610
611 struct nouveau_gpuobj *sg_ctxdma;
612 struct page *sg_dummy_page;
613 dma_addr_t sg_dummy_bus;
6ee73861
BS		 614 } gart_info;
615
a0af9add 616 /* nv10-nv40 tiling regions */
9f56b126 617 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 618
a76fb4e8
BS		 619 /* VRAM/fb configuration */
620 uint64_t vram_size;
621 uint64_t vram_sys_base;
6c3d7ef2 622 u32 vram_rblock_size;
a76fb4e8
BS		 623
624 uint64_t fb_phys;
625 uint64_t fb_available_size;
626 uint64_t fb_mappable_pages;
627 uint64_t fb_aper_free;
628 int fb_mtrr;
629
6ee73861
BS		 630 /* G8x/G9x virtual address space */
631 uint64_t vm_gart_base;
632 uint64_t vm_gart_size;
633 uint64_t vm_vram_base;
634 uint64_t vm_vram_size;
635 uint64_t vm_end;
636 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
637 int vm_vram_pt_nr;
6ee73861 638
04a39c57 639 struct nvbios vbios;
6ee73861
BS		 640
641 struct nv04_mode_state mode_reg;
642 struct nv04_mode_state saved_reg;
643 uint32_t saved_vga_font[4][16384];
644 uint32_t crtc_owner;
645 uint32_t dac_users[4];
646
647 struct nouveau_suspend_resume {
6ee73861 648 uint32_t *ramin_copy;
6ee73861
BS		 649 } susres;
650
651 struct backlight_device *backlight;
6ee73861
BS		 652
653 struct nouveau_channel *evo;
87c0e0e5
BS		 654 struct {
655 struct dcb_entry *dcb;
656 u16 script;
657 u32 pclk;
658 } evo_irq;
6ee73861
BS		 659
660 struct {
661 struct dentry *channel_root;
662 } debugfs;
38651674 663
8be48d92 664 struct nouveau_fbdev *nfbdev;
06415c56 665 struct apertures_struct *apertures;
6ee73861
BS		 666};
667
668static inline struct drm_nouveau_private *
669nouveau_bdev(struct ttm_bo_device *bd)
670{
671 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
672}
673
674static inline int
675nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
676{
677 struct nouveau_bo *prev;
678
679 if (!pnvbo)
680 return -EINVAL;
681 prev = *pnvbo;
682
683 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
684 if (prev) {
685 struct ttm_buffer_object *bo = &prev->bo;
686
687 ttm_bo_unref(&bo);
688 }
689
690 return 0;
691}
692
6ee73861
BS		 693#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
694 struct drm_nouveau_private *nv = dev->dev_private; \
695 if (!nouveau_channel_owner(dev, (cl), (id))) { \
696 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
697 DRM_CURRENTPID, (id)); \
698 return -EPERM; \
699 } \
700 (ch) = nv->fifos[(id)]; \
701} while (0)
702
703/* nouveau_drv.c */
de5899bd 704extern int nouveau_agpmode;
6ee73861
BS		 705extern int nouveau_duallink;
706extern int nouveau_uscript_lvds;
707extern int nouveau_uscript_tmds;
708extern int nouveau_vram_pushbuf;
709extern int nouveau_vram_notify;
710extern int nouveau_fbpercrtc;
f4053509 711extern int nouveau_tv_disable;
6ee73861
BS		 712extern char *nouveau_tv_norm;
713extern int nouveau_reg_debug;
714extern char *nouveau_vbios;
a1470890 715extern int nouveau_ignorelid;
a32ed69d
MK		 716extern int nouveau_nofbaccel;
717extern int nouveau_noaccel;
da647d5b 718extern int nouveau_override_conntype;
6ee73861 719
6a9ee8af
DA		 720extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
721extern int nouveau_pci_resume(struct pci_dev *pdev);
722
6ee73861
BS		 723/* nouveau_state.c */
724extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
725extern int nouveau_load(struct drm_device *, unsigned long flags);
726extern int nouveau_firstopen(struct drm_device *);
727extern void nouveau_lastclose(struct drm_device *);
728extern int nouveau_unload(struct drm_device *);
729extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
730 struct drm_file *);
731extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
732 struct drm_file *);
733extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
734 uint32_t reg, uint32_t mask, uint32_t val);
735extern bool nouveau_wait_for_idle(struct drm_device *);
736extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 737
738/* nouveau_mem.c */
fbd2895e
BS		 739extern int nouveau_mem_vram_init(struct drm_device *);
740extern void nouveau_mem_vram_fini(struct drm_device *);
741extern int nouveau_mem_gart_init(struct drm_device *);
742extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 743extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 744extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 745extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 746extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
747 uint32_t addr,
748 uint32_t size,
749 uint32_t pitch);
750extern void nv10_mem_expire_tiling(struct drm_device *dev,
751 struct nouveau_tile_reg *tile,
752 struct nouveau_fence *fence);
6ee73861
BS		 753extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
754 uint32_t size, uint32_t flags,
755 uint64_t phys);
756extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
757 uint32_t size);
758
759/* nouveau_notifier.c */
760extern int nouveau_notifier_init_channel(struct nouveau_channel *);
761extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
762extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
763 int cout, uint32_t *offset);
764extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
765extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
766 struct drm_file *);
767extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
768 struct drm_file *);
769
770/* nouveau_channel.c */
771extern struct drm_ioctl_desc nouveau_ioctls[];
772extern int nouveau_max_ioctl;
773extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
774extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
775 int channel);
776extern int nouveau_channel_alloc(struct drm_device *dev,
777 struct nouveau_channel **chan,
778 struct drm_file *file_priv,
779 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
780extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 781
782/* nouveau_object.c */
783extern int nouveau_gpuobj_early_init(struct drm_device *);
784extern int nouveau_gpuobj_init(struct drm_device *);
785extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 786extern int nouveau_gpuobj_suspend(struct drm_device *dev);
787extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
788extern void nouveau_gpuobj_resume(struct drm_device *dev);
789extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
790 uint32_t vram_h, uint32_t tt_h);
791extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
792extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
793 uint32_t size, int align, uint32_t flags,
794 struct nouveau_gpuobj **);
a8eaebc6
BS		 795extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
796 struct nouveau_gpuobj **);
43efc9ce
BS		 797extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
798 u32 size, u32 flags,
a8eaebc6 799 struct nouveau_gpuobj **);
6ee73861
BS		 800extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
801 uint64_t offset, uint64_t size, int access,
802 int target, struct nouveau_gpuobj **);
803extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
804 uint64_t offset, uint64_t size,
805 int access, struct nouveau_gpuobj **,
806 uint32_t *o_ret);
807extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
808 struct nouveau_gpuobj **);
f03a314b
FJ		 809extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
810 struct nouveau_gpuobj **);
6ee73861
BS		 811extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
812 struct drm_file *);
813extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
814 struct drm_file *);
815
816/* nouveau_irq.c */
817extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
818extern void nouveau_irq_preinstall(struct drm_device *);
819extern int nouveau_irq_postinstall(struct drm_device *);
820extern void nouveau_irq_uninstall(struct drm_device *);
821
822/* nouveau_sgdma.c */
823extern int nouveau_sgdma_init(struct drm_device *);
824extern void nouveau_sgdma_takedown(struct drm_device *);
825extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
826 uint32_t *page);
827extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
828
829/* nouveau_debugfs.c */
830#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
831extern int nouveau_debugfs_init(struct drm_minor *);
832extern void nouveau_debugfs_takedown(struct drm_minor *);
833extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
834extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
835#else
836static inline int
837nouveau_debugfs_init(struct drm_minor *minor)
838{
839 return 0;
840}
841
842static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
843{
844}
845
846static inline int
847nouveau_debugfs_channel_init(struct nouveau_channel *chan)
848{
849 return 0;
850}
851
852static inline void
853nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
854{
855}
856#endif
857
858/* nouveau_dma.c */
75c99da6 859extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 860extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 861extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 862
863/* nouveau_acpi.c */
afeb3e11 864#define ROM_BIOS_PAGE 4096
2f41a7f1 865#if defined(CONFIG_ACPI)
6a9ee8af
DA		 866void nouveau_register_dsm_handler(void);
867void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 868int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
869bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 870int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 871#else
872static inline void nouveau_register_dsm_handler(void) {}
873static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 874static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
875static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 876static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 877#endif
6ee73861
BS		 878
879/* nouveau_backlight.c */
880#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
881extern int nouveau_backlight_init(struct drm_device *);
882extern void nouveau_backlight_exit(struct drm_device *);
883#else
884static inline int nouveau_backlight_init(struct drm_device *dev)
885{
886 return 0;
887}
888
889static inline void nouveau_backlight_exit(struct drm_device *dev) { }
890#endif
891
892/* nouveau_bios.c */
893extern int nouveau_bios_init(struct drm_device *);
894extern void nouveau_bios_takedown(struct drm_device *dev);
895extern int nouveau_run_vbios_init(struct drm_device *);
896extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
897 struct dcb_entry *);
898extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
899 enum dcb_gpio_tag);
900extern struct dcb_connector_table_entry *
901nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 902extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 903extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
904 struct pll_lims *);
905extern int nouveau_bios_run_display_table(struct drm_device *,
906 struct dcb_entry *,
907 uint32_t script, int pxclk);
908extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
909 int *length);
910extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
911extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
912extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
913 bool *dl, bool *if_is_24bit);
914extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
915 int head, int pxclk);
916extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
917 enum LVDS_script, int pxclk);
918
919/* nouveau_ttm.c */
920int nouveau_ttm_global_init(struct drm_nouveau_private *);
921void nouveau_ttm_global_release(struct drm_nouveau_private *);
922int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
923
924/* nouveau_dp.c */
925int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
926 uint8_t *data, int data_nr);
927bool nouveau_dp_detect(struct drm_encoder *);
928bool nouveau_dp_link_train(struct drm_encoder *);
929
930/* nv04_fb.c */
931extern int nv04_fb_init(struct drm_device *);
932extern void nv04_fb_takedown(struct drm_device *);
933
934/* nv10_fb.c */
935extern int nv10_fb_init(struct drm_device *);
936extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 937extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
938 uint32_t, uint32_t);
6ee73861 939
8bded189
FJ		 940/* nv30_fb.c */
941extern int nv30_fb_init(struct drm_device *);
942extern void nv30_fb_takedown(struct drm_device *);
943
6ee73861
BS		 944/* nv40_fb.c */
945extern int nv40_fb_init(struct drm_device *);
946extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 947extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
948 uint32_t, uint32_t);
304424e1
MK		 949/* nv50_fb.c */
950extern int nv50_fb_init(struct drm_device *);
951extern void nv50_fb_takedown(struct drm_device *);
d96773e7 952extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 953
4b223eef
BS		 954/* nvc0_fb.c */
955extern int nvc0_fb_init(struct drm_device *);
956extern void nvc0_fb_takedown(struct drm_device *);
957
6ee73861
BS		 958/* nv04_fifo.c */
959extern int nv04_fifo_init(struct drm_device *);
960extern void nv04_fifo_disable(struct drm_device *);
961extern void nv04_fifo_enable(struct drm_device *);
962extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 963extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 964extern int nv04_fifo_channel_id(struct drm_device *);
965extern int nv04_fifo_create_context(struct nouveau_channel *);
966extern void nv04_fifo_destroy_context(struct nouveau_channel *);
967extern int nv04_fifo_load_context(struct nouveau_channel *);
968extern int nv04_fifo_unload_context(struct drm_device *);
969
970/* nv10_fifo.c */
971extern int nv10_fifo_init(struct drm_device *);
972extern int nv10_fifo_channel_id(struct drm_device *);
973extern int nv10_fifo_create_context(struct nouveau_channel *);
974extern void nv10_fifo_destroy_context(struct nouveau_channel *);
975extern int nv10_fifo_load_context(struct nouveau_channel *);
976extern int nv10_fifo_unload_context(struct drm_device *);
977
978/* nv40_fifo.c */
979extern int nv40_fifo_init(struct drm_device *);
980extern int nv40_fifo_create_context(struct nouveau_channel *);
981extern void nv40_fifo_destroy_context(struct nouveau_channel *);
982extern int nv40_fifo_load_context(struct nouveau_channel *);
983extern int nv40_fifo_unload_context(struct drm_device *);
984
985/* nv50_fifo.c */
986extern int nv50_fifo_init(struct drm_device *);
987extern void nv50_fifo_takedown(struct drm_device *);
988extern int nv50_fifo_channel_id(struct drm_device *);
989extern int nv50_fifo_create_context(struct nouveau_channel *);
990extern void nv50_fifo_destroy_context(struct nouveau_channel *);
991extern int nv50_fifo_load_context(struct nouveau_channel *);
992extern int nv50_fifo_unload_context(struct drm_device *);
993
4b223eef
BS		 994/* nvc0_fifo.c */
995extern int nvc0_fifo_init(struct drm_device *);
996extern void nvc0_fifo_takedown(struct drm_device *);
997extern void nvc0_fifo_disable(struct drm_device *);
998extern void nvc0_fifo_enable(struct drm_device *);
999extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1000extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1001extern int nvc0_fifo_channel_id(struct drm_device *);
1002extern int nvc0_fifo_create_context(struct nouveau_channel *);
1003extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1004extern int nvc0_fifo_load_context(struct nouveau_channel *);
1005extern int nvc0_fifo_unload_context(struct drm_device *);
1006
6ee73861
BS		 1007/* nv04_graph.c */
1008extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1009extern int nv04_graph_init(struct drm_device *);
1010extern void nv04_graph_takedown(struct drm_device *);
1011extern void nv04_graph_fifo_access(struct drm_device *, bool);
1012extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1013extern int nv04_graph_create_context(struct nouveau_channel *);
1014extern void nv04_graph_destroy_context(struct nouveau_channel *);
1015extern int nv04_graph_load_context(struct nouveau_channel *);
1016extern int nv04_graph_unload_context(struct drm_device *);
1017extern void nv04_graph_context_switch(struct drm_device *);
1018
1019/* nv10_graph.c */
1020extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1021extern int nv10_graph_init(struct drm_device *);
1022extern void nv10_graph_takedown(struct drm_device *);
1023extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1024extern int nv10_graph_create_context(struct nouveau_channel *);
1025extern void nv10_graph_destroy_context(struct nouveau_channel *);
1026extern int nv10_graph_load_context(struct nouveau_channel *);
1027extern int nv10_graph_unload_context(struct drm_device *);
1028extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1029extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1030 uint32_t, uint32_t);
6ee73861
BS		 1031
1032/* nv20_graph.c */
1033extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1034extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1035extern int nv20_graph_create_context(struct nouveau_channel *);
1036extern void nv20_graph_destroy_context(struct nouveau_channel *);
1037extern int nv20_graph_load_context(struct nouveau_channel *);
1038extern int nv20_graph_unload_context(struct drm_device *);
1039extern int nv20_graph_init(struct drm_device *);
1040extern void nv20_graph_takedown(struct drm_device *);
1041extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1042extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1043 uint32_t, uint32_t);
6ee73861
BS		 1044
1045/* nv40_graph.c */
1046extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1047extern int nv40_graph_init(struct drm_device *);
1048extern void nv40_graph_takedown(struct drm_device *);
1049extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1050extern int nv40_graph_create_context(struct nouveau_channel *);
1051extern void nv40_graph_destroy_context(struct nouveau_channel *);
1052extern int nv40_graph_load_context(struct nouveau_channel *);
1053extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1054extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1055extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1056 uint32_t, uint32_t);
6ee73861
BS		 1057
1058/* nv50_graph.c */
1059extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1060extern int nv50_graph_init(struct drm_device *);
1061extern void nv50_graph_takedown(struct drm_device *);
1062extern void nv50_graph_fifo_access(struct drm_device *, bool);
1063extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1064extern int nv50_graph_create_context(struct nouveau_channel *);
1065extern void nv50_graph_destroy_context(struct nouveau_channel *);
1066extern int nv50_graph_load_context(struct nouveau_channel *);
1067extern int nv50_graph_unload_context(struct drm_device *);
1068extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1069extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1070
4b223eef
BS		 1071/* nvc0_graph.c */
1072extern int nvc0_graph_init(struct drm_device *);
1073extern void nvc0_graph_takedown(struct drm_device *);
1074extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1075extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1076extern int nvc0_graph_create_context(struct nouveau_channel *);
1077extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1078extern int nvc0_graph_load_context(struct nouveau_channel *);
1079extern int nvc0_graph_unload_context(struct drm_device *);
1080
6ee73861
BS		 1081/* nv04_instmem.c */
1082extern int nv04_instmem_init(struct drm_device *);
1083extern void nv04_instmem_takedown(struct drm_device *);
1084extern int nv04_instmem_suspend(struct drm_device *);
1085extern void nv04_instmem_resume(struct drm_device *);
1086extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1087 uint32_t *size);
1088extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1089extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1090extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1091extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1092
1093/* nv50_instmem.c */
1094extern int nv50_instmem_init(struct drm_device *);
1095extern void nv50_instmem_takedown(struct drm_device *);
1096extern int nv50_instmem_suspend(struct drm_device *);
1097extern void nv50_instmem_resume(struct drm_device *);
1098extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1099 uint32_t *size);
1100extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1101extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1102extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1103extern void nv50_instmem_flush(struct drm_device *);
734ee835 1104extern void nv84_instmem_flush(struct drm_device *);
63187215 1105extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1106
4b223eef
BS		 1107/* nvc0_instmem.c */
1108extern int nvc0_instmem_init(struct drm_device *);
1109extern void nvc0_instmem_takedown(struct drm_device *);
1110extern int nvc0_instmem_suspend(struct drm_device *);
1111extern void nvc0_instmem_resume(struct drm_device *);
1112extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1113 uint32_t *size);
1114extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1115extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1116extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1117extern void nvc0_instmem_flush(struct drm_device *);
1118
6ee73861
BS		 1119/* nv04_mc.c */
1120extern int nv04_mc_init(struct drm_device *);
1121extern void nv04_mc_takedown(struct drm_device *);
1122
1123/* nv40_mc.c */
1124extern int nv40_mc_init(struct drm_device *);
1125extern void nv40_mc_takedown(struct drm_device *);
1126
1127/* nv50_mc.c */
1128extern int nv50_mc_init(struct drm_device *);
1129extern void nv50_mc_takedown(struct drm_device *);
1130
1131/* nv04_timer.c */
1132extern int nv04_timer_init(struct drm_device *);
1133extern uint64_t nv04_timer_read(struct drm_device *);
1134extern void nv04_timer_takedown(struct drm_device *);
1135
1136extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1137 unsigned long arg);
1138
1139/* nv04_dac.c */
8f1a6086 1140extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1141extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1142extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1143extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1144extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1145
1146/* nv04_dfp.c */
8f1a6086 1147extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1148extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1149extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1150 int head, bool dl);
1151extern void nv04_dfp_disable(struct drm_device *dev, int head);
1152extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1153
1154/* nv04_tv.c */
1155extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1156extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1157
1158/* nv17_tv.c */
8f1a6086 1159extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1160
1161/* nv04_display.c */
c88c2e06
FJ		 1162extern int nv04_display_early_init(struct drm_device *);
1163extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1164extern int nv04_display_create(struct drm_device *);
c88c2e06 1165extern int nv04_display_init(struct drm_device *);
6ee73861 1166extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1167
1168/* nv04_crtc.c */
1169extern int nv04_crtc_create(struct drm_device *, int index);
1170
1171/* nouveau_bo.c */
1172extern struct ttm_bo_driver nouveau_bo_driver;
1173extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1174 int size, int align, uint32_t flags,
1175 uint32_t tile_mode, uint32_t tile_flags,
1176 bool no_vm, bool mappable, struct nouveau_bo **);
1177extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1178extern int nouveau_bo_unpin(struct nouveau_bo *);
1179extern int nouveau_bo_map(struct nouveau_bo *);
1180extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1181extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1182 uint32_t busy);
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BS		 1183extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1184extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1185extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1186extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
415e6186 1187extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
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BS		 1188
1189/* nouveau_fence.c */
1190struct nouveau_fence;
1191extern int nouveau_fence_init(struct nouveau_channel *);
1192extern void nouveau_fence_fini(struct nouveau_channel *);
1193extern void nouveau_fence_update(struct nouveau_channel *);
1194extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1195 bool emit);
1196extern int nouveau_fence_emit(struct nouveau_fence *);
1197struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1198extern bool nouveau_fence_signalled(void *obj, void *arg);
1199extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1200extern int nouveau_fence_flush(void *obj, void *arg);
1201extern void nouveau_fence_unref(void **obj);
1202extern void *nouveau_fence_ref(void *obj);
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BS		 1203
1204/* nouveau_gem.c */
1205extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1206 int size, int align, uint32_t flags,
1207 uint32_t tile_mode, uint32_t tile_flags,
1208 bool no_vm, bool mappable, struct nouveau_bo **);
1209extern int nouveau_gem_object_new(struct drm_gem_object *);
1210extern void nouveau_gem_object_del(struct drm_gem_object *);
1211extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1212 struct drm_file *);
1213extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1214 struct drm_file *);
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BS		 1215extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1216 struct drm_file *);
1217extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1218 struct drm_file *);
1219extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1220 struct drm_file *);
1221
ee2e0131
BS		 1222/* nv10_gpio.c */
1223int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1224int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1225
45284162 1226/* nv50_gpio.c */
ee2e0131 1227int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1228int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1229int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1230void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1231
e9ebb68b
BS		 1232/* nv50_calc. */
1233int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1234 int *N1, int *M1, int *N2, int *M2, int *P);
1235int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1236 int clk, int *N, int *fN, int *M, int *P);
1237
6ee73861
BS		 1238#ifndef ioread32_native
1239#ifdef __BIG_ENDIAN
1240#define ioread16_native ioread16be
1241#define iowrite16_native iowrite16be
1242#define ioread32_native ioread32be
1243#define iowrite32_native iowrite32be
1244#else /* def __BIG_ENDIAN */
1245#define ioread16_native ioread16
1246#define iowrite16_native iowrite16
1247#define ioread32_native ioread32
1248#define iowrite32_native iowrite32
1249#endif /* def __BIG_ENDIAN else */
1250#endif /* !ioread32_native */
1251
1252/* channel control reg access */
1253static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1254{
1255 return ioread32_native(chan->user + reg);
1256}
1257
1258static inline void nvchan_wr32(struct nouveau_channel *chan,
1259 unsigned reg, u32 val)
1260{
1261 iowrite32_native(val, chan->user + reg);
1262}
1263
1264/* register access */
1265static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1266{
1267 struct drm_nouveau_private *dev_priv = dev->dev_private;
1268 return ioread32_native(dev_priv->mmio + reg);
1269}
1270
1271static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1272{
1273 struct drm_nouveau_private *dev_priv = dev->dev_private;
1274 iowrite32_native(val, dev_priv->mmio + reg);
1275}
1276
2a7fdb2b 1277static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1278{
1279 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1280 nv_wr32(dev, reg, (tmp & ~mask) | val);
1281 return tmp;
49eed80a
BS		 1282}
1283
6ee73861
BS		 1284static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1285{
1286 struct drm_nouveau_private *dev_priv = dev->dev_private;
1287 return ioread8(dev_priv->mmio + reg);
1288}
1289
1290static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1291{
1292 struct drm_nouveau_private *dev_priv = dev->dev_private;
1293 iowrite8(val, dev_priv->mmio + reg);
1294}
1295
4b5c152a 1296#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1297 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1298
1299/* PRAMIN access */
1300static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1301{
1302 struct drm_nouveau_private *dev_priv = dev->dev_private;
1303 return ioread32_native(dev_priv->ramin + offset);
1304}
1305
1306static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1307{
1308 struct drm_nouveau_private *dev_priv = dev->dev_private;
1309 iowrite32_native(val, dev_priv->ramin + offset);
1310}
1311
1312/* object access */
b3beb167
BS		 1313extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1314extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1315
1316/*
1317 * Logging
1318 * Argument d is (struct drm_device *).
1319 */
1320#define NV_PRINTK(level, d, fmt, arg...) \
1321 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1322 pci_name(d->pdev), ##arg)
1323#ifndef NV_DEBUG_NOTRACE
1324#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1325 if (drm_debug & DRM_UT_DRIVER) { \
1326 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1327 __LINE__, ##arg); \
1328 } \
1329} while (0)
1330#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1331 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1332 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1333 __LINE__, ##arg); \
1334 } \
1335} while (0)
1336#else
1337#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1338 if (drm_debug & DRM_UT_DRIVER) \
1339 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1340} while (0)
1341#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1342 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1343 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1344} while (0)
1345#endif
1346#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1347#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1348#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1349#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1350#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1351
1352/* nouveau_reg_debug bitmask */
1353enum {
1354 NOUVEAU_REG_DEBUG_MC = 0x1,
1355 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1356 NOUVEAU_REG_DEBUG_FB = 0x4,
1357 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1358 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1359 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1360 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1361 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1362 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1363 NOUVEAU_REG_DEBUG_EVO = 0x200,
1364};
1365
1366#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1367 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1368 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1369} while (0)
1370
1371static inline bool
1372nv_two_heads(struct drm_device *dev)
1373{
1374 struct drm_nouveau_private *dev_priv = dev->dev_private;
1375 const int impl = dev->pci_device & 0x0ff0;
1376
1377 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1378 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1379 return true;
1380
1381 return false;
1382}
1383
1384static inline bool
1385nv_gf4_disp_arch(struct drm_device *dev)
1386{
1387 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1388}
1389
1390static inline bool
1391nv_two_reg_pll(struct drm_device *dev)
1392{
1393 struct drm_nouveau_private *dev_priv = dev->dev_private;
1394 const int impl = dev->pci_device & 0x0ff0;
1395
1396 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1397 return true;
1398 return false;
1399}
1400
acae116c
FJ		 1401static inline bool
1402nv_match_device(struct drm_device *dev, unsigned device,
1403 unsigned sub_vendor, unsigned sub_device)
1404{
1405 return dev->pdev->device == device &&
1406 dev->pdev->subsystem_vendor == sub_vendor &&
1407 dev->pdev->subsystem_device == sub_device;
1408}
1409
f03a314b
FJ		 1410#define NV_SW 0x0000506e
1411#define NV_SW_DMA_SEMAPHORE 0x00000060
1412#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1413#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1414#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1415#define NV_SW_DMA_VBLSEM 0x0000018c
1416#define NV_SW_VBLSEM_OFFSET 0x00000400
1417#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1418#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1419
1420#endif /* __NOUVEAU_DRV_H__ */
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