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drm/nouveau: remove some useless GETPARAMs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
274fec93 57#include "nouveau_util.h"
054b93e4 58struct nouveau_grctx;
6ee73861
BS		 59
60#define MAX_NUM_DCB_ENTRIES 16
61
62#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 63#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 64
65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
66#define NV50_VM_BLOCK (512*1024*1024ULL)
67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68
a0af9add 69struct nouveau_tile_reg {
a0af9add 70 bool used;
a5cf68b0
FJ		 71 uint32_t addr;
72 uint32_t limit;
73 uint32_t pitch;
87a326a3
FJ		 74 uint32_t zcomp;
75 struct drm_mm_node *tag_mem;
a5cf68b0 76 struct nouveau_fence *fence;
a0af9add
FJ		 77};
78
6ee73861
BS		 79struct nouveau_bo {
80 struct ttm_buffer_object bo;
81 struct ttm_placement placement;
82 u32 placements[3];
78ad0f7b 83 u32 busy_placements[3];
6ee73861
BS		 84 struct ttm_bo_kmap_obj kmap;
85 struct list_head head;
86
87 /* protected by ttm_bo_reserve() */
88 struct drm_file *reserved_by;
89 struct list_head entry;
90 int pbbo_index;
a1606a95 91 bool validate_mapped;
6ee73861
BS		 92
93 struct nouveau_channel *channel;
94
95 bool mappable;
96 bool no_vm;
97
98 uint32_t tile_mode;
99 uint32_t tile_flags;
a0af9add 100 struct nouveau_tile_reg *tile;
6ee73861
BS		 101
102 struct drm_gem_object *gem;
6ee73861
BS		 103 int pin_refcnt;
104};
105
f13b3263
FJ		 106#define nouveau_bo_tile_layout(nvbo) \
107 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
108
6ee73861
BS		 109static inline struct nouveau_bo *
110nouveau_bo(struct ttm_buffer_object *bo)
111{
112 return container_of(bo, struct nouveau_bo, bo);
113}
114
115static inline struct nouveau_bo *
116nouveau_gem_object(struct drm_gem_object *gem)
117{
118 return gem ? gem->driver_private : NULL;
119}
120
121/* TODO: submit equivalent to TTM generic API upstream? */
122static inline void __iomem *
123nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
124{
125 bool is_iomem;
126 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
127 &nvbo->kmap, &is_iomem);
128 WARN_ON_ONCE(ioptr && !is_iomem);
129 return ioptr;
130}
131
6ee73861
BS		 132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 139#define NVOBJ_ENGINE_PPP 2
140#define NVOBJ_ENGINE_COPY 3
141#define NVOBJ_ENGINE_VP 4
142#define NVOBJ_ENGINE_CRYPT 5
143#define NVOBJ_ENGINE_BSP 6
50536946 144#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 145#define NVOBJ_ENGINE_INT 0xdeadbeef
146
6ee73861
BS		 147#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
148#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
e41115d0
BS		 149
150#define NVOBJ_CINST_GLOBAL 0xdeadbeef
151
6ee73861 152struct nouveau_gpuobj {
b3beb167 153 struct drm_device *dev;
eb9bcbdc 154 struct kref refcount;
6ee73861
BS		 155 struct list_head list;
156
e41115d0 157 void *node;
dc1e5c0d 158 u32 *suspend;
6ee73861
BS		 159
160 uint32_t flags;
6ee73861 161
43efc9ce 162 u32 size;
de3a6c0a
BS		 163 u32 pinst;
164 u32 cinst;
165 u64 vinst;
166
6ee73861
BS		 167 uint32_t engine;
168 uint32_t class;
169
170 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
171 void *priv;
172};
173
332b242f
FJ		 174struct nouveau_page_flip_state {
175 struct list_head head;
176 struct drm_pending_vblank_event *event;
177 int crtc, bpp, pitch, x, y;
178 uint64_t offset;
179};
180
e419cf09
FJ		 181enum nouveau_channel_mutex_class {
182 NOUVEAU_UCHANNEL_MUTEX,
183 NOUVEAU_KCHANNEL_MUTEX
184};
185
6ee73861
BS		 186struct nouveau_channel {
187 struct drm_device *dev;
188 int id;
189
f091a3d4
FJ		 190 /* references to the channel data structure */
191 struct kref ref;
192 /* users of the hardware channel resources, the hardware
193 * context will be kicked off when it reaches zero. */
194 atomic_t users;
6a6b73f2
BS		 195 struct mutex mutex;
196
6ee73861
BS		 197 /* owner of this fifo */
198 struct drm_file *file_priv;
199 /* mapping of the fifo itself */
200 struct drm_local_map *map;
201
202 /* mapping of the regs controling the fifo */
203 void __iomem *user;
204 uint32_t user_get;
205 uint32_t user_put;
206
207 /* Fencing */
208 struct {
209 /* lock protects the pending list only */
210 spinlock_t lock;
211 struct list_head pending;
212 uint32_t sequence;
213 uint32_t sequence_ack;
047d1d3c 214 atomic_t last_sequence_irq;
6ee73861
BS		 215 } fence;
216
217 /* DMA push buffer */
a8eaebc6
BS		 218 struct nouveau_gpuobj *pushbuf;
219 struct nouveau_bo *pushbuf_bo;
220 uint32_t pushbuf_base;
6ee73861
BS		 221
222 /* Notifier memory */
223 struct nouveau_bo *notifier_bo;
b833ac26 224 struct drm_mm notifier_heap;
6ee73861
BS		 225
226 /* PFIFO context */
a8eaebc6
BS		 227 struct nouveau_gpuobj *ramfc;
228 struct nouveau_gpuobj *cache;
6ee73861
BS		 229
230 /* PGRAPH context */
231 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 232 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 233 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 234 void *pgraph_ctx;
235
236 /* NV50 VM */
a8eaebc6
BS		 237 struct nouveau_gpuobj *vm_pd;
238 struct nouveau_gpuobj *vm_gart_pt;
239 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 240
241 /* Objects */
a8eaebc6
BS		 242 struct nouveau_gpuobj *ramin; /* Private instmem */
243 struct drm_mm ramin_heap; /* Private PRAMIN heap */
244 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 245
246 /* GPU object info for stuff used in-kernel (mm_enabled) */
247 uint32_t m2mf_ntfy;
248 uint32_t vram_handle;
249 uint32_t gart_handle;
250 bool accel_done;
251
252 /* Push buffer state (only for drm's channel on !mm_enabled) */
253 struct {
254 int max;
255 int free;
256 int cur;
257 int put;
258 /* access via pushbuf_bo */
9a391ad8
BS		 259
260 int ib_base;
261 int ib_max;
262 int ib_free;
263 int ib_put;
6ee73861
BS		 264 } dma;
265
266 uint32_t sw_subchannel[8];
267
268 struct {
269 struct nouveau_gpuobj *vblsem;
1f6d2de2 270 uint32_t vblsem_head;
6ee73861
BS		 271 uint32_t vblsem_offset;
272 uint32_t vblsem_rval;
273 struct list_head vbl_wait;
332b242f 274 struct list_head flip;
6ee73861
BS		 275 } nvsw;
276
277 struct {
278 bool active;
279 char name[32];
280 struct drm_info_list info;
281 } debugfs;
282};
283
284struct nouveau_instmem_engine {
285 void *priv;
286
287 int (*init)(struct drm_device *dev);
288 void (*takedown)(struct drm_device *dev);
289 int (*suspend)(struct drm_device *dev);
290 void (*resume)(struct drm_device *dev);
291
e41115d0
BS		 292 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
293 void (*put)(struct nouveau_gpuobj *);
294 int (*map)(struct nouveau_gpuobj *);
295 void (*unmap)(struct nouveau_gpuobj *);
296
f56cb86f 297 void (*flush)(struct drm_device *);
6ee73861
BS		 298};
299
300struct nouveau_mc_engine {
301 int (*init)(struct drm_device *dev);
302 void (*takedown)(struct drm_device *dev);
303};
304
305struct nouveau_timer_engine {
306 int (*init)(struct drm_device *dev);
307 void (*takedown)(struct drm_device *dev);
308 uint64_t (*read)(struct drm_device *dev);
309};
310
311struct nouveau_fb_engine {
cb00f7c1 312 int num_tiles;
87a326a3 313 struct drm_mm tag_heap;
20f63afe 314 void *priv;
cb00f7c1 315
6ee73861
BS		 316 int (*init)(struct drm_device *dev);
317 void (*takedown)(struct drm_device *dev);
cb00f7c1 318
a5cf68b0
FJ		 319 void (*init_tile_region)(struct drm_device *dev, int i,
320 uint32_t addr, uint32_t size,
321 uint32_t pitch, uint32_t flags);
322 void (*set_tile_region)(struct drm_device *dev, int i);
323 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 324};
325
326struct nouveau_fifo_engine {
6ee73861
BS		 327 int channels;
328
a8eaebc6 329 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 330 int cur_playlist;
331
6ee73861
BS		 332 int (*init)(struct drm_device *);
333 void (*takedown)(struct drm_device *);
334
335 void (*disable)(struct drm_device *);
336 void (*enable)(struct drm_device *);
337 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 338 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 339
340 int (*channel_id)(struct drm_device *);
341
342 int (*create_context)(struct nouveau_channel *);
343 void (*destroy_context)(struct nouveau_channel *);
344 int (*load_context)(struct nouveau_channel *);
345 int (*unload_context)(struct drm_device *);
56ac7475 346 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 347};
348
6ee73861 349struct nouveau_pgraph_engine {
6ee73861 350 bool accel_blocked;
b8c157d3 351 bool registered;
054b93e4 352 int grctx_size;
6ee73861 353
c50a5681 354 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 355 struct nouveau_gpuobj *ctx_table;
c50a5681 356
6ee73861
BS		 357 int (*init)(struct drm_device *);
358 void (*takedown)(struct drm_device *);
359
360 void (*fifo_access)(struct drm_device *, bool);
361
362 struct nouveau_channel *(*channel)(struct drm_device *);
363 int (*create_context)(struct nouveau_channel *);
364 void (*destroy_context)(struct nouveau_channel *);
365 int (*load_context)(struct nouveau_channel *);
366 int (*unload_context)(struct drm_device *);
56ac7475 367 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1 368
a5cf68b0 369 void (*set_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 370};
371
c88c2e06
FJ		 372struct nouveau_display_engine {
373 int (*early_init)(struct drm_device *);
374 void (*late_takedown)(struct drm_device *);
375 int (*create)(struct drm_device *);
376 int (*init)(struct drm_device *);
377 void (*destroy)(struct drm_device *);
378};
379
ee2e0131 380struct nouveau_gpio_engine {
fce2bad0
BS		 381 void *priv;
382
ee2e0131
BS		 383 int (*init)(struct drm_device *);
384 void (*takedown)(struct drm_device *);
385
386 int (*get)(struct drm_device *, enum dcb_gpio_tag);
387 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
388
fce2bad0
BS		 389 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
390 void (*)(void *, int), void *);
391 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
392 void (*)(void *, int), void *);
393 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
ee2e0131
BS		 394};
395
330c5988
BS		 396struct nouveau_pm_voltage_level {
397 u8 voltage;
398 u8 vid;
399};
400
401struct nouveau_pm_voltage {
402 bool supported;
403 u8 vid_mask;
404
405 struct nouveau_pm_voltage_level *level;
406 int nr_level;
407};
408
409#define NOUVEAU_PM_MAX_LEVEL 8
410struct nouveau_pm_level {
411 struct device_attribute dev_attr;
412 char name[32];
413 int id;
414
415 u32 core;
416 u32 memory;
417 u32 shader;
418 u32 unk05;
419
420 u8 voltage;
421 u8 fanspeed;
aee582de
BS		 422
423 u16 memscript;
330c5988
BS		 424};
425
34e9d85a
MP		 426struct nouveau_pm_temp_sensor_constants {
427 u16 offset_constant;
428 s16 offset_mult;
429 u16 offset_div;
430 u16 slope_mult;
431 u16 slope_div;
432};
433
434struct nouveau_pm_threshold_temp {
435 s16 critical;
436 s16 down_clock;
437 s16 fan_boost;
438};
439
7760fcb0
RS		 440struct nouveau_pm_memtiming {
441 u32 reg_100220;
442 u32 reg_100224;
443 u32 reg_100228;
444 u32 reg_10022c;
445 u32 reg_100230;
446 u32 reg_100234;
447 u32 reg_100238;
448 u32 reg_10023c;
449};
450
451struct nouveau_pm_memtimings {
452 bool supported;
453 struct nouveau_pm_memtiming *timing;
454 int nr_timing;
455};
456
330c5988
BS		 457struct nouveau_pm_engine {
458 struct nouveau_pm_voltage voltage;
459 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
460 int nr_perflvl;
7760fcb0 461 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 462 struct nouveau_pm_temp_sensor_constants sensor_constants;
463 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 464
465 struct nouveau_pm_level boot;
466 struct nouveau_pm_level *cur;
467
8155cac4 468 struct device *hwmon;
6032649d 469 struct notifier_block acpi_nb;
8155cac4 470
330c5988 471 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 472 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
473 u32 id, int khz);
330c5988
BS		 474 void (*clock_set)(struct drm_device *, void *);
475 int (*voltage_get)(struct drm_device *);
476 int (*voltage_set)(struct drm_device *, int voltage);
477 int (*fanspeed_get)(struct drm_device *);
478 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 479 int (*temp_get)(struct drm_device *);
330c5988
BS		 480};
481
bd2e597d
BS		 482struct nouveau_crypt_engine {
483 bool registered;
484
485 int (*init)(struct drm_device *);
486 void (*takedown)(struct drm_device *);
487 int (*create_context)(struct nouveau_channel *);
488 void (*destroy_context)(struct nouveau_channel *);
489 void (*tlb_flush)(struct drm_device *dev);
490};
491
6ee73861
BS		 492struct nouveau_engine {
493 struct nouveau_instmem_engine instmem;
494 struct nouveau_mc_engine mc;
495 struct nouveau_timer_engine timer;
496 struct nouveau_fb_engine fb;
497 struct nouveau_pgraph_engine graph;
498 struct nouveau_fifo_engine fifo;
c88c2e06 499 struct nouveau_display_engine display;
ee2e0131 500 struct nouveau_gpio_engine gpio;
330c5988 501 struct nouveau_pm_engine pm;
bd2e597d 502 struct nouveau_crypt_engine crypt;
6ee73861
BS		 503};
504
505struct nouveau_pll_vals {
506 union {
507 struct {
508#ifdef __BIG_ENDIAN
509 uint8_t N1, M1, N2, M2;
510#else
511 uint8_t M1, N1, M2, N2;
512#endif
513 };
514 struct {
515 uint16_t NM1, NM2;
516 } __attribute__((packed));
517 };
518 int log2P;
519
520 int refclk;
521};
522
523enum nv04_fp_display_regs {
524 FP_DISPLAY_END,
525 FP_TOTAL,
526 FP_CRTC,
527 FP_SYNC_START,
528 FP_SYNC_END,
529 FP_VALID_START,
530 FP_VALID_END
531};
532
533struct nv04_crtc_reg {
cbab95db 534 unsigned char MiscOutReg;
4a9f822f 535 uint8_t CRTC[0xa0];
6ee73861
BS		 536 uint8_t CR58[0x10];
537 uint8_t Sequencer[5];
538 uint8_t Graphics[9];
539 uint8_t Attribute[21];
cbab95db 540 unsigned char DAC[768];
6ee73861
BS		 541
542 /* PCRTC regs */
543 uint32_t fb_start;
544 uint32_t crtc_cfg;
545 uint32_t cursor_cfg;
546 uint32_t gpio_ext;
547 uint32_t crtc_830;
548 uint32_t crtc_834;
549 uint32_t crtc_850;
550 uint32_t crtc_eng_ctrl;
551
552 /* PRAMDAC regs */
553 uint32_t nv10_cursync;
554 struct nouveau_pll_vals pllvals;
555 uint32_t ramdac_gen_ctrl;
556 uint32_t ramdac_630;
557 uint32_t ramdac_634;
558 uint32_t tv_setup;
559 uint32_t tv_vtotal;
560 uint32_t tv_vskew;
561 uint32_t tv_vsync_delay;
562 uint32_t tv_htotal;
563 uint32_t tv_hskew;
564 uint32_t tv_hsync_delay;
565 uint32_t tv_hsync_delay2;
566 uint32_t fp_horiz_regs[7];
567 uint32_t fp_vert_regs[7];
568 uint32_t dither;
569 uint32_t fp_control;
570 uint32_t dither_regs[6];
571 uint32_t fp_debug_0;
572 uint32_t fp_debug_1;
573 uint32_t fp_debug_2;
574 uint32_t fp_margin_color;
575 uint32_t ramdac_8c0;
576 uint32_t ramdac_a20;
577 uint32_t ramdac_a24;
578 uint32_t ramdac_a34;
579 uint32_t ctv_regs[38];
580};
581
582struct nv04_output_reg {
583 uint32_t output;
584 int head;
585};
586
587struct nv04_mode_state {
cbab95db 588 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 589 uint32_t pllsel;
590 uint32_t sel_clk;
6ee73861
BS		 591};
592
593enum nouveau_card_type {
594 NV_04 = 0x00,
595 NV_10 = 0x10,
596 NV_20 = 0x20,
597 NV_30 = 0x30,
598 NV_40 = 0x40,
599 NV_50 = 0x50,
4b223eef 600 NV_C0 = 0xc0,
6ee73861
BS		 601};
602
603struct drm_nouveau_private {
604 struct drm_device *dev;
6ee73861
BS		 605
606 /* the card type, takes NV_* as values */
607 enum nouveau_card_type card_type;
608 /* exact chipset, derived from NV_PMC_BOOT_0 */
609 int chipset;
610 int flags;
611
612 void __iomem *mmio;
5125bfd8 613
e05d7eae 614 spinlock_t ramin_lock;
6ee73861 615 void __iomem *ramin;
5125bfd8
BS		 616 u32 ramin_size;
617 u32 ramin_base;
618 bool ramin_available;
e05d7eae
BS		 619 struct drm_mm ramin_heap;
620 struct list_head gpuobj_list;
b8c157d3 621 struct list_head classes;
6ee73861 622
ac8fb975
BS		 623 struct nouveau_bo *vga_ram;
624
35fa2f2a 625 /* interrupt handling */
8f8a5448 626 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 627 bool msi_enabled;
6ee73861
BS		 628 struct workqueue_struct *wq;
629 struct work_struct irq_work;
ab838338 630
6ee73861
BS		 631 struct list_head vbl_waiting;
632
633 struct {
ba4420c2 634 struct drm_global_reference mem_global_ref;
6ee73861
BS		 635 struct ttm_bo_global_ref bo_global_ref;
636 struct ttm_bo_device bdev;
6ee73861
BS		 637 atomic_t validate_sequence;
638 } ttm;
639
0c6c1c2f
FJ		 640 struct {
641 spinlock_t lock;
642 struct drm_mm heap;
643 struct nouveau_bo *bo;
644 } fence;
645
cff5c133
BS		 646 struct {
647 spinlock_t lock;
648 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
649 } channels;
6ee73861
BS		 650
651 struct nouveau_engine engine;
652 struct nouveau_channel *channel;
653
ff9e5279
MM		 654 /* For PFIFO and PGRAPH. */
655 spinlock_t context_switch_lock;
656
6ee73861 657 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 658 struct nouveau_ramht *ramht;
659 struct nouveau_gpuobj *ramfc;
660 struct nouveau_gpuobj *ramro;
661
6ee73861 662 uint32_t ramin_rsvd_vram;
6ee73861 663
6ee73861
BS		 664 struct {
665 enum {
666 NOUVEAU_GART_NONE = 0,
667 NOUVEAU_GART_AGP,
668 NOUVEAU_GART_SGDMA
669 } type;
670 uint64_t aper_base;
671 uint64_t aper_size;
672 uint64_t aper_free;
673
674 struct nouveau_gpuobj *sg_ctxdma;
6ee73861
BS		 675 } gart_info;
676
a0af9add 677 /* nv10-nv40 tiling regions */
a5cf68b0
FJ		 678 struct {
679 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
680 spinlock_t lock;
681 } tile;
a0af9add 682
a76fb4e8
BS		 683 /* VRAM/fb configuration */
684 uint64_t vram_size;
685 uint64_t vram_sys_base;
6c3d7ef2 686 u32 vram_rblock_size;
a76fb4e8
BS		 687
688 uint64_t fb_phys;
689 uint64_t fb_available_size;
690 uint64_t fb_mappable_pages;
691 uint64_t fb_aper_free;
692 int fb_mtrr;
693
6ee73861
BS		 694 /* G8x/G9x virtual address space */
695 uint64_t vm_gart_base;
696 uint64_t vm_gart_size;
697 uint64_t vm_vram_base;
698 uint64_t vm_vram_size;
699 uint64_t vm_end;
700 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
701 int vm_vram_pt_nr;
6ee73861 702
04a39c57 703 struct nvbios vbios;
6ee73861
BS		 704
705 struct nv04_mode_state mode_reg;
706 struct nv04_mode_state saved_reg;
707 uint32_t saved_vga_font[4][16384];
708 uint32_t crtc_owner;
709 uint32_t dac_users[4];
710
711 struct nouveau_suspend_resume {
6ee73861 712 uint32_t *ramin_copy;
6ee73861
BS		 713 } susres;
714
715 struct backlight_device *backlight;
6ee73861
BS		 716
717 struct nouveau_channel *evo;
1e96268a 718 u32 evo_alloc;
87c0e0e5
BS		 719 struct {
720 struct dcb_entry *dcb;
721 u16 script;
722 u32 pclk;
723 } evo_irq;
6ee73861
BS		 724
725 struct {
726 struct dentry *channel_root;
727 } debugfs;
38651674 728
8be48d92 729 struct nouveau_fbdev *nfbdev;
06415c56 730 struct apertures_struct *apertures;
6ee73861
BS		 731};
732
2730723b
FJ		 733static inline struct drm_nouveau_private *
734nouveau_private(struct drm_device *dev)
735{
736 return dev->dev_private;
737}
738
6ee73861
BS		 739static inline struct drm_nouveau_private *
740nouveau_bdev(struct ttm_bo_device *bd)
741{
742 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
743}
744
745static inline int
746nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
747{
748 struct nouveau_bo *prev;
749
750 if (!pnvbo)
751 return -EINVAL;
752 prev = *pnvbo;
753
754 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
755 if (prev) {
756 struct ttm_buffer_object *bo = &prev->bo;
757
758 ttm_bo_unref(&bo);
759 }
760
761 return 0;
762}
763
6ee73861 764/* nouveau_drv.c */
de5899bd 765extern int nouveau_agpmode;
6ee73861
BS		 766extern int nouveau_duallink;
767extern int nouveau_uscript_lvds;
768extern int nouveau_uscript_tmds;
769extern int nouveau_vram_pushbuf;
770extern int nouveau_vram_notify;
771extern int nouveau_fbpercrtc;
f4053509 772extern int nouveau_tv_disable;
6ee73861
BS		 773extern char *nouveau_tv_norm;
774extern int nouveau_reg_debug;
775extern char *nouveau_vbios;
a1470890 776extern int nouveau_ignorelid;
a32ed69d
MK		 777extern int nouveau_nofbaccel;
778extern int nouveau_noaccel;
0cba1b76 779extern int nouveau_force_post;
da647d5b 780extern int nouveau_override_conntype;
6f876986
BS		 781extern char *nouveau_perflvl;
782extern int nouveau_perflvl_wr;
35fa2f2a 783extern int nouveau_msi;
6ee73861 784
6a9ee8af
DA		 785extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
786extern int nouveau_pci_resume(struct pci_dev *pdev);
787
6ee73861
BS		 788/* nouveau_state.c */
789extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
790extern int nouveau_load(struct drm_device *, unsigned long flags);
791extern int nouveau_firstopen(struct drm_device *);
792extern void nouveau_lastclose(struct drm_device *);
793extern int nouveau_unload(struct drm_device *);
794extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
795 struct drm_file *);
796extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
797 struct drm_file *);
798extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
799 uint32_t reg, uint32_t mask, uint32_t val);
800extern bool nouveau_wait_for_idle(struct drm_device *);
801extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 802
803/* nouveau_mem.c */
fbd2895e
BS		 804extern int nouveau_mem_vram_init(struct drm_device *);
805extern void nouveau_mem_vram_fini(struct drm_device *);
806extern int nouveau_mem_gart_init(struct drm_device *);
807extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 808extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 809extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 810extern void nouveau_mem_close(struct drm_device *);
a5cf68b0
FJ		 811extern struct nouveau_tile_reg *nv10_mem_set_tiling(
812 struct drm_device *dev, uint32_t addr, uint32_t size,
813 uint32_t pitch, uint32_t flags);
814extern void nv10_mem_put_tile_region(struct drm_device *dev,
815 struct nouveau_tile_reg *tile,
816 struct nouveau_fence *fence);
6ee73861
BS		 817extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
818 uint32_t size, uint32_t flags,
819 uint64_t phys);
820extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
821 uint32_t size);
822
823/* nouveau_notifier.c */
824extern int nouveau_notifier_init_channel(struct nouveau_channel *);
825extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
826extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
827 int cout, uint32_t *offset);
828extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
829extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
830 struct drm_file *);
831extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
832 struct drm_file *);
833
834/* nouveau_channel.c */
835extern struct drm_ioctl_desc nouveau_ioctls[];
836extern int nouveau_max_ioctl;
837extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 838extern int nouveau_channel_alloc(struct drm_device *dev,
839 struct nouveau_channel **chan,
840 struct drm_file *file_priv,
841 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 842extern struct nouveau_channel *
feeb0aec
FJ		 843nouveau_channel_get_unlocked(struct nouveau_channel *);
844extern struct nouveau_channel *
cff5c133 845nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 846extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 847extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 848extern void nouveau_channel_ref(struct nouveau_channel *chan,
849 struct nouveau_channel **pchan);
6ee73861
BS		 850
851/* nouveau_object.c */
b8c157d3
BS		 852#define NVOBJ_CLASS(d,c,e) do { \
853 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
854 if (ret) \
855 return ret; \
856} while(0)
857
858#define NVOBJ_MTHD(d,c,m,e) do { \
859 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
860 if (ret) \
861 return ret; \
862} while(0)
863
6ee73861
BS		 864extern int nouveau_gpuobj_early_init(struct drm_device *);
865extern int nouveau_gpuobj_init(struct drm_device *);
866extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861 867extern int nouveau_gpuobj_suspend(struct drm_device *dev);
6ee73861 868extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 869extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
870extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
871 int (*exec)(struct nouveau_channel *,
872 u32 class, u32 mthd, u32 data));
873extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
274fec93 874extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
6ee73861
BS		 875extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
876 uint32_t vram_h, uint32_t tt_h);
877extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
878extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
879 uint32_t size, int align, uint32_t flags,
880 struct nouveau_gpuobj **);
a8eaebc6
BS		 881extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
882 struct nouveau_gpuobj **);
43efc9ce
BS		 883extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
884 u32 size, u32 flags,
a8eaebc6 885 struct nouveau_gpuobj **);
6ee73861
BS		 886extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
887 uint64_t offset, uint64_t size, int access,
888 int target, struct nouveau_gpuobj **);
889extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
890 uint64_t offset, uint64_t size,
891 int access, struct nouveau_gpuobj **,
892 uint32_t *o_ret);
893extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
894 struct nouveau_gpuobj **);
895extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
896 struct drm_file *);
897extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
898 struct drm_file *);
899
900/* nouveau_irq.c */
35fa2f2a
BS		 901extern int nouveau_irq_init(struct drm_device *);
902extern void nouveau_irq_fini(struct drm_device *);
6ee73861 903extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS		 904extern void nouveau_irq_register(struct drm_device *, int status_bit,
905 void (*)(struct drm_device *));
906extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS		 907extern void nouveau_irq_preinstall(struct drm_device *);
908extern int nouveau_irq_postinstall(struct drm_device *);
909extern void nouveau_irq_uninstall(struct drm_device *);
910
911/* nouveau_sgdma.c */
912extern int nouveau_sgdma_init(struct drm_device *);
913extern void nouveau_sgdma_takedown(struct drm_device *);
914extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
915 uint32_t *page);
916extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
917
918/* nouveau_debugfs.c */
919#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
920extern int nouveau_debugfs_init(struct drm_minor *);
921extern void nouveau_debugfs_takedown(struct drm_minor *);
922extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
923extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
924#else
925static inline int
926nouveau_debugfs_init(struct drm_minor *minor)
927{
928 return 0;
929}
930
931static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
932{
933}
934
935static inline int
936nouveau_debugfs_channel_init(struct nouveau_channel *chan)
937{
938 return 0;
939}
940
941static inline void
942nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
943{
944}
945#endif
946
947/* nouveau_dma.c */
75c99da6 948extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 949extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 950extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 951
952/* nouveau_acpi.c */
afeb3e11 953#define ROM_BIOS_PAGE 4096
2f41a7f1 954#if defined(CONFIG_ACPI)
6a9ee8af
DA		 955void nouveau_register_dsm_handler(void);
956void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 957int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
958bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 959int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 960#else
961static inline void nouveau_register_dsm_handler(void) {}
962static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 963static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
964static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 965static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 966#endif
6ee73861
BS		 967
968/* nouveau_backlight.c */
969#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
970extern int nouveau_backlight_init(struct drm_device *);
971extern void nouveau_backlight_exit(struct drm_device *);
972#else
973static inline int nouveau_backlight_init(struct drm_device *dev)
974{
975 return 0;
976}
977
978static inline void nouveau_backlight_exit(struct drm_device *dev) { }
979#endif
980
981/* nouveau_bios.c */
982extern int nouveau_bios_init(struct drm_device *);
983extern void nouveau_bios_takedown(struct drm_device *dev);
984extern int nouveau_run_vbios_init(struct drm_device *);
985extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
986 struct dcb_entry *);
987extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
988 enum dcb_gpio_tag);
989extern struct dcb_connector_table_entry *
990nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 991extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 992extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
993 struct pll_lims *);
994extern int nouveau_bios_run_display_table(struct drm_device *,
995 struct dcb_entry *,
996 uint32_t script, int pxclk);
997extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
998 int *length);
999extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1000extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1001extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1002 bool *dl, bool *if_is_24bit);
1003extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1004 int head, int pxclk);
1005extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1006 enum LVDS_script, int pxclk);
1007
1008/* nouveau_ttm.c */
1009int nouveau_ttm_global_init(struct drm_nouveau_private *);
1010void nouveau_ttm_global_release(struct drm_nouveau_private *);
1011int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1012
1013/* nouveau_dp.c */
1014int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1015 uint8_t *data, int data_nr);
1016bool nouveau_dp_detect(struct drm_encoder *);
1017bool nouveau_dp_link_train(struct drm_encoder *);
1018
1019/* nv04_fb.c */
1020extern int nv04_fb_init(struct drm_device *);
1021extern void nv04_fb_takedown(struct drm_device *);
1022
1023/* nv10_fb.c */
1024extern int nv10_fb_init(struct drm_device *);
1025extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1026extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1027 uint32_t addr, uint32_t size,
1028 uint32_t pitch, uint32_t flags);
1029extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1030extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1031
8bded189
FJ		 1032/* nv30_fb.c */
1033extern int nv30_fb_init(struct drm_device *);
1034extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1035extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1036 uint32_t addr, uint32_t size,
1037 uint32_t pitch, uint32_t flags);
1038extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1039
6ee73861
BS		 1040/* nv40_fb.c */
1041extern int nv40_fb_init(struct drm_device *);
1042extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1043extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1044
304424e1
MK		 1045/* nv50_fb.c */
1046extern int nv50_fb_init(struct drm_device *);
1047extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1048extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1049
4b223eef
BS		 1050/* nvc0_fb.c */
1051extern int nvc0_fb_init(struct drm_device *);
1052extern void nvc0_fb_takedown(struct drm_device *);
1053
6ee73861
BS		 1054/* nv04_fifo.c */
1055extern int nv04_fifo_init(struct drm_device *);
5178d40d 1056extern void nv04_fifo_fini(struct drm_device *);
6ee73861
BS		 1057extern void nv04_fifo_disable(struct drm_device *);
1058extern void nv04_fifo_enable(struct drm_device *);
1059extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1060extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1061extern int nv04_fifo_channel_id(struct drm_device *);
1062extern int nv04_fifo_create_context(struct nouveau_channel *);
1063extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1064extern int nv04_fifo_load_context(struct nouveau_channel *);
1065extern int nv04_fifo_unload_context(struct drm_device *);
5178d40d 1066extern void nv04_fifo_isr(struct drm_device *);
6ee73861
BS		 1067
1068/* nv10_fifo.c */
1069extern int nv10_fifo_init(struct drm_device *);
1070extern int nv10_fifo_channel_id(struct drm_device *);
1071extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1072extern int nv10_fifo_load_context(struct nouveau_channel *);
1073extern int nv10_fifo_unload_context(struct drm_device *);
1074
1075/* nv40_fifo.c */
1076extern int nv40_fifo_init(struct drm_device *);
1077extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1078extern int nv40_fifo_load_context(struct nouveau_channel *);
1079extern int nv40_fifo_unload_context(struct drm_device *);
1080
1081/* nv50_fifo.c */
1082extern int nv50_fifo_init(struct drm_device *);
1083extern void nv50_fifo_takedown(struct drm_device *);
1084extern int nv50_fifo_channel_id(struct drm_device *);
1085extern int nv50_fifo_create_context(struct nouveau_channel *);
1086extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1087extern int nv50_fifo_load_context(struct nouveau_channel *);
1088extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1089extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1090
4b223eef
BS		 1091/* nvc0_fifo.c */
1092extern int nvc0_fifo_init(struct drm_device *);
1093extern void nvc0_fifo_takedown(struct drm_device *);
1094extern void nvc0_fifo_disable(struct drm_device *);
1095extern void nvc0_fifo_enable(struct drm_device *);
1096extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1097extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1098extern int nvc0_fifo_channel_id(struct drm_device *);
1099extern int nvc0_fifo_create_context(struct nouveau_channel *);
1100extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1101extern int nvc0_fifo_load_context(struct nouveau_channel *);
1102extern int nvc0_fifo_unload_context(struct drm_device *);
1103
6ee73861 1104/* nv04_graph.c */
6ee73861
BS		 1105extern int nv04_graph_init(struct drm_device *);
1106extern void nv04_graph_takedown(struct drm_device *);
1107extern void nv04_graph_fifo_access(struct drm_device *, bool);
1108extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1109extern int nv04_graph_create_context(struct nouveau_channel *);
1110extern void nv04_graph_destroy_context(struct nouveau_channel *);
1111extern int nv04_graph_load_context(struct nouveau_channel *);
1112extern int nv04_graph_unload_context(struct drm_device *);
332b242f
FJ		 1113extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1114 u32 class, u32 mthd, u32 data);
274fec93 1115extern struct nouveau_bitfield nv04_graph_nsource[];
6ee73861
BS		 1116
1117/* nv10_graph.c */
6ee73861
BS		 1118extern int nv10_graph_init(struct drm_device *);
1119extern void nv10_graph_takedown(struct drm_device *);
1120extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1121extern int nv10_graph_create_context(struct nouveau_channel *);
1122extern void nv10_graph_destroy_context(struct nouveau_channel *);
1123extern int nv10_graph_load_context(struct nouveau_channel *);
1124extern int nv10_graph_unload_context(struct drm_device *);
a5cf68b0 1125extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
274fec93
BS		 1126extern struct nouveau_bitfield nv10_graph_intr[];
1127extern struct nouveau_bitfield nv10_graph_nstatus[];
6ee73861
BS		 1128
1129/* nv20_graph.c */
6ee73861
BS		 1130extern int nv20_graph_create_context(struct nouveau_channel *);
1131extern void nv20_graph_destroy_context(struct nouveau_channel *);
1132extern int nv20_graph_load_context(struct nouveau_channel *);
1133extern int nv20_graph_unload_context(struct drm_device *);
1134extern int nv20_graph_init(struct drm_device *);
1135extern void nv20_graph_takedown(struct drm_device *);
1136extern int nv30_graph_init(struct drm_device *);
a5cf68b0 1137extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1138
1139/* nv40_graph.c */
6ee73861
BS		 1140extern int nv40_graph_init(struct drm_device *);
1141extern void nv40_graph_takedown(struct drm_device *);
1142extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1143extern int nv40_graph_create_context(struct nouveau_channel *);
1144extern void nv40_graph_destroy_context(struct nouveau_channel *);
1145extern int nv40_graph_load_context(struct nouveau_channel *);
1146extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1147extern void nv40_grctx_init(struct nouveau_grctx *);
a5cf68b0 1148extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1149
1150/* nv50_graph.c */
6ee73861
BS		 1151extern int nv50_graph_init(struct drm_device *);
1152extern void nv50_graph_takedown(struct drm_device *);
1153extern void nv50_graph_fifo_access(struct drm_device *, bool);
1154extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1155extern int nv50_graph_create_context(struct nouveau_channel *);
1156extern void nv50_graph_destroy_context(struct nouveau_channel *);
1157extern int nv50_graph_load_context(struct nouveau_channel *);
1158extern int nv50_graph_unload_context(struct drm_device *);
d5f3c90d 1159extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1160extern void nv50_graph_tlb_flush(struct drm_device *dev);
1161extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1162
4b223eef
BS		 1163/* nvc0_graph.c */
1164extern int nvc0_graph_init(struct drm_device *);
1165extern void nvc0_graph_takedown(struct drm_device *);
1166extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1167extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1168extern int nvc0_graph_create_context(struct nouveau_channel *);
1169extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1170extern int nvc0_graph_load_context(struct nouveau_channel *);
1171extern int nvc0_graph_unload_context(struct drm_device *);
1172
bd2e597d
BS		 1173/* nv84_crypt.c */
1174extern int nv84_crypt_init(struct drm_device *dev);
1175extern void nv84_crypt_fini(struct drm_device *dev);
1176extern int nv84_crypt_create_context(struct nouveau_channel *);
1177extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1178extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1179
6ee73861
BS		 1180/* nv04_instmem.c */
1181extern int nv04_instmem_init(struct drm_device *);
1182extern void nv04_instmem_takedown(struct drm_device *);
1183extern int nv04_instmem_suspend(struct drm_device *);
1184extern void nv04_instmem_resume(struct drm_device *);
e41115d0
BS		 1185extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1186extern void nv04_instmem_put(struct nouveau_gpuobj *);
1187extern int nv04_instmem_map(struct nouveau_gpuobj *);
1188extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1189extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1190
1191/* nv50_instmem.c */
1192extern int nv50_instmem_init(struct drm_device *);
1193extern void nv50_instmem_takedown(struct drm_device *);
1194extern int nv50_instmem_suspend(struct drm_device *);
1195extern void nv50_instmem_resume(struct drm_device *);
e41115d0
BS		 1196extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1197extern void nv50_instmem_put(struct nouveau_gpuobj *);
1198extern int nv50_instmem_map(struct nouveau_gpuobj *);
1199extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1200extern void nv50_instmem_flush(struct drm_device *);
734ee835 1201extern void nv84_instmem_flush(struct drm_device *);
63187215 1202extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1203
4b223eef
BS		 1204/* nvc0_instmem.c */
1205extern int nvc0_instmem_init(struct drm_device *);
1206extern void nvc0_instmem_takedown(struct drm_device *);
1207extern int nvc0_instmem_suspend(struct drm_device *);
1208extern void nvc0_instmem_resume(struct drm_device *);
e41115d0
BS		 1209extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1210extern void nvc0_instmem_put(struct nouveau_gpuobj *);
1211extern int nvc0_instmem_map(struct nouveau_gpuobj *);
1212extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
4b223eef
BS		 1213extern void nvc0_instmem_flush(struct drm_device *);
1214
6ee73861
BS		 1215/* nv04_mc.c */
1216extern int nv04_mc_init(struct drm_device *);
1217extern void nv04_mc_takedown(struct drm_device *);
1218
1219/* nv40_mc.c */
1220extern int nv40_mc_init(struct drm_device *);
1221extern void nv40_mc_takedown(struct drm_device *);
1222
1223/* nv50_mc.c */
1224extern int nv50_mc_init(struct drm_device *);
1225extern void nv50_mc_takedown(struct drm_device *);
1226
1227/* nv04_timer.c */
1228extern int nv04_timer_init(struct drm_device *);
1229extern uint64_t nv04_timer_read(struct drm_device *);
1230extern void nv04_timer_takedown(struct drm_device *);
1231
1232extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1233 unsigned long arg);
1234
1235/* nv04_dac.c */
8f1a6086 1236extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1237extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1238extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1239extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1240extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1241
1242/* nv04_dfp.c */
8f1a6086 1243extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1244extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1245extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1246 int head, bool dl);
1247extern void nv04_dfp_disable(struct drm_device *dev, int head);
1248extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1249
1250/* nv04_tv.c */
1251extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1252extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1253
1254/* nv17_tv.c */
8f1a6086 1255extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1256
1257/* nv04_display.c */
c88c2e06
FJ		 1258extern int nv04_display_early_init(struct drm_device *);
1259extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1260extern int nv04_display_create(struct drm_device *);
c88c2e06 1261extern int nv04_display_init(struct drm_device *);
6ee73861 1262extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1263
1264/* nv04_crtc.c */
1265extern int nv04_crtc_create(struct drm_device *, int index);
1266
1267/* nouveau_bo.c */
1268extern struct ttm_bo_driver nouveau_bo_driver;
1269extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1270 int size, int align, uint32_t flags,
1271 uint32_t tile_mode, uint32_t tile_flags,
1272 bool no_vm, bool mappable, struct nouveau_bo **);
1273extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1274extern int nouveau_bo_unpin(struct nouveau_bo *);
1275extern int nouveau_bo_map(struct nouveau_bo *);
1276extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1277extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1278 uint32_t busy);
6ee73861
BS		 1279extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1280extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1281extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1282extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1283extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
6ee73861
BS		 1284
1285/* nouveau_fence.c */
1286struct nouveau_fence;
0c6c1c2f
FJ		 1287extern int nouveau_fence_init(struct drm_device *);
1288extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1289extern int nouveau_fence_channel_init(struct nouveau_channel *);
1290extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1291extern void nouveau_fence_update(struct nouveau_channel *);
1292extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1293 bool emit);
1294extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1295extern void nouveau_fence_work(struct nouveau_fence *fence,
1296 void (*work)(void *priv, bool signalled),
1297 void *priv);
6ee73861 1298struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1299
1300extern bool __nouveau_fence_signalled(void *obj, void *arg);
1301extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1302extern int __nouveau_fence_flush(void *obj, void *arg);
1303extern void __nouveau_fence_unref(void **obj);
1304extern void *__nouveau_fence_ref(void *obj);
1305
1306static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1307{
1308 return __nouveau_fence_signalled(obj, NULL);
1309}
1310static inline int
1311nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1312{
1313 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1314}
2730723b 1315extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1316static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1317{
1318 return __nouveau_fence_flush(obj, NULL);
1319}
1320static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1321{
1322 __nouveau_fence_unref((void **)obj);
1323}
1324static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1325{
1326 return __nouveau_fence_ref(obj);
1327}
6ee73861
BS		 1328
1329/* nouveau_gem.c */
1330extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1331 int size, int align, uint32_t flags,
1332 uint32_t tile_mode, uint32_t tile_flags,
1333 bool no_vm, bool mappable, struct nouveau_bo **);
1334extern int nouveau_gem_object_new(struct drm_gem_object *);
1335extern void nouveau_gem_object_del(struct drm_gem_object *);
1336extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1337 struct drm_file *);
1338extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1339 struct drm_file *);
6ee73861
BS		 1340extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1341 struct drm_file *);
1342extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1343 struct drm_file *);
1344extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1345 struct drm_file *);
1346
042206c0
FJ		 1347/* nouveau_display.c */
1348int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1349void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1350int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1351 struct drm_pending_vblank_event *event);
1352int nouveau_finish_page_flip(struct nouveau_channel *,
1353 struct nouveau_page_flip_state *);
042206c0 1354
ee2e0131
BS		 1355/* nv10_gpio.c */
1356int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1357int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1358
45284162 1359/* nv50_gpio.c */
ee2e0131 1360int nv50_gpio_init(struct drm_device *dev);
2cbd4c81 1361void nv50_gpio_fini(struct drm_device *dev);
45284162
BS		 1362int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1363int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
fce2bad0
BS		 1364int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1365 void (*)(void *, int), void *);
1366void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1367 void (*)(void *, int), void *);
1368bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1369
e9ebb68b
BS		 1370/* nv50_calc. */
1371int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1372 int *N1, int *M1, int *N2, int *M2, int *P);
1373int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1374 int clk, int *N, int *fN, int *M, int *P);
1375
6ee73861
BS		 1376#ifndef ioread32_native
1377#ifdef __BIG_ENDIAN
1378#define ioread16_native ioread16be
1379#define iowrite16_native iowrite16be
1380#define ioread32_native ioread32be
1381#define iowrite32_native iowrite32be
1382#else /* def __BIG_ENDIAN */
1383#define ioread16_native ioread16
1384#define iowrite16_native iowrite16
1385#define ioread32_native ioread32
1386#define iowrite32_native iowrite32
1387#endif /* def __BIG_ENDIAN else */
1388#endif /* !ioread32_native */
1389
1390/* channel control reg access */
1391static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1392{
1393 return ioread32_native(chan->user + reg);
1394}
1395
1396static inline void nvchan_wr32(struct nouveau_channel *chan,
1397 unsigned reg, u32 val)
1398{
1399 iowrite32_native(val, chan->user + reg);
1400}
1401
1402/* register access */
1403static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1404{
1405 struct drm_nouveau_private *dev_priv = dev->dev_private;
1406 return ioread32_native(dev_priv->mmio + reg);
1407}
1408
1409static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1410{
1411 struct drm_nouveau_private *dev_priv = dev->dev_private;
1412 iowrite32_native(val, dev_priv->mmio + reg);
1413}
1414
2a7fdb2b 1415static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1416{
1417 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1418 nv_wr32(dev, reg, (tmp & ~mask) | val);
1419 return tmp;
49eed80a
BS		 1420}
1421
6ee73861
BS		 1422static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1423{
1424 struct drm_nouveau_private *dev_priv = dev->dev_private;
1425 return ioread8(dev_priv->mmio + reg);
1426}
1427
1428static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1429{
1430 struct drm_nouveau_private *dev_priv = dev->dev_private;
1431 iowrite8(val, dev_priv->mmio + reg);
1432}
1433
4b5c152a 1434#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1435 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1436
1437/* PRAMIN access */
1438static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1439{
1440 struct drm_nouveau_private *dev_priv = dev->dev_private;
1441 return ioread32_native(dev_priv->ramin + offset);
1442}
1443
1444static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1445{
1446 struct drm_nouveau_private *dev_priv = dev->dev_private;
1447 iowrite32_native(val, dev_priv->ramin + offset);
1448}
1449
1450/* object access */
b3beb167
BS		 1451extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1452extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1453
1454/*
1455 * Logging
1456 * Argument d is (struct drm_device *).
1457 */
1458#define NV_PRINTK(level, d, fmt, arg...) \
1459 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1460 pci_name(d->pdev), ##arg)
1461#ifndef NV_DEBUG_NOTRACE
1462#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1463 if (drm_debug & DRM_UT_DRIVER) { \
1464 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1465 __LINE__, ##arg); \
1466 } \
1467} while (0)
1468#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1469 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1470 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1471 __LINE__, ##arg); \
1472 } \
1473} while (0)
1474#else
1475#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1476 if (drm_debug & DRM_UT_DRIVER) \
1477 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1478} while (0)
1479#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1480 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1481 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1482} while (0)
1483#endif
1484#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1485#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1486#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1487#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1488#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1489
1490/* nouveau_reg_debug bitmask */
1491enum {
1492 NOUVEAU_REG_DEBUG_MC = 0x1,
1493 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1494 NOUVEAU_REG_DEBUG_FB = 0x4,
1495 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1496 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1497 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1498 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1499 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1500 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1501 NOUVEAU_REG_DEBUG_EVO = 0x200,
1502};
1503
1504#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1505 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1506 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1507} while (0)
1508
1509static inline bool
1510nv_two_heads(struct drm_device *dev)
1511{
1512 struct drm_nouveau_private *dev_priv = dev->dev_private;
1513 const int impl = dev->pci_device & 0x0ff0;
1514
1515 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1516 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1517 return true;
1518
1519 return false;
1520}
1521
1522static inline bool
1523nv_gf4_disp_arch(struct drm_device *dev)
1524{
1525 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1526}
1527
1528static inline bool
1529nv_two_reg_pll(struct drm_device *dev)
1530{
1531 struct drm_nouveau_private *dev_priv = dev->dev_private;
1532 const int impl = dev->pci_device & 0x0ff0;
1533
1534 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1535 return true;
1536 return false;
1537}
1538
acae116c
FJ		 1539static inline bool
1540nv_match_device(struct drm_device *dev, unsigned device,
1541 unsigned sub_vendor, unsigned sub_device)
1542{
1543 return dev->pdev->device == device &&
1544 dev->pdev->subsystem_vendor == sub_vendor &&
1545 dev->pdev->subsystem_device == sub_device;
1546}
1547
f03a314b
FJ		 1548#define NV_SW 0x0000506e
1549#define NV_SW_DMA_SEMAPHORE 0x00000060
1550#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1551#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1552#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1553#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1554#define NV_SW_DMA_VBLSEM 0x0000018c
1555#define NV_SW_VBLSEM_OFFSET 0x00000400
1556#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1557#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1558#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1559
1560#endif /* __NOUVEAU_DRV_H__ */
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