]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/nouveau/nouveau_drv.h
UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
f887c425 29#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
6ee73861
BS
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
f887c425 33#define DRIVER_DATE "20120316"
6ee73861 34
f887c425 35#define DRIVER_MAJOR 1
6ee73861 36#define DRIVER_MINOR 0
f887c425 37#define DRIVER_PATCHLEVEL 0
6ee73861
BS
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
760285e7
DH
42#include <drm/ttm/ttm_bo_api.h>
43#include <drm/ttm/ttm_bo_driver.h>
44#include <drm/ttm/ttm_placement.h>
45#include <drm/ttm/ttm_memory.h>
46#include <drm/ttm/ttm_module.h>
6ee73861
BS
47
48struct nouveau_fpriv {
3f0a68d8 49 spinlock_t lock;
e8a863c1 50 struct list_head channels;
fe32b16e 51 struct nouveau_vm *vm;
6ee73861
BS
52};
53
3f0a68d8
BS
54static inline struct nouveau_fpriv *
55nouveau_fpriv(struct drm_file *file_priv)
56{
57 return file_priv ? file_priv->driver_priv : NULL;
58}
59
6ee73861
BS
60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
760285e7 62#include <drm/nouveau_drm.h>
6ee73861
BS
63#include "nouveau_reg.h"
64#include "nouveau_bios.h"
274fec93 65#include "nouveau_util.h"
f869ef88 66
054b93e4 67struct nouveau_grctx;
d5f42394 68struct nouveau_mem;
f869ef88 69#include "nouveau_vm.h"
6ee73861
BS
70
71#define MAX_NUM_DCB_ENTRIES 16
72
5132f377 73#define NOUVEAU_MAX_CHANNEL_NR 4096
a0af9add 74#define NOUVEAU_MAX_TILE_NR 15
6ee73861 75
d5f42394 76struct nouveau_mem {
573a2a37
BS
77 struct drm_device *dev;
78
f869ef88 79 struct nouveau_vma bar_vma;
d2f96666 80 struct nouveau_vma vma[2];
4c74eb7f 81 u8 page_shift;
f869ef88 82
8f7286f8 83 struct drm_mm_node *tag;
573a2a37 84 struct list_head regions;
26c0c9e3 85 dma_addr_t *pages;
573a2a37
BS
86 u32 memtype;
87 u64 offset;
88 u64 size;
22b33e8e 89 struct sg_table *sg;
573a2a37
BS
90};
91
a0af9add 92struct nouveau_tile_reg {
a0af9add 93 bool used;
a5cf68b0
FJ
94 uint32_t addr;
95 uint32_t limit;
96 uint32_t pitch;
87a326a3
FJ
97 uint32_t zcomp;
98 struct drm_mm_node *tag_mem;
a5cf68b0 99 struct nouveau_fence *fence;
a0af9add
FJ
100};
101
6ee73861
BS
102struct nouveau_bo {
103 struct ttm_buffer_object bo;
104 struct ttm_placement placement;
db5c8e29 105 u32 valid_domains;
6ee73861 106 u32 placements[3];
78ad0f7b 107 u32 busy_placements[3];
6ee73861
BS
108 struct ttm_bo_kmap_obj kmap;
109 struct list_head head;
110
111 /* protected by ttm_bo_reserve() */
112 struct drm_file *reserved_by;
113 struct list_head entry;
114 int pbbo_index;
a1606a95 115 bool validate_mapped;
6ee73861 116
fd2871af 117 struct list_head vma_list;
f91bac5b 118 unsigned page_shift;
6ee73861
BS
119
120 uint32_t tile_mode;
121 uint32_t tile_flags;
a0af9add 122 struct nouveau_tile_reg *tile;
6ee73861
BS
123
124 struct drm_gem_object *gem;
6ee73861 125 int pin_refcnt;
35916ace
DA
126
127 struct ttm_bo_kmap_obj dma_buf_vmap;
128 int vmapping_count;
6ee73861
BS
129};
130
f13b3263
FJ
131#define nouveau_bo_tile_layout(nvbo) \
132 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
133
6ee73861
BS
134static inline struct nouveau_bo *
135nouveau_bo(struct ttm_buffer_object *bo)
136{
137 return container_of(bo, struct nouveau_bo, bo);
138}
139
140static inline struct nouveau_bo *
141nouveau_gem_object(struct drm_gem_object *gem)
142{
143 return gem ? gem->driver_private : NULL;
144}
145
146/* TODO: submit equivalent to TTM generic API upstream? */
147static inline void __iomem *
148nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
149{
150 bool is_iomem;
151 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
152 &nvbo->kmap, &is_iomem);
153 WARN_ON_ONCE(ioptr && !is_iomem);
154 return ioptr;
155}
156
6ee73861
BS
157enum nouveau_flags {
158 NV_NFORCE = 0x10000000,
159 NV_NFORCE2 = 0x20000000
160};
161
162#define NVOBJ_ENGINE_SW 0
163#define NVOBJ_ENGINE_GR 1
6dfdd7a6 164#define NVOBJ_ENGINE_CRYPT 2
7ff5441e
BS
165#define NVOBJ_ENGINE_COPY0 3
166#define NVOBJ_ENGINE_COPY1 4
a02ccc7f 167#define NVOBJ_ENGINE_MPEG 5
8f27c543
BS
168#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
169#define NVOBJ_ENGINE_BSP 6
170#define NVOBJ_ENGINE_VP 7
c420b2dc
BS
171#define NVOBJ_ENGINE_FIFO 14
172#define NVOBJ_ENGINE_FENCE 15
6dfdd7a6 173#define NVOBJ_ENGINE_NR 16
c420b2dc 174#define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/
6ee73861 175
a11c3198 176#define NVOBJ_FLAG_DONT_MAP (1 << 0)
6ee73861
BS
177#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
178#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
34cf01bc 179#define NVOBJ_FLAG_VM (1 << 3)
c906ca0f 180#define NVOBJ_FLAG_VM_USER (1 << 4)
e41115d0
BS
181
182#define NVOBJ_CINST_GLOBAL 0xdeadbeef
183
6ee73861 184struct nouveau_gpuobj {
b3beb167 185 struct drm_device *dev;
eb9bcbdc 186 struct kref refcount;
6ee73861
BS
187 struct list_head list;
188
e41115d0 189 void *node;
dc1e5c0d 190 u32 *suspend;
6ee73861
BS
191
192 uint32_t flags;
6ee73861 193
43efc9ce 194 u32 size;
f8522fc8
BS
195 u32 pinst; /* PRAMIN BAR offset */
196 u32 cinst; /* Channel offset */
197 u64 vinst; /* VRAM address */
198 u64 linst; /* VM address */
de3a6c0a 199
6ee73861
BS
200 uint32_t engine;
201 uint32_t class;
202
203 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
204 void *priv;
205};
206
332b242f
FJ
207struct nouveau_page_flip_state {
208 struct list_head head;
209 struct drm_pending_vblank_event *event;
210 int crtc, bpp, pitch, x, y;
211 uint64_t offset;
212};
213
e419cf09
FJ
214enum nouveau_channel_mutex_class {
215 NOUVEAU_UCHANNEL_MUTEX,
216 NOUVEAU_KCHANNEL_MUTEX
217};
218
6ee73861
BS
219struct nouveau_channel {
220 struct drm_device *dev;
e8a863c1 221 struct list_head list;
6ee73861
BS
222 int id;
223
f091a3d4
FJ
224 /* references to the channel data structure */
225 struct kref ref;
226 /* users of the hardware channel resources, the hardware
227 * context will be kicked off when it reaches zero. */
228 atomic_t users;
6a6b73f2
BS
229 struct mutex mutex;
230
6ee73861
BS
231 /* owner of this fifo */
232 struct drm_file *file_priv;
233 /* mapping of the fifo itself */
234 struct drm_local_map *map;
235
25985edc 236 /* mapping of the regs controlling the fifo */
6ee73861
BS
237 void __iomem *user;
238 uint32_t user_get;
4e03b4af 239 uint32_t user_get_hi;
6ee73861
BS
240 uint32_t user_put;
241
6ee73861 242 /* DMA push buffer */
a8eaebc6
BS
243 struct nouveau_gpuobj *pushbuf;
244 struct nouveau_bo *pushbuf_bo;
ce163f69 245 struct nouveau_vma pushbuf_vma;
4e03b4af 246 uint64_t pushbuf_base;
6ee73861
BS
247
248 /* Notifier memory */
249 struct nouveau_bo *notifier_bo;
0b718733 250 struct nouveau_vma notifier_vma;
b833ac26 251 struct drm_mm notifier_heap;
6ee73861
BS
252
253 /* PFIFO context */
a8eaebc6 254 struct nouveau_gpuobj *ramfc;
6ee73861 255
a82dd49f 256 /* Execution engine contexts */
6dfdd7a6 257 void *engctx[NVOBJ_ENGINE_NR];
6ee73861
BS
258
259 /* NV50 VM */
f869ef88 260 struct nouveau_vm *vm;
a8eaebc6 261 struct nouveau_gpuobj *vm_pd;
6ee73861
BS
262
263 /* Objects */
a8eaebc6
BS
264 struct nouveau_gpuobj *ramin; /* Private instmem */
265 struct drm_mm ramin_heap; /* Private PRAMIN heap */
266 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS
267
268 /* GPU object info for stuff used in-kernel (mm_enabled) */
269 uint32_t m2mf_ntfy;
270 uint32_t vram_handle;
271 uint32_t gart_handle;
272 bool accel_done;
273
274 /* Push buffer state (only for drm's channel on !mm_enabled) */
275 struct {
276 int max;
277 int free;
278 int cur;
279 int put;
280 /* access via pushbuf_bo */
9a391ad8
BS
281
282 int ib_base;
283 int ib_max;
284 int ib_free;
285 int ib_put;
6ee73861
BS
286 } dma;
287
6ee73861
BS
288 struct {
289 bool active;
290 char name[32];
291 struct drm_info_list info;
292 } debugfs;
293};
294
6dfdd7a6
BS
295struct nouveau_exec_engine {
296 void (*destroy)(struct drm_device *, int engine);
297 int (*init)(struct drm_device *, int engine);
6c320fef 298 int (*fini)(struct drm_device *, int engine, bool suspend);
6dfdd7a6
BS
299 int (*context_new)(struct nouveau_channel *, int engine);
300 void (*context_del)(struct nouveau_channel *, int engine);
301 int (*object_new)(struct nouveau_channel *, int engine,
302 u32 handle, u16 class);
96c50082 303 void (*set_tile_region)(struct drm_device *dev, int i);
6dfdd7a6
BS
304 void (*tlb_flush)(struct drm_device *, int engine);
305};
306
6ee73861
BS
307struct nouveau_instmem_engine {
308 void *priv;
309
310 int (*init)(struct drm_device *dev);
311 void (*takedown)(struct drm_device *dev);
312 int (*suspend)(struct drm_device *dev);
313 void (*resume)(struct drm_device *dev);
314
6e32fedc
BS
315 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
316 u32 size, u32 align);
e41115d0
BS
317 void (*put)(struct nouveau_gpuobj *);
318 int (*map)(struct nouveau_gpuobj *);
319 void (*unmap)(struct nouveau_gpuobj *);
320
f56cb86f 321 void (*flush)(struct drm_device *);
6ee73861
BS
322};
323
324struct nouveau_mc_engine {
325 int (*init)(struct drm_device *dev);
326 void (*takedown)(struct drm_device *dev);
327};
328
329struct nouveau_timer_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 uint64_t (*read)(struct drm_device *dev);
333};
334
335struct nouveau_fb_engine {
cb00f7c1 336 int num_tiles;
87a326a3 337 struct drm_mm tag_heap;
20f63afe 338 void *priv;
cb00f7c1 339
6ee73861
BS
340 int (*init)(struct drm_device *dev);
341 void (*takedown)(struct drm_device *dev);
cb00f7c1 342
a5cf68b0
FJ
343 void (*init_tile_region)(struct drm_device *dev, int i,
344 uint32_t addr, uint32_t size,
345 uint32_t pitch, uint32_t flags);
346 void (*set_tile_region)(struct drm_device *dev, int i);
347 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS
348};
349
c88c2e06 350struct nouveau_display_engine {
ef8389a8 351 void *priv;
c88c2e06
FJ
352 int (*early_init)(struct drm_device *);
353 void (*late_takedown)(struct drm_device *);
354 int (*create)(struct drm_device *);
c88c2e06 355 void (*destroy)(struct drm_device *);
2a44e499
BS
356 int (*init)(struct drm_device *);
357 void (*fini)(struct drm_device *);
b29caa58 358
de691855
BS
359 struct drm_property *dithering_mode;
360 struct drm_property *dithering_depth;
b29caa58
BS
361 struct drm_property *underscan_property;
362 struct drm_property *underscan_hborder_property;
363 struct drm_property *underscan_vborder_property;
df26bc9c
CB
364 /* not really hue and saturation: */
365 struct drm_property *vibrant_hue_property;
366 struct drm_property *color_vibrance_property;
c88c2e06
FJ
367};
368
ee2e0131 369struct nouveau_gpio_engine {
a0b25635
BS
370 spinlock_t lock;
371 struct list_head isr;
372 int (*init)(struct drm_device *);
373 void (*fini)(struct drm_device *);
374 int (*drive)(struct drm_device *, int line, int dir, int out);
375 int (*sense)(struct drm_device *, int line);
376 void (*irq_enable)(struct drm_device *, int line, bool);
ee2e0131
BS
377};
378
330c5988 379struct nouveau_pm_voltage_level {
c3450239
BS
380 u32 voltage; /* microvolts */
381 u8 vid;
330c5988
BS
382};
383
384struct nouveau_pm_voltage {
385 bool supported;
03ce8d9e 386 u8 version;
330c5988
BS
387 u8 vid_mask;
388
389 struct nouveau_pm_voltage_level *level;
390 int nr_level;
391};
392
c7c039fd
RS
393/* Exclusive upper limits */
394#define NV_MEM_CL_DDR2_MAX 8
395#define NV_MEM_WR_DDR2_MAX 9
396#define NV_MEM_CL_DDR3_MAX 17
397#define NV_MEM_WR_DDR3_MAX 17
398#define NV_MEM_CL_GDDR3_MAX 16
399#define NV_MEM_WR_GDDR3_MAX 18
400#define NV_MEM_CL_GDDR5_MAX 21
401#define NV_MEM_WR_GDDR5_MAX 20
402
e614b2e7
MP
403struct nouveau_pm_memtiming {
404 int id;
c7c039fd
RS
405
406 u32 reg[9];
407 u32 mr[4];
408
bfb31465
RS
409 u8 tCWL;
410
c7c039fd
RS
411 u8 odt;
412 u8 drive_strength;
9a782488
RS
413};
414
ddb20055 415struct nouveau_pm_tbl_header {
9a782488
RS
416 u8 version;
417 u8 header_len;
418 u8 entry_cnt;
419 u8 entry_len;
420};
421
ddb20055 422struct nouveau_pm_tbl_entry {
2228c6fe 423 u8 tWR;
bfb31465 424 u8 tWTR;
2228c6fe 425 u8 tCL;
bfb31465 426 u8 tRC;
9a782488 427 u8 empty_4;
bfb31465 428 u8 tRFC; /* Byte 5 */
9a782488 429 u8 empty_6;
bfb31465 430 u8 tRAS; /* Byte 7 */
9a782488 431 u8 empty_8;
bfb31465
RS
432 u8 tRP; /* Byte 9 */
433 u8 tRCDRD;
434 u8 tRCDWR;
435 u8 tRRD;
436 u8 tUNK_13;
437 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
438 u8 empty_15;
439 u8 tUNK_16;
440 u8 empty_17;
441 u8 tUNK_18;
442 u8 tCWL;
443 u8 tUNK_20, tUNK_21;
9a782488
RS
444};
445
8d7bb400
BS
446struct nouveau_pm_profile;
447struct nouveau_pm_profile_func {
25c53c10
BS
448 void (*destroy)(struct nouveau_pm_profile *);
449 void (*init)(struct nouveau_pm_profile *);
450 void (*fini)(struct nouveau_pm_profile *);
8d7bb400
BS
451 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
452};
453
454struct nouveau_pm_profile {
455 const struct nouveau_pm_profile_func *func;
456 struct list_head head;
457 char name[8];
458};
459
330c5988
BS
460#define NOUVEAU_PM_MAX_LEVEL 8
461struct nouveau_pm_level {
8d7bb400 462 struct nouveau_pm_profile profile;
330c5988
BS
463 struct device_attribute dev_attr;
464 char name[32];
465 int id;
466
8d7bb400 467 struct nouveau_pm_memtiming timing;
330c5988 468 u32 memory;
085028ce 469 u16 memscript;
085028ce
BS
470
471 u32 core;
330c5988 472 u32 shader;
9698b9a6
BS
473 u32 rop;
474 u32 copy;
475 u32 daemon;
4fd2847e 476 u32 vdec;
f3fbaf34 477 u32 dom6;
9698b9a6
BS
478 u32 unka0; /* nva3:nvc0 */
479 u32 hub01; /* nvc0- */
480 u32 hub06; /* nvc0- */
481 u32 hub07; /* nvc0- */
330c5988 482
3b5565dd
BS
483 u32 volt_min; /* microvolts */
484 u32 volt_max;
c3450239 485 u8 fanspeed;
330c5988
BS
486};
487
34e9d85a
MP
488struct nouveau_pm_temp_sensor_constants {
489 u16 offset_constant;
490 s16 offset_mult;
40ce4279
EV
491 s16 offset_div;
492 s16 slope_mult;
493 s16 slope_div;
34e9d85a
MP
494};
495
496struct nouveau_pm_threshold_temp {
497 s16 critical;
498 s16 down_clock;
499 s16 fan_boost;
500};
501
11b7d895 502struct nouveau_pm_fan {
bc6389e4 503 u32 percent;
11b7d895
MP
504 u32 min_duty;
505 u32 max_duty;
3f8e11e4 506 u32 pwm_freq;
b1aa5531 507 u32 pwm_divisor;
11b7d895
MP
508};
509
330c5988
BS
510struct nouveau_pm_engine {
511 struct nouveau_pm_voltage voltage;
512 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
513 int nr_perflvl;
34e9d85a
MP
514 struct nouveau_pm_temp_sensor_constants sensor_constants;
515 struct nouveau_pm_threshold_temp threshold_temp;
11b7d895 516 struct nouveau_pm_fan fan;
330c5988 517
8d7bb400
BS
518 struct nouveau_pm_profile *profile_ac;
519 struct nouveau_pm_profile *profile_dc;
25c53c10 520 struct nouveau_pm_profile *profile;
8d7bb400
BS
521 struct list_head profiles;
522
330c5988
BS
523 struct nouveau_pm_level boot;
524 struct nouveau_pm_level *cur;
525
8155cac4 526 struct device *hwmon;
6032649d 527 struct notifier_block acpi_nb;
8155cac4 528
77e7da68
BS
529 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
530 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
dd1da8de 531 int (*clocks_set)(struct drm_device *, void *);
77e7da68 532
330c5988
BS
533 int (*voltage_get)(struct drm_device *);
534 int (*voltage_set)(struct drm_device *, int voltage);
675aac03
BS
535 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
536 int (*pwm_set)(struct drm_device *, int line, u32, u32);
8155cac4 537 int (*temp_get)(struct drm_device *);
330c5988
BS
538};
539
60d2a88a 540struct nouveau_vram_engine {
987eec10 541 struct nouveau_mm mm;
24f246ac 542
60d2a88a 543 int (*init)(struct drm_device *);
24f246ac 544 void (*takedown)(struct drm_device *dev);
60d2a88a 545 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
d5f42394
BS
546 u32 type, struct nouveau_mem **);
547 void (*put)(struct drm_device *, struct nouveau_mem **);
60d2a88a
BS
548
549 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
550};
551
6ee73861
BS
552struct nouveau_engine {
553 struct nouveau_instmem_engine instmem;
554 struct nouveau_mc_engine mc;
555 struct nouveau_timer_engine timer;
556 struct nouveau_fb_engine fb;
c88c2e06 557 struct nouveau_display_engine display;
ee2e0131 558 struct nouveau_gpio_engine gpio;
330c5988 559 struct nouveau_pm_engine pm;
60d2a88a 560 struct nouveau_vram_engine vram;
6ee73861
BS
561};
562
563struct nouveau_pll_vals {
564 union {
565 struct {
566#ifdef __BIG_ENDIAN
567 uint8_t N1, M1, N2, M2;
568#else
569 uint8_t M1, N1, M2, N2;
570#endif
571 };
572 struct {
573 uint16_t NM1, NM2;
574 } __attribute__((packed));
575 };
576 int log2P;
577
578 int refclk;
579};
580
581enum nv04_fp_display_regs {
582 FP_DISPLAY_END,
583 FP_TOTAL,
584 FP_CRTC,
585 FP_SYNC_START,
586 FP_SYNC_END,
587 FP_VALID_START,
588 FP_VALID_END
589};
590
591struct nv04_crtc_reg {
cbab95db 592 unsigned char MiscOutReg;
4a9f822f 593 uint8_t CRTC[0xa0];
6ee73861
BS
594 uint8_t CR58[0x10];
595 uint8_t Sequencer[5];
596 uint8_t Graphics[9];
597 uint8_t Attribute[21];
cbab95db 598 unsigned char DAC[768];
6ee73861
BS
599
600 /* PCRTC regs */
601 uint32_t fb_start;
602 uint32_t crtc_cfg;
603 uint32_t cursor_cfg;
604 uint32_t gpio_ext;
605 uint32_t crtc_830;
606 uint32_t crtc_834;
607 uint32_t crtc_850;
608 uint32_t crtc_eng_ctrl;
609
610 /* PRAMDAC regs */
611 uint32_t nv10_cursync;
612 struct nouveau_pll_vals pllvals;
613 uint32_t ramdac_gen_ctrl;
614 uint32_t ramdac_630;
615 uint32_t ramdac_634;
616 uint32_t tv_setup;
617 uint32_t tv_vtotal;
618 uint32_t tv_vskew;
619 uint32_t tv_vsync_delay;
620 uint32_t tv_htotal;
621 uint32_t tv_hskew;
622 uint32_t tv_hsync_delay;
623 uint32_t tv_hsync_delay2;
624 uint32_t fp_horiz_regs[7];
625 uint32_t fp_vert_regs[7];
626 uint32_t dither;
627 uint32_t fp_control;
628 uint32_t dither_regs[6];
629 uint32_t fp_debug_0;
630 uint32_t fp_debug_1;
631 uint32_t fp_debug_2;
632 uint32_t fp_margin_color;
633 uint32_t ramdac_8c0;
634 uint32_t ramdac_a20;
635 uint32_t ramdac_a24;
636 uint32_t ramdac_a34;
637 uint32_t ctv_regs[38];
638};
639
640struct nv04_output_reg {
641 uint32_t output;
642 int head;
643};
644
645struct nv04_mode_state {
cbab95db 646 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS
647 uint32_t pllsel;
648 uint32_t sel_clk;
6ee73861
BS
649};
650
651enum nouveau_card_type {
2f5394c3 652 NV_04 = 0x04,
6ee73861
BS
653 NV_10 = 0x10,
654 NV_20 = 0x20,
655 NV_30 = 0x30,
656 NV_40 = 0x40,
657 NV_50 = 0x50,
4b223eef 658 NV_C0 = 0xc0,
2f5394c3 659 NV_D0 = 0xd0,
68455a43 660 NV_E0 = 0xe0,
6ee73861
BS
661};
662
663struct drm_nouveau_private {
664 struct drm_device *dev;
aba99a84 665 bool noaccel;
6ee73861
BS
666
667 /* the card type, takes NV_* as values */
668 enum nouveau_card_type card_type;
669 /* exact chipset, derived from NV_PMC_BOOT_0 */
670 int chipset;
671 int flags;
f2cbe46f 672 u32 crystal;
6ee73861
BS
673
674 void __iomem *mmio;
5125bfd8 675
e05d7eae 676 spinlock_t ramin_lock;
6ee73861 677 void __iomem *ramin;
5125bfd8
BS
678 u32 ramin_size;
679 u32 ramin_base;
680 bool ramin_available;
e05d7eae 681 struct drm_mm ramin_heap;
6dfdd7a6 682 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
e05d7eae 683 struct list_head gpuobj_list;
b8c157d3 684 struct list_head classes;
6ee73861 685
ac8fb975
BS
686 struct nouveau_bo *vga_ram;
687
35fa2f2a 688 /* interrupt handling */
8f8a5448 689 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 690 bool msi_enabled;
ab838338 691
6ee73861 692 struct {
ba4420c2 693 struct drm_global_reference mem_global_ref;
6ee73861
BS
694 struct ttm_bo_global_ref bo_global_ref;
695 struct ttm_bo_device bdev;
6ee73861 696 atomic_t validate_sequence;
d1b167e1
BS
697 int (*move)(struct nouveau_channel *,
698 struct ttm_buffer_object *,
699 struct ttm_mem_reg *, struct ttm_mem_reg *);
6ee73861
BS
700 } ttm;
701
0c6c1c2f
FJ
702 struct {
703 spinlock_t lock;
704 struct drm_mm heap;
705 struct nouveau_bo *bo;
706 } fence;
707
cff5c133
BS
708 struct {
709 spinlock_t lock;
710 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
711 } channels;
6ee73861
BS
712
713 struct nouveau_engine engine;
714 struct nouveau_channel *channel;
715
ff9e5279
MM
716 /* For PFIFO and PGRAPH. */
717 spinlock_t context_switch_lock;
718
04eb34a4
BS
719 /* VM/PRAMIN flush, legacy PRAMIN aperture */
720 spinlock_t vm_lock;
721
6ee73861 722 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS
723 struct nouveau_ramht *ramht;
724 struct nouveau_gpuobj *ramfc;
725 struct nouveau_gpuobj *ramro;
726
6ee73861 727 uint32_t ramin_rsvd_vram;
6ee73861 728
6ee73861
BS
729 struct {
730 enum {
731 NOUVEAU_GART_NONE = 0,
58e6c7a9
BS
732 NOUVEAU_GART_AGP, /* AGP */
733 NOUVEAU_GART_PDMA, /* paged dma object */
734 NOUVEAU_GART_HW /* on-chip gart/vm */
6ee73861
BS
735 } type;
736 uint64_t aper_base;
737 uint64_t aper_size;
738 uint64_t aper_free;
739
7948758d
BS
740 struct ttm_backend_func *func;
741
742 struct {
743 struct page *page;
744 dma_addr_t addr;
745 } dummy;
746
6ee73861 747 struct nouveau_gpuobj *sg_ctxdma;
6ee73861
BS
748 } gart_info;
749
a0af9add 750 /* nv10-nv40 tiling regions */
a5cf68b0
FJ
751 struct {
752 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
753 spinlock_t lock;
754 } tile;
a0af9add 755
a76fb4e8 756 /* VRAM/fb configuration */
7ad2d31c
BS
757 enum {
758 NV_MEM_TYPE_UNKNOWN = 0,
759 NV_MEM_TYPE_STOLEN,
760 NV_MEM_TYPE_SGRAM,
761 NV_MEM_TYPE_SDRAM,
762 NV_MEM_TYPE_DDR1,
763 NV_MEM_TYPE_DDR2,
764 NV_MEM_TYPE_DDR3,
765 NV_MEM_TYPE_GDDR2,
766 NV_MEM_TYPE_GDDR3,
767 NV_MEM_TYPE_GDDR4,
768 NV_MEM_TYPE_GDDR5
769 } vram_type;
a76fb4e8
BS
770 uint64_t vram_size;
771 uint64_t vram_sys_base;
c7c039fd 772 bool vram_rank_B;
a76fb4e8 773
a76fb4e8
BS
774 uint64_t fb_available_size;
775 uint64_t fb_mappable_pages;
776 uint64_t fb_aper_free;
777 int fb_mtrr;
778
f869ef88
BS
779 /* BAR control (NV50-) */
780 struct nouveau_vm *bar1_vm;
781 struct nouveau_vm *bar3_vm;
782
6ee73861 783 /* G8x/G9x virtual address space */
4c136142 784 struct nouveau_vm *chan_vm;
6ee73861 785
04a39c57 786 struct nvbios vbios;
b4c26818 787 u8 *mxms;
486a45c2 788 struct list_head i2c_ports;
6ee73861
BS
789
790 struct nv04_mode_state mode_reg;
791 struct nv04_mode_state saved_reg;
792 uint32_t saved_vga_font[4][16384];
793 uint32_t crtc_owner;
794 uint32_t dac_users[4];
795
6ee73861 796 struct backlight_device *backlight;
6ee73861 797
6ee73861
BS
798 struct {
799 struct dentry *channel_root;
800 } debugfs;
38651674 801
8be48d92 802 struct nouveau_fbdev *nfbdev;
06415c56 803 struct apertures_struct *apertures;
6ee73861
BS
804};
805
2730723b
FJ
806static inline struct drm_nouveau_private *
807nouveau_private(struct drm_device *dev)
808{
809 return dev->dev_private;
810}
811
6ee73861
BS
812static inline struct drm_nouveau_private *
813nouveau_bdev(struct ttm_bo_device *bd)
814{
815 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
816}
817
818static inline int
819nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
820{
821 struct nouveau_bo *prev;
822
823 if (!pnvbo)
824 return -EINVAL;
825 prev = *pnvbo;
826
827 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
828 if (prev) {
829 struct ttm_buffer_object *bo = &prev->bo;
830
831 ttm_bo_unref(&bo);
832 }
833
834 return 0;
835}
836
6ee73861 837/* nouveau_drv.c */
03bc9675 838extern int nouveau_modeset;
de5899bd 839extern int nouveau_agpmode;
6ee73861
BS
840extern int nouveau_duallink;
841extern int nouveau_uscript_lvds;
842extern int nouveau_uscript_tmds;
843extern int nouveau_vram_pushbuf;
844extern int nouveau_vram_notify;
7ad2d31c 845extern char *nouveau_vram_type;
6ee73861 846extern int nouveau_fbpercrtc;
f4053509 847extern int nouveau_tv_disable;
6ee73861
BS
848extern char *nouveau_tv_norm;
849extern int nouveau_reg_debug;
850extern char *nouveau_vbios;
a1470890 851extern int nouveau_ignorelid;
a32ed69d
MK
852extern int nouveau_nofbaccel;
853extern int nouveau_noaccel;
0cba1b76 854extern int nouveau_force_post;
da647d5b 855extern int nouveau_override_conntype;
6f876986
BS
856extern char *nouveau_perflvl;
857extern int nouveau_perflvl_wr;
35fa2f2a 858extern int nouveau_msi;
0411de85 859extern int nouveau_ctxfw;
b4c26818 860extern int nouveau_mxmdcb;
6ee73861 861
6a9ee8af
DA
862extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
863extern int nouveau_pci_resume(struct pci_dev *pdev);
864
6ee73861 865/* nouveau_state.c */
3f0a68d8 866extern int nouveau_open(struct drm_device *, struct drm_file *);
6ee73861 867extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
3f0a68d8 868extern void nouveau_postclose(struct drm_device *, struct drm_file *);
6ee73861
BS
869extern int nouveau_load(struct drm_device *, unsigned long flags);
870extern int nouveau_firstopen(struct drm_device *);
871extern void nouveau_lastclose(struct drm_device *);
872extern int nouveau_unload(struct drm_device *);
12fb9525
BS
873extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
874 uint32_t reg, uint32_t mask, uint32_t val);
875extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
876 uint32_t reg, uint32_t mask, uint32_t val);
78e2933d
BS
877extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
878 bool (*cond)(void *), void *);
6ee73861
BS
879extern bool nouveau_wait_for_idle(struct drm_device *);
880extern int nouveau_card_init(struct drm_device *);
6ee73861
BS
881
882/* nouveau_mem.c */
fbd2895e
BS
883extern int nouveau_mem_vram_init(struct drm_device *);
884extern void nouveau_mem_vram_fini(struct drm_device *);
885extern int nouveau_mem_gart_init(struct drm_device *);
886extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 887extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 888extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 889extern void nouveau_mem_close(struct drm_device *);
60d2a88a 890extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
085028ce
BS
891extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
892 struct nouveau_pm_memtiming *);
fd99fd61
BS
893extern void nouveau_mem_timing_read(struct drm_device *,
894 struct nouveau_pm_memtiming *);
c70c41e8 895extern int nouveau_mem_vbios_type(struct drm_device *);
a5cf68b0
FJ
896extern struct nouveau_tile_reg *nv10_mem_set_tiling(
897 struct drm_device *dev, uint32_t addr, uint32_t size,
898 uint32_t pitch, uint32_t flags);
899extern void nv10_mem_put_tile_region(struct drm_device *dev,
900 struct nouveau_tile_reg *tile,
901 struct nouveau_fence *fence);
573a2a37 902extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
26c0c9e3 903extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
6ee73861
BS
904
905/* nouveau_notifier.c */
906extern int nouveau_notifier_init_channel(struct nouveau_channel *);
907extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
908extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
73412c38
BS
909 int cout, uint32_t start, uint32_t end,
910 uint32_t *offset);
6ee73861
BS
911
912/* nouveau_channel.c */
6ee73861 913extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS
914extern int nouveau_channel_alloc(struct drm_device *dev,
915 struct nouveau_channel **chan,
916 struct drm_file *file_priv,
917 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 918extern struct nouveau_channel *
feeb0aec
FJ
919nouveau_channel_get_unlocked(struct nouveau_channel *);
920extern struct nouveau_channel *
e8a863c1 921nouveau_channel_get(struct drm_file *, int id);
feeb0aec 922extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 923extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ
924extern void nouveau_channel_ref(struct nouveau_channel *chan,
925 struct nouveau_channel **pchan);
d1b167e1 926extern int nouveau_channel_idle(struct nouveau_channel *chan);
6ee73861 927
ce22af03 928/* nouveau_gpuobj.c */
6dfdd7a6
BS
929#define NVOBJ_ENGINE_ADD(d, e, p) do { \
930 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
931 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
932} while (0)
933
934#define NVOBJ_ENGINE_DEL(d, e) do { \
935 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
936 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
937} while (0)
938
0b89a072 939#define NVOBJ_CLASS(d, c, e) do { \
b8c157d3
BS
940 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
941 if (ret) \
942 return ret; \
71298e2f 943} while (0)
b8c157d3 944
0b89a072 945#define NVOBJ_MTHD(d, c, m, e) do { \
b8c157d3
BS
946 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
947 if (ret) \
948 return ret; \
71298e2f 949} while (0)
b8c157d3 950
6ee73861
BS
951extern int nouveau_gpuobj_early_init(struct drm_device *);
952extern int nouveau_gpuobj_init(struct drm_device *);
953extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861 954extern int nouveau_gpuobj_suspend(struct drm_device *dev);
6ee73861 955extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS
956extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
957extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
958 int (*exec)(struct nouveau_channel *,
71298e2f 959 u32 class, u32 mthd, u32 data));
b8c157d3 960extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
274fec93 961extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
6ee73861
BS
962extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
963 uint32_t vram_h, uint32_t tt_h);
964extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
965extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
966 uint32_t size, int align, uint32_t flags,
967 struct nouveau_gpuobj **);
a8eaebc6
BS
968extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
969 struct nouveau_gpuobj **);
43efc9ce
BS
970extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
971 u32 size, u32 flags,
a8eaebc6 972 struct nouveau_gpuobj **);
6ee73861
BS
973extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
974 uint64_t offset, uint64_t size, int access,
975 int target, struct nouveau_gpuobj **);
ceac3099 976extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
7f4a195f
BS
977extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
978 u64 size, int target, int access, u32 type,
979 u32 comp, struct nouveau_gpuobj **pobj);
980extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
981 int class, u64 base, u64 size, int target,
982 int access, u32 type, u32 comp);
6ee73861
BS
983
984/* nouveau_irq.c */
35fa2f2a
BS
985extern int nouveau_irq_init(struct drm_device *);
986extern void nouveau_irq_fini(struct drm_device *);
6ee73861 987extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS
988extern void nouveau_irq_register(struct drm_device *, int status_bit,
989 void (*)(struct drm_device *));
990extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS
991extern void nouveau_irq_preinstall(struct drm_device *);
992extern int nouveau_irq_postinstall(struct drm_device *);
993extern void nouveau_irq_uninstall(struct drm_device *);
994
995/* nouveau_sgdma.c */
996extern int nouveau_sgdma_init(struct drm_device *);
997extern void nouveau_sgdma_takedown(struct drm_device *);
fd70b6cd
FJ
998extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
999 uint32_t offset);
649bf3ca
JG
1000extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1001 unsigned long size,
1002 uint32_t page_flags,
1003 struct page *dummy_read_page);
6ee73861
BS
1004
1005/* nouveau_debugfs.c */
1006#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1007extern int nouveau_debugfs_init(struct drm_minor *);
1008extern void nouveau_debugfs_takedown(struct drm_minor *);
1009extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1010extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1011#else
1012static inline int
1013nouveau_debugfs_init(struct drm_minor *minor)
1014{
1015 return 0;
1016}
1017
1018static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1019{
1020}
1021
1022static inline int
1023nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1024{
1025 return 0;
1026}
1027
1028static inline void
1029nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1030{
1031}
1032#endif
1033
1034/* nouveau_dma.c */
48aca13f 1035extern void nouveau_dma_init(struct nouveau_channel *);
9a391ad8 1036extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS
1037
1038/* nouveau_acpi.c */
afeb3e11 1039#define ROM_BIOS_PAGE 4096
2f41a7f1 1040#if defined(CONFIG_ACPI)
6a9ee8af
DA
1041void nouveau_register_dsm_handler(void);
1042void nouveau_unregister_dsm_handler(void);
d099230c 1043void nouveau_switcheroo_optimus_dsm(void);
afeb3e11
DA
1044int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1045bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 1046int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA
1047#else
1048static inline void nouveau_register_dsm_handler(void) {}
1049static inline void nouveau_unregister_dsm_handler(void) {}
d099230c 1050static inline void nouveau_switcheroo_optimus_dsm(void) {}
afeb3e11
DA
1051static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1052static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 1053static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 1054#endif
6ee73861
BS
1055
1056/* nouveau_backlight.c */
1057#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
10b461e4
BS
1058extern int nouveau_backlight_init(struct drm_device *);
1059extern void nouveau_backlight_exit(struct drm_device *);
6ee73861 1060#else
10b461e4 1061static inline int nouveau_backlight_init(struct drm_device *dev)
6ee73861
BS
1062{
1063 return 0;
1064}
1065
10b461e4 1066static inline void nouveau_backlight_exit(struct drm_device *dev) { }
6ee73861
BS
1067#endif
1068
1069/* nouveau_bios.c */
1070extern int nouveau_bios_init(struct drm_device *);
1071extern void nouveau_bios_takedown(struct drm_device *dev);
1072extern int nouveau_run_vbios_init(struct drm_device *);
1073extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
02e4f587 1074 struct dcb_entry *, int crtc);
59ef9742 1075extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
6ee73861
BS
1076extern struct dcb_connector_table_entry *
1077nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 1078extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS
1079extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1080 struct pll_lims *);
02e4f587
BS
1081extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1082 struct dcb_entry *, int crtc);
6ee73861
BS
1083extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1084extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1085extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1086 bool *dl, bool *if_is_24bit);
1087extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1088 int head, int pxclk);
1089extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1090 enum LVDS_script, int pxclk);
721b0821 1091bool bios_encoder_match(struct dcb_entry *, u32 hash);
6ee73861 1092
b4c26818
BS
1093/* nouveau_mxm.c */
1094int nouveau_mxm_init(struct drm_device *dev);
1095void nouveau_mxm_fini(struct drm_device *dev);
1096
6ee73861
BS
1097/* nouveau_ttm.c */
1098int nouveau_ttm_global_init(struct drm_nouveau_private *);
1099void nouveau_ttm_global_release(struct drm_nouveau_private *);
1100int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1101
25575b41
BS
1102/* nouveau_hdmi.c */
1103void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1104
6ee73861 1105/* nv04_fb.c */
7ad2d31c 1106extern int nv04_fb_vram_init(struct drm_device *);
6ee73861
BS
1107extern int nv04_fb_init(struct drm_device *);
1108extern void nv04_fb_takedown(struct drm_device *);
1109
1110/* nv10_fb.c */
7ad2d31c
BS
1111extern int nv10_fb_vram_init(struct drm_device *dev);
1112extern int nv1a_fb_vram_init(struct drm_device *dev);
6ee73861
BS
1113extern int nv10_fb_init(struct drm_device *);
1114extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ
1115extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1116 uint32_t addr, uint32_t size,
1117 uint32_t pitch, uint32_t flags);
1118extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1119extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1120
d81c19e3
BS
1121/* nv20_fb.c */
1122extern int nv20_fb_vram_init(struct drm_device *dev);
1123extern int nv20_fb_init(struct drm_device *);
1124extern void nv20_fb_takedown(struct drm_device *);
1125extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1126 uint32_t addr, uint32_t size,
1127 uint32_t pitch, uint32_t flags);
1128extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1129extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1130
8bded189
FJ
1131/* nv30_fb.c */
1132extern int nv30_fb_init(struct drm_device *);
1133extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ
1134extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1135 uint32_t addr, uint32_t size,
1136 uint32_t pitch, uint32_t flags);
1137extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1138
6ee73861 1139/* nv40_fb.c */
ff92a6cd 1140extern int nv40_fb_vram_init(struct drm_device *dev);
6ee73861
BS
1141extern int nv40_fb_init(struct drm_device *);
1142extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ
1143extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1144
304424e1
MK
1145/* nv50_fb.c */
1146extern int nv50_fb_init(struct drm_device *);
1147extern void nv50_fb_takedown(struct drm_device *);
6fdb383e 1148extern void nv50_fb_vm_trap(struct drm_device *, int display);
304424e1 1149
4b223eef
BS
1150/* nvc0_fb.c */
1151extern int nvc0_fb_init(struct drm_device *);
1152extern void nvc0_fb_takedown(struct drm_device *);
1153
6ee73861 1154/* nv04_graph.c */
4976986b 1155extern int nv04_graph_create(struct drm_device *);
4976986b 1156extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
332b242f
FJ
1157extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1158 u32 class, u32 mthd, u32 data);
274fec93 1159extern struct nouveau_bitfield nv04_graph_nsource[];
6ee73861
BS
1160
1161/* nv10_graph.c */
d11db279 1162extern int nv10_graph_create(struct drm_device *);
6ee73861 1163extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
274fec93
BS
1164extern struct nouveau_bitfield nv10_graph_intr[];
1165extern struct nouveau_bitfield nv10_graph_nstatus[];
6ee73861
BS
1166
1167/* nv20_graph.c */
a0b1de84 1168extern int nv20_graph_create(struct drm_device *);
6ee73861
BS
1169
1170/* nv40_graph.c */
39c8d368 1171extern int nv40_graph_create(struct drm_device *);
d58086de
BS
1172extern void nv40_grctx_init(struct drm_device *, u32 *size);
1173extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
6ee73861
BS
1174
1175/* nv50_graph.c */
2703c21a 1176extern int nv50_graph_create(struct drm_device *);
6effe393 1177extern struct nouveau_enum nv50_data_error_names[];
7ff5441e 1178extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
d58086de
BS
1179extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
1180extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
6ee73861 1181
4b223eef 1182/* nvc0_graph.c */
7a45cd19 1183extern int nvc0_graph_create(struct drm_device *);
d5a27370 1184extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
4b223eef 1185
ab394543
BS
1186/* nve0_graph.c */
1187extern int nve0_graph_create(struct drm_device *);
1188
bd2e597d 1189/* nv84_crypt.c */
6dfdd7a6 1190extern int nv84_crypt_create(struct drm_device *);
bd2e597d 1191
8f27c543
BS
1192/* nv98_crypt.c */
1193extern int nv98_crypt_create(struct drm_device *dev);
1194
7ff5441e
BS
1195/* nva3_copy.c */
1196extern int nva3_copy_create(struct drm_device *dev);
1197
1198/* nvc0_copy.c */
1199extern int nvc0_copy_create(struct drm_device *dev, int engine);
1200
323dcac5
BS
1201/* nv31_mpeg.c */
1202extern int nv31_mpeg_create(struct drm_device *dev);
a02ccc7f 1203
93187450
BS
1204/* nv50_mpeg.c */
1205extern int nv50_mpeg_create(struct drm_device *dev);
c0924326 1206
8f27c543
BS
1207/* nv84_bsp.c */
1208/* nv98_bsp.c */
1209extern int nv84_bsp_create(struct drm_device *dev);
1210
1211/* nv84_vp.c */
1212/* nv98_vp.c */
1213extern int nv84_vp_create(struct drm_device *dev);
1214
1215/* nv98_ppp.c */
1216extern int nv98_ppp_create(struct drm_device *dev);
1217
6ee73861
BS
1218/* nv04_instmem.c */
1219extern int nv04_instmem_init(struct drm_device *);
1220extern void nv04_instmem_takedown(struct drm_device *);
1221extern int nv04_instmem_suspend(struct drm_device *);
1222extern void nv04_instmem_resume(struct drm_device *);
6e32fedc
BS
1223extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1224 u32 size, u32 align);
e41115d0
BS
1225extern void nv04_instmem_put(struct nouveau_gpuobj *);
1226extern int nv04_instmem_map(struct nouveau_gpuobj *);
1227extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1228extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS
1229
1230/* nv50_instmem.c */
1231extern int nv50_instmem_init(struct drm_device *);
1232extern void nv50_instmem_takedown(struct drm_device *);
1233extern int nv50_instmem_suspend(struct drm_device *);
1234extern void nv50_instmem_resume(struct drm_device *);
6e32fedc
BS
1235extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1236 u32 size, u32 align);
e41115d0
BS
1237extern void nv50_instmem_put(struct nouveau_gpuobj *);
1238extern int nv50_instmem_map(struct nouveau_gpuobj *);
1239extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1240extern void nv50_instmem_flush(struct drm_device *);
734ee835 1241extern void nv84_instmem_flush(struct drm_device *);
6ee73861 1242
4b223eef
BS
1243/* nvc0_instmem.c */
1244extern int nvc0_instmem_init(struct drm_device *);
1245extern void nvc0_instmem_takedown(struct drm_device *);
1246extern int nvc0_instmem_suspend(struct drm_device *);
1247extern void nvc0_instmem_resume(struct drm_device *);
4b223eef 1248
6ee73861
BS
1249/* nv04_mc.c */
1250extern int nv04_mc_init(struct drm_device *);
1251extern void nv04_mc_takedown(struct drm_device *);
1252
1253/* nv40_mc.c */
1254extern int nv40_mc_init(struct drm_device *);
1255extern void nv40_mc_takedown(struct drm_device *);
1256
1257/* nv50_mc.c */
1258extern int nv50_mc_init(struct drm_device *);
1259extern void nv50_mc_takedown(struct drm_device *);
1260
1261/* nv04_timer.c */
1262extern int nv04_timer_init(struct drm_device *);
1263extern uint64_t nv04_timer_read(struct drm_device *);
1264extern void nv04_timer_takedown(struct drm_device *);
1265
1266extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1267 unsigned long arg);
1268
1269/* nv04_dac.c */
8f1a6086 1270extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1271extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS
1272extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1273extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1274extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS
1275
1276/* nv04_dfp.c */
8f1a6086 1277extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS
1278extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1279extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1280 int head, bool dl);
1281extern void nv04_dfp_disable(struct drm_device *dev, int head);
1282extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1283
1284/* nv04_tv.c */
1285extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1286extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS
1287
1288/* nv17_tv.c */
8f1a6086 1289extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS
1290
1291/* nv04_display.c */
c88c2e06
FJ
1292extern int nv04_display_early_init(struct drm_device *);
1293extern void nv04_display_late_takedown(struct drm_device *);
6ee73861
BS
1294extern int nv04_display_create(struct drm_device *);
1295extern void nv04_display_destroy(struct drm_device *);
2a44e499
BS
1296extern int nv04_display_init(struct drm_device *);
1297extern void nv04_display_fini(struct drm_device *);
6ee73861 1298
26f6d88b
BS
1299/* nvd0_display.c */
1300extern int nvd0_display_create(struct drm_device *);
26f6d88b 1301extern void nvd0_display_destroy(struct drm_device *);
2a44e499
BS
1302extern int nvd0_display_init(struct drm_device *);
1303extern void nvd0_display_fini(struct drm_device *);
3376ee37
BS
1304struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1305void nvd0_display_flip_stop(struct drm_crtc *);
1306int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1307 struct nouveau_channel *, u32 swap_interval);
26f6d88b 1308
6ee73861
BS
1309/* nv04_crtc.c */
1310extern int nv04_crtc_create(struct drm_device *, int index);
1311
1312/* nouveau_bo.c */
1313extern struct ttm_bo_driver nouveau_bo_driver;
d1b167e1 1314extern void nouveau_bo_move_init(struct nouveau_channel *);
7375c95b
BS
1315extern int nouveau_bo_new(struct drm_device *, int size, int align,
1316 uint32_t flags, uint32_t tile_mode,
22b33e8e
DA
1317 uint32_t tile_flags,
1318 struct sg_table *sg,
1319 struct nouveau_bo **);
6ee73861
BS
1320extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1321extern int nouveau_bo_unpin(struct nouveau_bo *);
1322extern int nouveau_bo_map(struct nouveau_bo *);
1323extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ
1324extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1325 uint32_t busy);
6ee73861
BS
1326extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1327extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1328extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1329extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1330extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
7a45d764
BS
1331extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1332 bool no_wait_reserve, bool no_wait_gpu);
6ee73861 1333
fd2871af
BS
1334extern struct nouveau_vma *
1335nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1336extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1337 struct nouveau_vma *);
1338extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1339
6ee73861 1340/* nouveau_gem.c */
f6d4e621
BS
1341extern int nouveau_gem_new(struct drm_device *, int size, int align,
1342 uint32_t domain, uint32_t tile_mode,
1343 uint32_t tile_flags, struct nouveau_bo **);
6ee73861
BS
1344extern int nouveau_gem_object_new(struct drm_gem_object *);
1345extern void nouveau_gem_object_del(struct drm_gem_object *);
639212d0
BS
1346extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1347extern void nouveau_gem_object_close(struct drm_gem_object *,
1348 struct drm_file *);
6ee73861
BS
1349extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1350 struct drm_file *);
1351extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1352 struct drm_file *);
6ee73861
BS
1353extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1354 struct drm_file *);
1355extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1356 struct drm_file *);
1357extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1358 struct drm_file *);
1359
22b33e8e
DA
1360extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
1361 struct drm_gem_object *obj, int flags);
1362extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
1363 struct dma_buf *dma_buf);
1364
042206c0 1365/* nouveau_display.c */
27d5030a
BS
1366int nouveau_display_create(struct drm_device *dev);
1367void nouveau_display_destroy(struct drm_device *dev);
f62b27db
BS
1368int nouveau_display_init(struct drm_device *dev);
1369void nouveau_display_fini(struct drm_device *dev);
042206c0
FJ
1370int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1371void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ
1372int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1373 struct drm_pending_vblank_event *event);
1374int nouveau_finish_page_flip(struct nouveau_channel *,
1375 struct nouveau_page_flip_state *);
33dbc27f
BS
1376int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1377 struct drm_mode_create_dumb *args);
1378int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1379 uint32_t handle, uint64_t *offset);
1380int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1381 uint32_t handle);
042206c0 1382
ee2e0131 1383/* nv10_gpio.c */
a0b25635
BS
1384int nv10_gpio_init(struct drm_device *dev);
1385void nv10_gpio_fini(struct drm_device *dev);
1386int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1387int nv10_gpio_sense(struct drm_device *dev, int line);
1388void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
6ee73861 1389
45284162 1390/* nv50_gpio.c */
ee2e0131 1391int nv50_gpio_init(struct drm_device *dev);
2cbd4c81 1392void nv50_gpio_fini(struct drm_device *dev);
a0b25635
BS
1393int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1394int nv50_gpio_sense(struct drm_device *dev, int line);
1395void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1396int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1397int nvd0_gpio_sense(struct drm_device *dev, int line);
1398
1399/* nv50_calc.c */
e9ebb68b
BS
1400int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1401 int *N1, int *M1, int *N2, int *M2, int *P);
52eba8dd
BS
1402int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1403 int clk, int *N, int *fN, int *M, int *P);
e9ebb68b 1404
6ee73861
BS
1405#ifndef ioread32_native
1406#ifdef __BIG_ENDIAN
1407#define ioread16_native ioread16be
1408#define iowrite16_native iowrite16be
1409#define ioread32_native ioread32be
1410#define iowrite32_native iowrite32be
1411#else /* def __BIG_ENDIAN */
1412#define ioread16_native ioread16
1413#define iowrite16_native iowrite16
1414#define ioread32_native ioread32
1415#define iowrite32_native iowrite32
1416#endif /* def __BIG_ENDIAN else */
1417#endif /* !ioread32_native */
1418
1419/* channel control reg access */
1420static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1421{
1422 return ioread32_native(chan->user + reg);
1423}
1424
1425static inline void nvchan_wr32(struct nouveau_channel *chan,
1426 unsigned reg, u32 val)
1427{
1428 iowrite32_native(val, chan->user + reg);
1429}
1430
1431/* register access */
1432static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1433{
1434 struct drm_nouveau_private *dev_priv = dev->dev_private;
1435 return ioread32_native(dev_priv->mmio + reg);
1436}
1437
1438static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1439{
1440 struct drm_nouveau_private *dev_priv = dev->dev_private;
1441 iowrite32_native(val, dev_priv->mmio + reg);
1442}
1443
2a7fdb2b 1444static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS
1445{
1446 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS
1447 nv_wr32(dev, reg, (tmp & ~mask) | val);
1448 return tmp;
49eed80a
BS
1449}
1450
6ee73861
BS
1451static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1452{
1453 struct drm_nouveau_private *dev_priv = dev->dev_private;
1454 return ioread8(dev_priv->mmio + reg);
1455}
1456
1457static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1458{
1459 struct drm_nouveau_private *dev_priv = dev->dev_private;
1460 iowrite8(val, dev_priv->mmio + reg);
1461}
1462
4b5c152a 1463#define nv_wait(dev, reg, mask, val) \
12fb9525
BS
1464 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1465#define nv_wait_ne(dev, reg, mask, val) \
1466 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
78e2933d
BS
1467#define nv_wait_cb(dev, func, data) \
1468 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
6ee73861
BS
1469
1470/* PRAMIN access */
1471static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1472{
1473 struct drm_nouveau_private *dev_priv = dev->dev_private;
1474 return ioread32_native(dev_priv->ramin + offset);
1475}
1476
1477static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1478{
1479 struct drm_nouveau_private *dev_priv = dev->dev_private;
1480 iowrite32_native(val, dev_priv->ramin + offset);
1481}
1482
1483/* object access */
b3beb167
BS
1484extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1485extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS
1486
1487/*
1488 * Logging
1489 * Argument d is (struct drm_device *).
1490 */
1491#define NV_PRINTK(level, d, fmt, arg...) \
1492 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1493 pci_name(d->pdev), ##arg)
1494#ifndef NV_DEBUG_NOTRACE
1495#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM
1496 if (drm_debug & DRM_UT_DRIVER) { \
1497 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1498 __LINE__, ##arg); \
1499 } \
1500} while (0)
1501#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1502 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS
1503 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1504 __LINE__, ##arg); \
1505 } \
1506} while (0)
1507#else
1508#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM
1509 if (drm_debug & DRM_UT_DRIVER) \
1510 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1511} while (0)
1512#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1513 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS
1514 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1515} while (0)
1516#endif
1517#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1518#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1519#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1520#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1521#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
6b5a81a2
BS
1522#define NV_WARNONCE(d, fmt, arg...) do { \
1523 static int _warned = 0; \
1524 if (!_warned) { \
1525 NV_WARN(d, fmt, ##arg); \
1526 _warned = 1; \
1527 } \
1528} while(0)
6ee73861
BS
1529
1530/* nouveau_reg_debug bitmask */
1531enum {
1532 NOUVEAU_REG_DEBUG_MC = 0x1,
1533 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1534 NOUVEAU_REG_DEBUG_FB = 0x4,
1535 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1536 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1537 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1538 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1539 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1540 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1541 NOUVEAU_REG_DEBUG_EVO = 0x200,
43720133 1542 NOUVEAU_REG_DEBUG_AUXCH = 0x400
6ee73861
BS
1543};
1544
1545#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1546 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1547 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1548} while (0)
1549
1550static inline bool
1551nv_two_heads(struct drm_device *dev)
1552{
1553 struct drm_nouveau_private *dev_priv = dev->dev_private;
1554 const int impl = dev->pci_device & 0x0ff0;
1555
1556 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1557 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1558 return true;
1559
1560 return false;
1561}
1562
1563static inline bool
1564nv_gf4_disp_arch(struct drm_device *dev)
1565{
1566 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1567}
1568
1569static inline bool
1570nv_two_reg_pll(struct drm_device *dev)
1571{
1572 struct drm_nouveau_private *dev_priv = dev->dev_private;
1573 const int impl = dev->pci_device & 0x0ff0;
1574
1575 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1576 return true;
1577 return false;
1578}
1579
acae116c
FJ
1580static inline bool
1581nv_match_device(struct drm_device *dev, unsigned device,
1582 unsigned sub_vendor, unsigned sub_device)
1583{
1584 return dev->pdev->device == device &&
1585 dev->pdev->subsystem_vendor == sub_vendor &&
1586 dev->pdev->subsystem_device == sub_device;
1587}
1588
6dfdd7a6
BS
1589static inline void *
1590nv_engine(struct drm_device *dev, int engine)
1591{
1592 struct drm_nouveau_private *dev_priv = dev->dev_private;
1593 return (void *)dev_priv->eng[engine];
1594}
1595
c693931d
BS
1596/* returns 1 if device is one of the nv4x using the 0x4497 object class,
1597 * helpful to determine a number of other hardware features
1598 */
1599static inline int
1600nv44_graph_class(struct drm_device *dev)
1601{
1602 struct drm_nouveau_private *dev_priv = dev->dev_private;
1603
1604 if ((dev_priv->chipset & 0xf0) == 0x60)
1605 return 1;
1606
1607 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1608}
1609
7f4a195f 1610/* memory type/access flags, do not match hardware values */
a11c3198
BS
1611#define NV_MEM_ACCESS_RO 1
1612#define NV_MEM_ACCESS_WO 2
7f4a195f 1613#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
a11c3198
BS
1614#define NV_MEM_ACCESS_SYS 4
1615#define NV_MEM_ACCESS_VM 8
990449c7 1616#define NV_MEM_ACCESS_NOSNOOP 16
7f4a195f
BS
1617
1618#define NV_MEM_TARGET_VRAM 0
1619#define NV_MEM_TARGET_PCI 1
1620#define NV_MEM_TARGET_PCI_NOSNOOP 2
1621#define NV_MEM_TARGET_VM 3
1622#define NV_MEM_TARGET_GART 4
1623
1624#define NV_MEM_TYPE_VM 0x7f
1625#define NV_MEM_COMP_VM 0x03
1626
b5b2e598
BS
1627/* FIFO methods */
1628#define NV01_SUBCHAN_OBJECT 0x00000000
1629#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1630#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1631#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1632#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1633#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1634#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1635#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
5e120f6e 1636#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
b5b2e598
BS
1637#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1638#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1639#define NV10_SUBCHAN_REF_CNT 0x00000050
d5316e25 1640#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
b5b2e598
BS
1641#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1642#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1643#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1644#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1645#define NV40_SUBCHAN_YIELD 0x00000080
1646
7f4a195f 1647/* NV_SW object class */
f03a314b 1648#define NV_SW 0x0000506e
f03a314b
FJ
1649#define NV_SW_DMA_VBLSEM 0x0000018c
1650#define NV_SW_VBLSEM_OFFSET 0x00000400
1651#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1652#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1653#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS
1654
1655#endif /* __NOUVEAU_DRV_H__ */