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drm/nouveau: Fix a few confusions between "chipset" and "card_type".
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
f13b3263
FJ		 103#define nouveau_bo_tile_layout(nvbo) \
104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
105
6ee73861
BS		 106static inline struct nouveau_bo *
107nouveau_bo(struct ttm_buffer_object *bo)
108{
109 return container_of(bo, struct nouveau_bo, bo);
110}
111
112static inline struct nouveau_bo *
113nouveau_gem_object(struct drm_gem_object *gem)
114{
115 return gem ? gem->driver_private : NULL;
116}
117
118/* TODO: submit equivalent to TTM generic API upstream? */
119static inline void __iomem *
120nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
121{
122 bool is_iomem;
123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
124 &nvbo->kmap, &is_iomem);
125 WARN_ON_ONCE(ioptr && !is_iomem);
126 return ioptr;
127}
128
6ee73861
BS		 129enum nouveau_flags {
130 NV_NFORCE = 0x10000000,
131 NV_NFORCE2 = 0x20000000
132};
133
134#define NVOBJ_ENGINE_SW 0
135#define NVOBJ_ENGINE_GR 1
136#define NVOBJ_ENGINE_DISPLAY 2
137#define NVOBJ_ENGINE_INT 0xdeadbeef
138
6ee73861
BS		 139#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
140#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 141struct nouveau_gpuobj {
b3beb167 142 struct drm_device *dev;
eb9bcbdc 143 struct kref refcount;
6ee73861
BS		 144 struct list_head list;
145
b833ac26 146 struct drm_mm_node *im_pramin;
6ee73861 147 struct nouveau_bo *im_backing;
6ee73861
BS		 148 uint32_t *im_backing_suspend;
149 int im_bound;
150
151 uint32_t flags;
6ee73861 152
43efc9ce 153 u32 size;
de3a6c0a
BS		 154 u32 pinst;
155 u32 cinst;
156 u64 vinst;
157
6ee73861
BS		 158 uint32_t engine;
159 uint32_t class;
160
161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
162 void *priv;
163};
164
6ee73861
BS		 165struct nouveau_channel {
166 struct drm_device *dev;
167 int id;
168
169 /* owner of this fifo */
170 struct drm_file *file_priv;
171 /* mapping of the fifo itself */
172 struct drm_local_map *map;
173
174 /* mapping of the regs controling the fifo */
175 void __iomem *user;
176 uint32_t user_get;
177 uint32_t user_put;
178
179 /* Fencing */
180 struct {
181 /* lock protects the pending list only */
182 spinlock_t lock;
183 struct list_head pending;
184 uint32_t sequence;
185 uint32_t sequence_ack;
047d1d3c 186 atomic_t last_sequence_irq;
6ee73861
BS		 187 } fence;
188
189 /* DMA push buffer */
a8eaebc6
BS		 190 struct nouveau_gpuobj *pushbuf;
191 struct nouveau_bo *pushbuf_bo;
192 uint32_t pushbuf_base;
6ee73861
BS		 193
194 /* Notifier memory */
195 struct nouveau_bo *notifier_bo;
b833ac26 196 struct drm_mm notifier_heap;
6ee73861
BS		 197
198 /* PFIFO context */
a8eaebc6
BS		 199 struct nouveau_gpuobj *ramfc;
200 struct nouveau_gpuobj *cache;
6ee73861
BS		 201
202 /* PGRAPH context */
203 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 204 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 205 void *pgraph_ctx;
206
207 /* NV50 VM */
a8eaebc6
BS		 208 struct nouveau_gpuobj *vm_pd;
209 struct nouveau_gpuobj *vm_gart_pt;
210 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 211
212 /* Objects */
a8eaebc6
BS		 213 struct nouveau_gpuobj *ramin; /* Private instmem */
214 struct drm_mm ramin_heap; /* Private PRAMIN heap */
215 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 216
217 /* GPU object info for stuff used in-kernel (mm_enabled) */
218 uint32_t m2mf_ntfy;
219 uint32_t vram_handle;
220 uint32_t gart_handle;
221 bool accel_done;
222
223 /* Push buffer state (only for drm's channel on !mm_enabled) */
224 struct {
225 int max;
226 int free;
227 int cur;
228 int put;
229 /* access via pushbuf_bo */
9a391ad8
BS		 230
231 int ib_base;
232 int ib_max;
233 int ib_free;
234 int ib_put;
6ee73861
BS		 235 } dma;
236
237 uint32_t sw_subchannel[8];
238
239 struct {
240 struct nouveau_gpuobj *vblsem;
241 uint32_t vblsem_offset;
242 uint32_t vblsem_rval;
243 struct list_head vbl_wait;
244 } nvsw;
245
246 struct {
247 bool active;
248 char name[32];
249 struct drm_info_list info;
250 } debugfs;
251};
252
253struct nouveau_instmem_engine {
254 void *priv;
255
256 int (*init)(struct drm_device *dev);
257 void (*takedown)(struct drm_device *dev);
258 int (*suspend)(struct drm_device *dev);
259 void (*resume)(struct drm_device *dev);
260
261 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
262 uint32_t *size);
263 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
264 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
265 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 266 void (*flush)(struct drm_device *);
6ee73861
BS		 267};
268
269struct nouveau_mc_engine {
270 int (*init)(struct drm_device *dev);
271 void (*takedown)(struct drm_device *dev);
272};
273
274struct nouveau_timer_engine {
275 int (*init)(struct drm_device *dev);
276 void (*takedown)(struct drm_device *dev);
277 uint64_t (*read)(struct drm_device *dev);
278};
279
280struct nouveau_fb_engine {
cb00f7c1
FJ		 281 int num_tiles;
282
6ee73861
BS		 283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 285
286 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
287 uint32_t size, uint32_t pitch);
6ee73861
BS		 288};
289
290struct nouveau_fifo_engine {
6ee73861
BS		 291 int channels;
292
a8eaebc6 293 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 294 int cur_playlist;
295
6ee73861
BS		 296 int (*init)(struct drm_device *);
297 void (*takedown)(struct drm_device *);
298
299 void (*disable)(struct drm_device *);
300 void (*enable)(struct drm_device *);
301 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 302 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 303
304 int (*channel_id)(struct drm_device *);
305
306 int (*create_context)(struct nouveau_channel *);
307 void (*destroy_context)(struct nouveau_channel *);
308 int (*load_context)(struct nouveau_channel *);
309 int (*unload_context)(struct drm_device *);
56ac7475 310 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 311};
312
313struct nouveau_pgraph_object_method {
314 int id;
315 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
316 uint32_t data);
317};
318
319struct nouveau_pgraph_object_class {
320 int id;
321 bool software;
322 struct nouveau_pgraph_object_method *methods;
323};
324
325struct nouveau_pgraph_engine {
326 struct nouveau_pgraph_object_class *grclass;
327 bool accel_blocked;
054b93e4 328 int grctx_size;
6ee73861 329
c50a5681 330 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 331 struct nouveau_gpuobj *ctx_table;
c50a5681 332
6ee73861
BS		 333 int (*init)(struct drm_device *);
334 void (*takedown)(struct drm_device *);
335
336 void (*fifo_access)(struct drm_device *, bool);
337
338 struct nouveau_channel *(*channel)(struct drm_device *);
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
56ac7475 343 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1
FJ		 344
345 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
346 uint32_t size, uint32_t pitch);
6ee73861
BS		 347};
348
c88c2e06
FJ		 349struct nouveau_display_engine {
350 int (*early_init)(struct drm_device *);
351 void (*late_takedown)(struct drm_device *);
352 int (*create)(struct drm_device *);
353 int (*init)(struct drm_device *);
354 void (*destroy)(struct drm_device *);
355};
356
ee2e0131
BS		 357struct nouveau_gpio_engine {
358 int (*init)(struct drm_device *);
359 void (*takedown)(struct drm_device *);
360
361 int (*get)(struct drm_device *, enum dcb_gpio_tag);
362 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
363
364 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
365};
366
330c5988
BS		 367struct nouveau_pm_voltage_level {
368 u8 voltage;
369 u8 vid;
370};
371
372struct nouveau_pm_voltage {
373 bool supported;
374 u8 vid_mask;
375
376 struct nouveau_pm_voltage_level *level;
377 int nr_level;
378};
379
380#define NOUVEAU_PM_MAX_LEVEL 8
381struct nouveau_pm_level {
382 struct device_attribute dev_attr;
383 char name[32];
384 int id;
385
386 u32 core;
387 u32 memory;
388 u32 shader;
389 u32 unk05;
390
391 u8 voltage;
392 u8 fanspeed;
aee582de
BS		 393
394 u16 memscript;
330c5988
BS		 395};
396
34e9d85a
MP		 397struct nouveau_pm_temp_sensor_constants {
398 u16 offset_constant;
399 s16 offset_mult;
400 u16 offset_div;
401 u16 slope_mult;
402 u16 slope_div;
403};
404
405struct nouveau_pm_threshold_temp {
406 s16 critical;
407 s16 down_clock;
408 s16 fan_boost;
409};
410
7760fcb0
RS		 411struct nouveau_pm_memtiming {
412 u32 reg_100220;
413 u32 reg_100224;
414 u32 reg_100228;
415 u32 reg_10022c;
416 u32 reg_100230;
417 u32 reg_100234;
418 u32 reg_100238;
419 u32 reg_10023c;
420};
421
422struct nouveau_pm_memtimings {
423 bool supported;
424 struct nouveau_pm_memtiming *timing;
425 int nr_timing;
426};
427
330c5988
BS		 428struct nouveau_pm_engine {
429 struct nouveau_pm_voltage voltage;
430 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
431 int nr_perflvl;
7760fcb0 432 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 433 struct nouveau_pm_temp_sensor_constants sensor_constants;
434 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 435
436 struct nouveau_pm_level boot;
437 struct nouveau_pm_level *cur;
438
8155cac4
FJ		 439 struct device *hwmon;
440
330c5988 441 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 442 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
443 u32 id, int khz);
330c5988
BS		 444 void (*clock_set)(struct drm_device *, void *);
445 int (*voltage_get)(struct drm_device *);
446 int (*voltage_set)(struct drm_device *, int voltage);
447 int (*fanspeed_get)(struct drm_device *);
448 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 449 int (*temp_get)(struct drm_device *);
330c5988
BS		 450};
451
6ee73861
BS		 452struct nouveau_engine {
453 struct nouveau_instmem_engine instmem;
454 struct nouveau_mc_engine mc;
455 struct nouveau_timer_engine timer;
456 struct nouveau_fb_engine fb;
457 struct nouveau_pgraph_engine graph;
458 struct nouveau_fifo_engine fifo;
c88c2e06 459 struct nouveau_display_engine display;
ee2e0131 460 struct nouveau_gpio_engine gpio;
330c5988 461 struct nouveau_pm_engine pm;
6ee73861
BS		 462};
463
464struct nouveau_pll_vals {
465 union {
466 struct {
467#ifdef __BIG_ENDIAN
468 uint8_t N1, M1, N2, M2;
469#else
470 uint8_t M1, N1, M2, N2;
471#endif
472 };
473 struct {
474 uint16_t NM1, NM2;
475 } __attribute__((packed));
476 };
477 int log2P;
478
479 int refclk;
480};
481
482enum nv04_fp_display_regs {
483 FP_DISPLAY_END,
484 FP_TOTAL,
485 FP_CRTC,
486 FP_SYNC_START,
487 FP_SYNC_END,
488 FP_VALID_START,
489 FP_VALID_END
490};
491
492struct nv04_crtc_reg {
cbab95db 493 unsigned char MiscOutReg;
4a9f822f 494 uint8_t CRTC[0xa0];
6ee73861
BS		 495 uint8_t CR58[0x10];
496 uint8_t Sequencer[5];
497 uint8_t Graphics[9];
498 uint8_t Attribute[21];
cbab95db 499 unsigned char DAC[768];
6ee73861
BS		 500
501 /* PCRTC regs */
502 uint32_t fb_start;
503 uint32_t crtc_cfg;
504 uint32_t cursor_cfg;
505 uint32_t gpio_ext;
506 uint32_t crtc_830;
507 uint32_t crtc_834;
508 uint32_t crtc_850;
509 uint32_t crtc_eng_ctrl;
510
511 /* PRAMDAC regs */
512 uint32_t nv10_cursync;
513 struct nouveau_pll_vals pllvals;
514 uint32_t ramdac_gen_ctrl;
515 uint32_t ramdac_630;
516 uint32_t ramdac_634;
517 uint32_t tv_setup;
518 uint32_t tv_vtotal;
519 uint32_t tv_vskew;
520 uint32_t tv_vsync_delay;
521 uint32_t tv_htotal;
522 uint32_t tv_hskew;
523 uint32_t tv_hsync_delay;
524 uint32_t tv_hsync_delay2;
525 uint32_t fp_horiz_regs[7];
526 uint32_t fp_vert_regs[7];
527 uint32_t dither;
528 uint32_t fp_control;
529 uint32_t dither_regs[6];
530 uint32_t fp_debug_0;
531 uint32_t fp_debug_1;
532 uint32_t fp_debug_2;
533 uint32_t fp_margin_color;
534 uint32_t ramdac_8c0;
535 uint32_t ramdac_a20;
536 uint32_t ramdac_a24;
537 uint32_t ramdac_a34;
538 uint32_t ctv_regs[38];
539};
540
541struct nv04_output_reg {
542 uint32_t output;
543 int head;
544};
545
546struct nv04_mode_state {
cbab95db 547 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 548 uint32_t pllsel;
549 uint32_t sel_clk;
6ee73861
BS		 550};
551
552enum nouveau_card_type {
553 NV_04 = 0x00,
554 NV_10 = 0x10,
555 NV_20 = 0x20,
556 NV_30 = 0x30,
557 NV_40 = 0x40,
558 NV_50 = 0x50,
4b223eef 559 NV_C0 = 0xc0,
6ee73861
BS		 560};
561
562struct drm_nouveau_private {
563 struct drm_device *dev;
6ee73861
BS		 564
565 /* the card type, takes NV_* as values */
566 enum nouveau_card_type card_type;
567 /* exact chipset, derived from NV_PMC_BOOT_0 */
568 int chipset;
569 int flags;
570
571 void __iomem *mmio;
5125bfd8 572
e05d7eae 573 spinlock_t ramin_lock;
6ee73861 574 void __iomem *ramin;
5125bfd8
BS		 575 u32 ramin_size;
576 u32 ramin_base;
577 bool ramin_available;
e05d7eae
BS		 578 struct drm_mm ramin_heap;
579 struct list_head gpuobj_list;
6ee73861 580
ac8fb975
BS		 581 struct nouveau_bo *vga_ram;
582
6ee73861
BS		 583 struct workqueue_struct *wq;
584 struct work_struct irq_work;
a5acac66 585 struct work_struct hpd_work;
6ee73861
BS		 586
587 struct list_head vbl_waiting;
588
589 struct {
ba4420c2 590 struct drm_global_reference mem_global_ref;
6ee73861
BS		 591 struct ttm_bo_global_ref bo_global_ref;
592 struct ttm_bo_device bdev;
6ee73861
BS		 593 atomic_t validate_sequence;
594 } ttm;
595
0c6c1c2f
FJ		 596 struct {
597 spinlock_t lock;
598 struct drm_mm heap;
599 struct nouveau_bo *bo;
600 } fence;
601
6ee73861
BS		 602 int fifo_alloc_count;
603 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
604
605 struct nouveau_engine engine;
606 struct nouveau_channel *channel;
607
ff9e5279
MM		 608 /* For PFIFO and PGRAPH. */
609 spinlock_t context_switch_lock;
610
6ee73861 611 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 612 struct nouveau_ramht *ramht;
613 struct nouveau_gpuobj *ramfc;
614 struct nouveau_gpuobj *ramro;
615
6ee73861 616 uint32_t ramin_rsvd_vram;
6ee73861 617
6ee73861
BS		 618 struct {
619 enum {
620 NOUVEAU_GART_NONE = 0,
621 NOUVEAU_GART_AGP,
622 NOUVEAU_GART_SGDMA
623 } type;
624 uint64_t aper_base;
625 uint64_t aper_size;
626 uint64_t aper_free;
627
628 struct nouveau_gpuobj *sg_ctxdma;
629 struct page *sg_dummy_page;
630 dma_addr_t sg_dummy_bus;
6ee73861
BS		 631 } gart_info;
632
a0af9add 633 /* nv10-nv40 tiling regions */
9f56b126 634 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 635
a76fb4e8
BS		 636 /* VRAM/fb configuration */
637 uint64_t vram_size;
638 uint64_t vram_sys_base;
6c3d7ef2 639 u32 vram_rblock_size;
a76fb4e8
BS		 640
641 uint64_t fb_phys;
642 uint64_t fb_available_size;
643 uint64_t fb_mappable_pages;
644 uint64_t fb_aper_free;
645 int fb_mtrr;
646
6ee73861
BS		 647 /* G8x/G9x virtual address space */
648 uint64_t vm_gart_base;
649 uint64_t vm_gart_size;
650 uint64_t vm_vram_base;
651 uint64_t vm_vram_size;
652 uint64_t vm_end;
653 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
654 int vm_vram_pt_nr;
6ee73861 655
04a39c57 656 struct nvbios vbios;
6ee73861
BS		 657
658 struct nv04_mode_state mode_reg;
659 struct nv04_mode_state saved_reg;
660 uint32_t saved_vga_font[4][16384];
661 uint32_t crtc_owner;
662 uint32_t dac_users[4];
663
664 struct nouveau_suspend_resume {
6ee73861 665 uint32_t *ramin_copy;
6ee73861
BS		 666 } susres;
667
668 struct backlight_device *backlight;
6ee73861
BS		 669
670 struct nouveau_channel *evo;
87c0e0e5
BS		 671 struct {
672 struct dcb_entry *dcb;
673 u16 script;
674 u32 pclk;
675 } evo_irq;
6ee73861
BS		 676
677 struct {
678 struct dentry *channel_root;
679 } debugfs;
38651674 680
8be48d92 681 struct nouveau_fbdev *nfbdev;
06415c56 682 struct apertures_struct *apertures;
6ee73861
BS		 683};
684
2730723b
FJ		 685static inline struct drm_nouveau_private *
686nouveau_private(struct drm_device *dev)
687{
688 return dev->dev_private;
689}
690
6ee73861
BS		 691static inline struct drm_nouveau_private *
692nouveau_bdev(struct ttm_bo_device *bd)
693{
694 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
695}
696
697static inline int
698nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
699{
700 struct nouveau_bo *prev;
701
702 if (!pnvbo)
703 return -EINVAL;
704 prev = *pnvbo;
705
706 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
707 if (prev) {
708 struct ttm_buffer_object *bo = &prev->bo;
709
710 ttm_bo_unref(&bo);
711 }
712
713 return 0;
714}
715
6ee73861
BS		 716#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
717 struct drm_nouveau_private *nv = dev->dev_private; \
718 if (!nouveau_channel_owner(dev, (cl), (id))) { \
719 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
720 DRM_CURRENTPID, (id)); \
721 return -EPERM; \
722 } \
723 (ch) = nv->fifos[(id)]; \
724} while (0)
725
726/* nouveau_drv.c */
de5899bd 727extern int nouveau_agpmode;
6ee73861
BS		 728extern int nouveau_duallink;
729extern int nouveau_uscript_lvds;
730extern int nouveau_uscript_tmds;
731extern int nouveau_vram_pushbuf;
732extern int nouveau_vram_notify;
733extern int nouveau_fbpercrtc;
f4053509 734extern int nouveau_tv_disable;
6ee73861
BS		 735extern char *nouveau_tv_norm;
736extern int nouveau_reg_debug;
737extern char *nouveau_vbios;
a1470890 738extern int nouveau_ignorelid;
a32ed69d
MK		 739extern int nouveau_nofbaccel;
740extern int nouveau_noaccel;
0cba1b76 741extern int nouveau_force_post;
da647d5b 742extern int nouveau_override_conntype;
6f876986
BS		 743extern char *nouveau_perflvl;
744extern int nouveau_perflvl_wr;
6ee73861 745
6a9ee8af
DA		 746extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
747extern int nouveau_pci_resume(struct pci_dev *pdev);
748
6ee73861
BS		 749/* nouveau_state.c */
750extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
751extern int nouveau_load(struct drm_device *, unsigned long flags);
752extern int nouveau_firstopen(struct drm_device *);
753extern void nouveau_lastclose(struct drm_device *);
754extern int nouveau_unload(struct drm_device *);
755extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
756 struct drm_file *);
757extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
758 struct drm_file *);
759extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
760 uint32_t reg, uint32_t mask, uint32_t val);
761extern bool nouveau_wait_for_idle(struct drm_device *);
762extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 763
764/* nouveau_mem.c */
fbd2895e
BS		 765extern int nouveau_mem_vram_init(struct drm_device *);
766extern void nouveau_mem_vram_fini(struct drm_device *);
767extern int nouveau_mem_gart_init(struct drm_device *);
768extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 769extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 770extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 771extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 772extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
773 uint32_t addr,
774 uint32_t size,
775 uint32_t pitch);
776extern void nv10_mem_expire_tiling(struct drm_device *dev,
777 struct nouveau_tile_reg *tile,
778 struct nouveau_fence *fence);
6ee73861
BS		 779extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
780 uint32_t size, uint32_t flags,
781 uint64_t phys);
782extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
783 uint32_t size);
784
785/* nouveau_notifier.c */
786extern int nouveau_notifier_init_channel(struct nouveau_channel *);
787extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
788extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
789 int cout, uint32_t *offset);
790extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
791extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
792 struct drm_file *);
793extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
794 struct drm_file *);
795
796/* nouveau_channel.c */
797extern struct drm_ioctl_desc nouveau_ioctls[];
798extern int nouveau_max_ioctl;
799extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
800extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
801 int channel);
802extern int nouveau_channel_alloc(struct drm_device *dev,
803 struct nouveau_channel **chan,
804 struct drm_file *file_priv,
805 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
806extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 807
808/* nouveau_object.c */
809extern int nouveau_gpuobj_early_init(struct drm_device *);
810extern int nouveau_gpuobj_init(struct drm_device *);
811extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 812extern int nouveau_gpuobj_suspend(struct drm_device *dev);
813extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
814extern void nouveau_gpuobj_resume(struct drm_device *dev);
815extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
816 uint32_t vram_h, uint32_t tt_h);
817extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
818extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
819 uint32_t size, int align, uint32_t flags,
820 struct nouveau_gpuobj **);
a8eaebc6
BS		 821extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
822 struct nouveau_gpuobj **);
43efc9ce
BS		 823extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
824 u32 size, u32 flags,
a8eaebc6 825 struct nouveau_gpuobj **);
6ee73861
BS		 826extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
827 uint64_t offset, uint64_t size, int access,
828 int target, struct nouveau_gpuobj **);
829extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
830 uint64_t offset, uint64_t size,
831 int access, struct nouveau_gpuobj **,
832 uint32_t *o_ret);
833extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
834 struct nouveau_gpuobj **);
f03a314b
FJ		 835extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
836 struct nouveau_gpuobj **);
6ee73861
BS		 837extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
838 struct drm_file *);
839extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
840 struct drm_file *);
841
842/* nouveau_irq.c */
843extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
844extern void nouveau_irq_preinstall(struct drm_device *);
845extern int nouveau_irq_postinstall(struct drm_device *);
846extern void nouveau_irq_uninstall(struct drm_device *);
847
848/* nouveau_sgdma.c */
849extern int nouveau_sgdma_init(struct drm_device *);
850extern void nouveau_sgdma_takedown(struct drm_device *);
851extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
852 uint32_t *page);
853extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
854
855/* nouveau_debugfs.c */
856#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
857extern int nouveau_debugfs_init(struct drm_minor *);
858extern void nouveau_debugfs_takedown(struct drm_minor *);
859extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
860extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
861#else
862static inline int
863nouveau_debugfs_init(struct drm_minor *minor)
864{
865 return 0;
866}
867
868static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
869{
870}
871
872static inline int
873nouveau_debugfs_channel_init(struct nouveau_channel *chan)
874{
875 return 0;
876}
877
878static inline void
879nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
880{
881}
882#endif
883
884/* nouveau_dma.c */
75c99da6 885extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 886extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 887extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 888
889/* nouveau_acpi.c */
afeb3e11 890#define ROM_BIOS_PAGE 4096
2f41a7f1 891#if defined(CONFIG_ACPI)
6a9ee8af
DA		 892void nouveau_register_dsm_handler(void);
893void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 894int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
895bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 896int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 897#else
898static inline void nouveau_register_dsm_handler(void) {}
899static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 900static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
901static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 902static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 903#endif
6ee73861
BS		 904
905/* nouveau_backlight.c */
906#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
907extern int nouveau_backlight_init(struct drm_device *);
908extern void nouveau_backlight_exit(struct drm_device *);
909#else
910static inline int nouveau_backlight_init(struct drm_device *dev)
911{
912 return 0;
913}
914
915static inline void nouveau_backlight_exit(struct drm_device *dev) { }
916#endif
917
918/* nouveau_bios.c */
919extern int nouveau_bios_init(struct drm_device *);
920extern void nouveau_bios_takedown(struct drm_device *dev);
921extern int nouveau_run_vbios_init(struct drm_device *);
922extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
923 struct dcb_entry *);
924extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
925 enum dcb_gpio_tag);
926extern struct dcb_connector_table_entry *
927nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 928extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 929extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
930 struct pll_lims *);
931extern int nouveau_bios_run_display_table(struct drm_device *,
932 struct dcb_entry *,
933 uint32_t script, int pxclk);
934extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
935 int *length);
936extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
937extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
938extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
939 bool *dl, bool *if_is_24bit);
940extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
941 int head, int pxclk);
942extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
943 enum LVDS_script, int pxclk);
944
945/* nouveau_ttm.c */
946int nouveau_ttm_global_init(struct drm_nouveau_private *);
947void nouveau_ttm_global_release(struct drm_nouveau_private *);
948int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
949
950/* nouveau_dp.c */
951int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
952 uint8_t *data, int data_nr);
953bool nouveau_dp_detect(struct drm_encoder *);
954bool nouveau_dp_link_train(struct drm_encoder *);
955
956/* nv04_fb.c */
957extern int nv04_fb_init(struct drm_device *);
958extern void nv04_fb_takedown(struct drm_device *);
959
960/* nv10_fb.c */
961extern int nv10_fb_init(struct drm_device *);
962extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 963extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
964 uint32_t, uint32_t);
6ee73861 965
8bded189
FJ		 966/* nv30_fb.c */
967extern int nv30_fb_init(struct drm_device *);
968extern void nv30_fb_takedown(struct drm_device *);
969
6ee73861
BS		 970/* nv40_fb.c */
971extern int nv40_fb_init(struct drm_device *);
972extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 973extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
974 uint32_t, uint32_t);
304424e1
MK		 975/* nv50_fb.c */
976extern int nv50_fb_init(struct drm_device *);
977extern void nv50_fb_takedown(struct drm_device *);
d96773e7 978extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 979
4b223eef
BS		 980/* nvc0_fb.c */
981extern int nvc0_fb_init(struct drm_device *);
982extern void nvc0_fb_takedown(struct drm_device *);
983
6ee73861
BS		 984/* nv04_fifo.c */
985extern int nv04_fifo_init(struct drm_device *);
986extern void nv04_fifo_disable(struct drm_device *);
987extern void nv04_fifo_enable(struct drm_device *);
988extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 989extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 990extern int nv04_fifo_channel_id(struct drm_device *);
991extern int nv04_fifo_create_context(struct nouveau_channel *);
992extern void nv04_fifo_destroy_context(struct nouveau_channel *);
993extern int nv04_fifo_load_context(struct nouveau_channel *);
994extern int nv04_fifo_unload_context(struct drm_device *);
995
996/* nv10_fifo.c */
997extern int nv10_fifo_init(struct drm_device *);
998extern int nv10_fifo_channel_id(struct drm_device *);
999extern int nv10_fifo_create_context(struct nouveau_channel *);
1000extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1001extern int nv10_fifo_load_context(struct nouveau_channel *);
1002extern int nv10_fifo_unload_context(struct drm_device *);
1003
1004/* nv40_fifo.c */
1005extern int nv40_fifo_init(struct drm_device *);
1006extern int nv40_fifo_create_context(struct nouveau_channel *);
1007extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1008extern int nv40_fifo_load_context(struct nouveau_channel *);
1009extern int nv40_fifo_unload_context(struct drm_device *);
1010
1011/* nv50_fifo.c */
1012extern int nv50_fifo_init(struct drm_device *);
1013extern void nv50_fifo_takedown(struct drm_device *);
1014extern int nv50_fifo_channel_id(struct drm_device *);
1015extern int nv50_fifo_create_context(struct nouveau_channel *);
1016extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1017extern int nv50_fifo_load_context(struct nouveau_channel *);
1018extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1019extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1020
4b223eef
BS		 1021/* nvc0_fifo.c */
1022extern int nvc0_fifo_init(struct drm_device *);
1023extern void nvc0_fifo_takedown(struct drm_device *);
1024extern void nvc0_fifo_disable(struct drm_device *);
1025extern void nvc0_fifo_enable(struct drm_device *);
1026extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1027extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1028extern int nvc0_fifo_channel_id(struct drm_device *);
1029extern int nvc0_fifo_create_context(struct nouveau_channel *);
1030extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1031extern int nvc0_fifo_load_context(struct nouveau_channel *);
1032extern int nvc0_fifo_unload_context(struct drm_device *);
1033
6ee73861
BS		 1034/* nv04_graph.c */
1035extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1036extern int nv04_graph_init(struct drm_device *);
1037extern void nv04_graph_takedown(struct drm_device *);
1038extern void nv04_graph_fifo_access(struct drm_device *, bool);
1039extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1040extern int nv04_graph_create_context(struct nouveau_channel *);
1041extern void nv04_graph_destroy_context(struct nouveau_channel *);
1042extern int nv04_graph_load_context(struct nouveau_channel *);
1043extern int nv04_graph_unload_context(struct drm_device *);
1044extern void nv04_graph_context_switch(struct drm_device *);
1045
1046/* nv10_graph.c */
1047extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1048extern int nv10_graph_init(struct drm_device *);
1049extern void nv10_graph_takedown(struct drm_device *);
1050extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1051extern int nv10_graph_create_context(struct nouveau_channel *);
1052extern void nv10_graph_destroy_context(struct nouveau_channel *);
1053extern int nv10_graph_load_context(struct nouveau_channel *);
1054extern int nv10_graph_unload_context(struct drm_device *);
1055extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1056extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1057 uint32_t, uint32_t);
6ee73861
BS		 1058
1059/* nv20_graph.c */
1060extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1061extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1062extern int nv20_graph_create_context(struct nouveau_channel *);
1063extern void nv20_graph_destroy_context(struct nouveau_channel *);
1064extern int nv20_graph_load_context(struct nouveau_channel *);
1065extern int nv20_graph_unload_context(struct drm_device *);
1066extern int nv20_graph_init(struct drm_device *);
1067extern void nv20_graph_takedown(struct drm_device *);
1068extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1069extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1070 uint32_t, uint32_t);
6ee73861
BS		 1071
1072/* nv40_graph.c */
1073extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1074extern int nv40_graph_init(struct drm_device *);
1075extern void nv40_graph_takedown(struct drm_device *);
1076extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1077extern int nv40_graph_create_context(struct nouveau_channel *);
1078extern void nv40_graph_destroy_context(struct nouveau_channel *);
1079extern int nv40_graph_load_context(struct nouveau_channel *);
1080extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1081extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1082extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1083 uint32_t, uint32_t);
6ee73861
BS		 1084
1085/* nv50_graph.c */
1086extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1087extern int nv50_graph_init(struct drm_device *);
1088extern void nv50_graph_takedown(struct drm_device *);
1089extern void nv50_graph_fifo_access(struct drm_device *, bool);
1090extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1091extern int nv50_graph_create_context(struct nouveau_channel *);
1092extern void nv50_graph_destroy_context(struct nouveau_channel *);
1093extern int nv50_graph_load_context(struct nouveau_channel *);
1094extern int nv50_graph_unload_context(struct drm_device *);
1095extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1096extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1097extern void nv50_graph_tlb_flush(struct drm_device *dev);
1098extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1099
4b223eef
BS		 1100/* nvc0_graph.c */
1101extern int nvc0_graph_init(struct drm_device *);
1102extern void nvc0_graph_takedown(struct drm_device *);
1103extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1104extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1105extern int nvc0_graph_create_context(struct nouveau_channel *);
1106extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1107extern int nvc0_graph_load_context(struct nouveau_channel *);
1108extern int nvc0_graph_unload_context(struct drm_device *);
1109
6ee73861
BS		 1110/* nv04_instmem.c */
1111extern int nv04_instmem_init(struct drm_device *);
1112extern void nv04_instmem_takedown(struct drm_device *);
1113extern int nv04_instmem_suspend(struct drm_device *);
1114extern void nv04_instmem_resume(struct drm_device *);
1115extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1116 uint32_t *size);
1117extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1118extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1119extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1120extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1121
1122/* nv50_instmem.c */
1123extern int nv50_instmem_init(struct drm_device *);
1124extern void nv50_instmem_takedown(struct drm_device *);
1125extern int nv50_instmem_suspend(struct drm_device *);
1126extern void nv50_instmem_resume(struct drm_device *);
1127extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1128 uint32_t *size);
1129extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1130extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1131extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1132extern void nv50_instmem_flush(struct drm_device *);
734ee835 1133extern void nv84_instmem_flush(struct drm_device *);
63187215 1134extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1135
4b223eef
BS		 1136/* nvc0_instmem.c */
1137extern int nvc0_instmem_init(struct drm_device *);
1138extern void nvc0_instmem_takedown(struct drm_device *);
1139extern int nvc0_instmem_suspend(struct drm_device *);
1140extern void nvc0_instmem_resume(struct drm_device *);
1141extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1142 uint32_t *size);
1143extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1144extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1145extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1146extern void nvc0_instmem_flush(struct drm_device *);
1147
6ee73861
BS		 1148/* nv04_mc.c */
1149extern int nv04_mc_init(struct drm_device *);
1150extern void nv04_mc_takedown(struct drm_device *);
1151
1152/* nv40_mc.c */
1153extern int nv40_mc_init(struct drm_device *);
1154extern void nv40_mc_takedown(struct drm_device *);
1155
1156/* nv50_mc.c */
1157extern int nv50_mc_init(struct drm_device *);
1158extern void nv50_mc_takedown(struct drm_device *);
1159
1160/* nv04_timer.c */
1161extern int nv04_timer_init(struct drm_device *);
1162extern uint64_t nv04_timer_read(struct drm_device *);
1163extern void nv04_timer_takedown(struct drm_device *);
1164
1165extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1166 unsigned long arg);
1167
1168/* nv04_dac.c */
8f1a6086 1169extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1170extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1171extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1172extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1173extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1174
1175/* nv04_dfp.c */
8f1a6086 1176extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1177extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1178extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1179 int head, bool dl);
1180extern void nv04_dfp_disable(struct drm_device *dev, int head);
1181extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1182
1183/* nv04_tv.c */
1184extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1185extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1186
1187/* nv17_tv.c */
8f1a6086 1188extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1189
1190/* nv04_display.c */
c88c2e06
FJ		 1191extern int nv04_display_early_init(struct drm_device *);
1192extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1193extern int nv04_display_create(struct drm_device *);
c88c2e06 1194extern int nv04_display_init(struct drm_device *);
6ee73861 1195extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1196
1197/* nv04_crtc.c */
1198extern int nv04_crtc_create(struct drm_device *, int index);
1199
1200/* nouveau_bo.c */
1201extern struct ttm_bo_driver nouveau_bo_driver;
1202extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1203 int size, int align, uint32_t flags,
1204 uint32_t tile_mode, uint32_t tile_flags,
1205 bool no_vm, bool mappable, struct nouveau_bo **);
1206extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1207extern int nouveau_bo_unpin(struct nouveau_bo *);
1208extern int nouveau_bo_map(struct nouveau_bo *);
1209extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1210extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1211 uint32_t busy);
6ee73861
BS		 1212extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1213extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1214extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1215extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1216
1217/* nouveau_fence.c */
1218struct nouveau_fence;
0c6c1c2f
FJ		 1219extern int nouveau_fence_init(struct drm_device *);
1220extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1221extern int nouveau_fence_channel_init(struct nouveau_channel *);
1222extern void nouveau_fence_channel_fini(struct nouveau_channel *);
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BS		 1223extern void nouveau_fence_update(struct nouveau_channel *);
1224extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1225 bool emit);
1226extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1227extern void nouveau_fence_work(struct nouveau_fence *fence,
1228 void (*work)(void *priv, bool signalled),
1229 void *priv);
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BS		 1230struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1231extern bool nouveau_fence_signalled(void *obj, void *arg);
1232extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
2730723b 1233extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
6ee73861
BS		 1234extern int nouveau_fence_flush(void *obj, void *arg);
1235extern void nouveau_fence_unref(void **obj);
1236extern void *nouveau_fence_ref(void *obj);
6ee73861
BS		 1237
1238/* nouveau_gem.c */
1239extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1240 int size, int align, uint32_t flags,
1241 uint32_t tile_mode, uint32_t tile_flags,
1242 bool no_vm, bool mappable, struct nouveau_bo **);
1243extern int nouveau_gem_object_new(struct drm_gem_object *);
1244extern void nouveau_gem_object_del(struct drm_gem_object *);
1245extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1246 struct drm_file *);
1247extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1248 struct drm_file *);
6ee73861
BS		 1249extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1250 struct drm_file *);
1251extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1252 struct drm_file *);
1253extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1254 struct drm_file *);
1255
ee2e0131
BS		 1256/* nv10_gpio.c */
1257int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1258int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1259
45284162 1260/* nv50_gpio.c */
ee2e0131 1261int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1262int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1263int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1264void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1265
e9ebb68b
BS		 1266/* nv50_calc. */
1267int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1268 int *N1, int *M1, int *N2, int *M2, int *P);
1269int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1270 int clk, int *N, int *fN, int *M, int *P);
1271
6ee73861
BS		 1272#ifndef ioread32_native
1273#ifdef __BIG_ENDIAN
1274#define ioread16_native ioread16be
1275#define iowrite16_native iowrite16be
1276#define ioread32_native ioread32be
1277#define iowrite32_native iowrite32be
1278#else /* def __BIG_ENDIAN */
1279#define ioread16_native ioread16
1280#define iowrite16_native iowrite16
1281#define ioread32_native ioread32
1282#define iowrite32_native iowrite32
1283#endif /* def __BIG_ENDIAN else */
1284#endif /* !ioread32_native */
1285
1286/* channel control reg access */
1287static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1288{
1289 return ioread32_native(chan->user + reg);
1290}
1291
1292static inline void nvchan_wr32(struct nouveau_channel *chan,
1293 unsigned reg, u32 val)
1294{
1295 iowrite32_native(val, chan->user + reg);
1296}
1297
1298/* register access */
1299static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1300{
1301 struct drm_nouveau_private *dev_priv = dev->dev_private;
1302 return ioread32_native(dev_priv->mmio + reg);
1303}
1304
1305static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1306{
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 iowrite32_native(val, dev_priv->mmio + reg);
1309}
1310
2a7fdb2b 1311static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1312{
1313 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1314 nv_wr32(dev, reg, (tmp & ~mask) | val);
1315 return tmp;
49eed80a
BS		 1316}
1317
6ee73861
BS		 1318static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1319{
1320 struct drm_nouveau_private *dev_priv = dev->dev_private;
1321 return ioread8(dev_priv->mmio + reg);
1322}
1323
1324static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1325{
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 iowrite8(val, dev_priv->mmio + reg);
1328}
1329
4b5c152a 1330#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1331 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1332
1333/* PRAMIN access */
1334static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1335{
1336 struct drm_nouveau_private *dev_priv = dev->dev_private;
1337 return ioread32_native(dev_priv->ramin + offset);
1338}
1339
1340static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1341{
1342 struct drm_nouveau_private *dev_priv = dev->dev_private;
1343 iowrite32_native(val, dev_priv->ramin + offset);
1344}
1345
1346/* object access */
b3beb167
BS		 1347extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1348extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1349
1350/*
1351 * Logging
1352 * Argument d is (struct drm_device *).
1353 */
1354#define NV_PRINTK(level, d, fmt, arg...) \
1355 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1356 pci_name(d->pdev), ##arg)
1357#ifndef NV_DEBUG_NOTRACE
1358#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1359 if (drm_debug & DRM_UT_DRIVER) { \
1360 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1361 __LINE__, ##arg); \
1362 } \
1363} while (0)
1364#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1365 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1366 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1367 __LINE__, ##arg); \
1368 } \
1369} while (0)
1370#else
1371#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1372 if (drm_debug & DRM_UT_DRIVER) \
1373 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1374} while (0)
1375#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1376 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1377 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1378} while (0)
1379#endif
1380#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1381#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1382#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1383#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1384#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1385
1386/* nouveau_reg_debug bitmask */
1387enum {
1388 NOUVEAU_REG_DEBUG_MC = 0x1,
1389 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1390 NOUVEAU_REG_DEBUG_FB = 0x4,
1391 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1392 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1393 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1394 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1395 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1396 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1397 NOUVEAU_REG_DEBUG_EVO = 0x200,
1398};
1399
1400#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1401 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1402 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1403} while (0)
1404
1405static inline bool
1406nv_two_heads(struct drm_device *dev)
1407{
1408 struct drm_nouveau_private *dev_priv = dev->dev_private;
1409 const int impl = dev->pci_device & 0x0ff0;
1410
1411 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1412 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1413 return true;
1414
1415 return false;
1416}
1417
1418static inline bool
1419nv_gf4_disp_arch(struct drm_device *dev)
1420{
1421 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1422}
1423
1424static inline bool
1425nv_two_reg_pll(struct drm_device *dev)
1426{
1427 struct drm_nouveau_private *dev_priv = dev->dev_private;
1428 const int impl = dev->pci_device & 0x0ff0;
1429
1430 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1431 return true;
1432 return false;
1433}
1434
acae116c
FJ		 1435static inline bool
1436nv_match_device(struct drm_device *dev, unsigned device,
1437 unsigned sub_vendor, unsigned sub_device)
1438{
1439 return dev->pdev->device == device &&
1440 dev->pdev->subsystem_vendor == sub_vendor &&
1441 dev->pdev->subsystem_device == sub_device;
1442}
1443
f03a314b
FJ		 1444#define NV_SW 0x0000506e
1445#define NV_SW_DMA_SEMAPHORE 0x00000060
1446#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1447#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1448#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1449#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1450#define NV_SW_DMA_VBLSEM 0x0000018c
1451#define NV_SW_VBLSEM_OFFSET 0x00000400
1452#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1453#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1454
1455#endif /* __NOUVEAU_DRV_H__ */
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