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drm/nv04-nv40: unregister irq handler on destroy
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
274fec93 57#include "nouveau_util.h"
054b93e4 58struct nouveau_grctx;
6ee73861
BS		 59
60#define MAX_NUM_DCB_ENTRIES 16
61
62#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 63#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 64
65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
66#define NV50_VM_BLOCK (512*1024*1024ULL)
67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68
a0af9add 69struct nouveau_tile_reg {
a0af9add 70 bool used;
a5cf68b0
FJ		 71 uint32_t addr;
72 uint32_t limit;
73 uint32_t pitch;
87a326a3
FJ		 74 uint32_t zcomp;
75 struct drm_mm_node *tag_mem;
a5cf68b0 76 struct nouveau_fence *fence;
a0af9add
FJ		 77};
78
6ee73861
BS		 79struct nouveau_bo {
80 struct ttm_buffer_object bo;
81 struct ttm_placement placement;
82 u32 placements[3];
78ad0f7b 83 u32 busy_placements[3];
6ee73861
BS		 84 struct ttm_bo_kmap_obj kmap;
85 struct list_head head;
86
87 /* protected by ttm_bo_reserve() */
88 struct drm_file *reserved_by;
89 struct list_head entry;
90 int pbbo_index;
a1606a95 91 bool validate_mapped;
6ee73861
BS		 92
93 struct nouveau_channel *channel;
94
95 bool mappable;
96 bool no_vm;
97
98 uint32_t tile_mode;
99 uint32_t tile_flags;
a0af9add 100 struct nouveau_tile_reg *tile;
6ee73861
BS		 101
102 struct drm_gem_object *gem;
6ee73861
BS		 103 int pin_refcnt;
104};
105
f13b3263
FJ		 106#define nouveau_bo_tile_layout(nvbo) \
107 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
108
6ee73861
BS		 109static inline struct nouveau_bo *
110nouveau_bo(struct ttm_buffer_object *bo)
111{
112 return container_of(bo, struct nouveau_bo, bo);
113}
114
115static inline struct nouveau_bo *
116nouveau_gem_object(struct drm_gem_object *gem)
117{
118 return gem ? gem->driver_private : NULL;
119}
120
121/* TODO: submit equivalent to TTM generic API upstream? */
122static inline void __iomem *
123nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
124{
125 bool is_iomem;
126 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
127 &nvbo->kmap, &is_iomem);
128 WARN_ON_ONCE(ioptr && !is_iomem);
129 return ioptr;
130}
131
6ee73861
BS		 132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 139#define NVOBJ_ENGINE_PPP 2
140#define NVOBJ_ENGINE_COPY 3
141#define NVOBJ_ENGINE_VP 4
142#define NVOBJ_ENGINE_CRYPT 5
143#define NVOBJ_ENGINE_BSP 6
50536946 144#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 145#define NVOBJ_ENGINE_INT 0xdeadbeef
146
6ee73861
BS		 147#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
148#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 149struct nouveau_gpuobj {
b3beb167 150 struct drm_device *dev;
eb9bcbdc 151 struct kref refcount;
6ee73861
BS		 152 struct list_head list;
153
b833ac26 154 struct drm_mm_node *im_pramin;
6ee73861 155 struct nouveau_bo *im_backing;
6ee73861
BS		 156 uint32_t *im_backing_suspend;
157 int im_bound;
158
159 uint32_t flags;
6ee73861 160
43efc9ce 161 u32 size;
de3a6c0a
BS		 162 u32 pinst;
163 u32 cinst;
164 u64 vinst;
165
6ee73861
BS		 166 uint32_t engine;
167 uint32_t class;
168
169 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
170 void *priv;
171};
172
332b242f
FJ		 173struct nouveau_page_flip_state {
174 struct list_head head;
175 struct drm_pending_vblank_event *event;
176 int crtc, bpp, pitch, x, y;
177 uint64_t offset;
178};
179
e419cf09
FJ		 180enum nouveau_channel_mutex_class {
181 NOUVEAU_UCHANNEL_MUTEX,
182 NOUVEAU_KCHANNEL_MUTEX
183};
184
6ee73861
BS		 185struct nouveau_channel {
186 struct drm_device *dev;
187 int id;
188
f091a3d4
FJ		 189 /* references to the channel data structure */
190 struct kref ref;
191 /* users of the hardware channel resources, the hardware
192 * context will be kicked off when it reaches zero. */
193 atomic_t users;
6a6b73f2
BS		 194 struct mutex mutex;
195
6ee73861
BS		 196 /* owner of this fifo */
197 struct drm_file *file_priv;
198 /* mapping of the fifo itself */
199 struct drm_local_map *map;
200
201 /* mapping of the regs controling the fifo */
202 void __iomem *user;
203 uint32_t user_get;
204 uint32_t user_put;
205
206 /* Fencing */
207 struct {
208 /* lock protects the pending list only */
209 spinlock_t lock;
210 struct list_head pending;
211 uint32_t sequence;
212 uint32_t sequence_ack;
047d1d3c 213 atomic_t last_sequence_irq;
6ee73861
BS		 214 } fence;
215
216 /* DMA push buffer */
a8eaebc6
BS		 217 struct nouveau_gpuobj *pushbuf;
218 struct nouveau_bo *pushbuf_bo;
219 uint32_t pushbuf_base;
6ee73861
BS		 220
221 /* Notifier memory */
222 struct nouveau_bo *notifier_bo;
b833ac26 223 struct drm_mm notifier_heap;
6ee73861
BS		 224
225 /* PFIFO context */
a8eaebc6
BS		 226 struct nouveau_gpuobj *ramfc;
227 struct nouveau_gpuobj *cache;
6ee73861
BS		 228
229 /* PGRAPH context */
230 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 231 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 232 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 233 void *pgraph_ctx;
234
235 /* NV50 VM */
a8eaebc6
BS		 236 struct nouveau_gpuobj *vm_pd;
237 struct nouveau_gpuobj *vm_gart_pt;
238 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 239
240 /* Objects */
a8eaebc6
BS		 241 struct nouveau_gpuobj *ramin; /* Private instmem */
242 struct drm_mm ramin_heap; /* Private PRAMIN heap */
243 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 244
245 /* GPU object info for stuff used in-kernel (mm_enabled) */
246 uint32_t m2mf_ntfy;
247 uint32_t vram_handle;
248 uint32_t gart_handle;
249 bool accel_done;
250
251 /* Push buffer state (only for drm's channel on !mm_enabled) */
252 struct {
253 int max;
254 int free;
255 int cur;
256 int put;
257 /* access via pushbuf_bo */
9a391ad8
BS		 258
259 int ib_base;
260 int ib_max;
261 int ib_free;
262 int ib_put;
6ee73861
BS		 263 } dma;
264
265 uint32_t sw_subchannel[8];
266
267 struct {
268 struct nouveau_gpuobj *vblsem;
1f6d2de2 269 uint32_t vblsem_head;
6ee73861
BS		 270 uint32_t vblsem_offset;
271 uint32_t vblsem_rval;
272 struct list_head vbl_wait;
332b242f 273 struct list_head flip;
6ee73861
BS		 274 } nvsw;
275
276 struct {
277 bool active;
278 char name[32];
279 struct drm_info_list info;
280 } debugfs;
281};
282
283struct nouveau_instmem_engine {
284 void *priv;
285
286 int (*init)(struct drm_device *dev);
287 void (*takedown)(struct drm_device *dev);
288 int (*suspend)(struct drm_device *dev);
289 void (*resume)(struct drm_device *dev);
290
291 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
9100468d 292 u32 *size, u32 align);
6ee73861
BS		 293 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
294 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
295 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 296 void (*flush)(struct drm_device *);
6ee73861
BS		 297};
298
299struct nouveau_mc_engine {
300 int (*init)(struct drm_device *dev);
301 void (*takedown)(struct drm_device *dev);
302};
303
304struct nouveau_timer_engine {
305 int (*init)(struct drm_device *dev);
306 void (*takedown)(struct drm_device *dev);
307 uint64_t (*read)(struct drm_device *dev);
308};
309
310struct nouveau_fb_engine {
cb00f7c1 311 int num_tiles;
87a326a3 312 struct drm_mm tag_heap;
cb00f7c1 313
6ee73861
BS		 314 int (*init)(struct drm_device *dev);
315 void (*takedown)(struct drm_device *dev);
cb00f7c1 316
a5cf68b0
FJ		 317 void (*init_tile_region)(struct drm_device *dev, int i,
318 uint32_t addr, uint32_t size,
319 uint32_t pitch, uint32_t flags);
320 void (*set_tile_region)(struct drm_device *dev, int i);
321 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 322};
323
324struct nouveau_fifo_engine {
6ee73861
BS		 325 int channels;
326
a8eaebc6 327 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 328 int cur_playlist;
329
6ee73861
BS		 330 int (*init)(struct drm_device *);
331 void (*takedown)(struct drm_device *);
332
333 void (*disable)(struct drm_device *);
334 void (*enable)(struct drm_device *);
335 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 336 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 337
338 int (*channel_id)(struct drm_device *);
339
340 int (*create_context)(struct nouveau_channel *);
341 void (*destroy_context)(struct nouveau_channel *);
342 int (*load_context)(struct nouveau_channel *);
343 int (*unload_context)(struct drm_device *);
56ac7475 344 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 345};
346
6ee73861 347struct nouveau_pgraph_engine {
6ee73861 348 bool accel_blocked;
b8c157d3 349 bool registered;
054b93e4 350 int grctx_size;
6ee73861 351
c50a5681 352 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 353 struct nouveau_gpuobj *ctx_table;
c50a5681 354
6ee73861
BS		 355 int (*init)(struct drm_device *);
356 void (*takedown)(struct drm_device *);
357
358 void (*fifo_access)(struct drm_device *, bool);
359
360 struct nouveau_channel *(*channel)(struct drm_device *);
361 int (*create_context)(struct nouveau_channel *);
362 void (*destroy_context)(struct nouveau_channel *);
363 int (*load_context)(struct nouveau_channel *);
364 int (*unload_context)(struct drm_device *);
56ac7475 365 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1 366
a5cf68b0 367 void (*set_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 368};
369
c88c2e06
FJ		 370struct nouveau_display_engine {
371 int (*early_init)(struct drm_device *);
372 void (*late_takedown)(struct drm_device *);
373 int (*create)(struct drm_device *);
374 int (*init)(struct drm_device *);
375 void (*destroy)(struct drm_device *);
376};
377
ee2e0131
BS		 378struct nouveau_gpio_engine {
379 int (*init)(struct drm_device *);
380 void (*takedown)(struct drm_device *);
381
382 int (*get)(struct drm_device *, enum dcb_gpio_tag);
383 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
384
385 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
386};
387
330c5988
BS		 388struct nouveau_pm_voltage_level {
389 u8 voltage;
390 u8 vid;
391};
392
393struct nouveau_pm_voltage {
394 bool supported;
395 u8 vid_mask;
396
397 struct nouveau_pm_voltage_level *level;
398 int nr_level;
399};
400
401#define NOUVEAU_PM_MAX_LEVEL 8
402struct nouveau_pm_level {
403 struct device_attribute dev_attr;
404 char name[32];
405 int id;
406
407 u32 core;
408 u32 memory;
409 u32 shader;
410 u32 unk05;
411
412 u8 voltage;
413 u8 fanspeed;
aee582de
BS		 414
415 u16 memscript;
330c5988
BS		 416};
417
34e9d85a
MP		 418struct nouveau_pm_temp_sensor_constants {
419 u16 offset_constant;
420 s16 offset_mult;
421 u16 offset_div;
422 u16 slope_mult;
423 u16 slope_div;
424};
425
426struct nouveau_pm_threshold_temp {
427 s16 critical;
428 s16 down_clock;
429 s16 fan_boost;
430};
431
7760fcb0
RS		 432struct nouveau_pm_memtiming {
433 u32 reg_100220;
434 u32 reg_100224;
435 u32 reg_100228;
436 u32 reg_10022c;
437 u32 reg_100230;
438 u32 reg_100234;
439 u32 reg_100238;
440 u32 reg_10023c;
441};
442
443struct nouveau_pm_memtimings {
444 bool supported;
445 struct nouveau_pm_memtiming *timing;
446 int nr_timing;
447};
448
330c5988
BS		 449struct nouveau_pm_engine {
450 struct nouveau_pm_voltage voltage;
451 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
452 int nr_perflvl;
7760fcb0 453 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 454 struct nouveau_pm_temp_sensor_constants sensor_constants;
455 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 456
457 struct nouveau_pm_level boot;
458 struct nouveau_pm_level *cur;
459
8155cac4 460 struct device *hwmon;
6032649d 461 struct notifier_block acpi_nb;
8155cac4 462
330c5988 463 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 464 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
465 u32 id, int khz);
330c5988
BS		 466 void (*clock_set)(struct drm_device *, void *);
467 int (*voltage_get)(struct drm_device *);
468 int (*voltage_set)(struct drm_device *, int voltage);
469 int (*fanspeed_get)(struct drm_device *);
470 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 471 int (*temp_get)(struct drm_device *);
330c5988
BS		 472};
473
bd2e597d
BS		 474struct nouveau_crypt_engine {
475 bool registered;
476
477 int (*init)(struct drm_device *);
478 void (*takedown)(struct drm_device *);
479 int (*create_context)(struct nouveau_channel *);
480 void (*destroy_context)(struct nouveau_channel *);
481 void (*tlb_flush)(struct drm_device *dev);
482};
483
6ee73861
BS		 484struct nouveau_engine {
485 struct nouveau_instmem_engine instmem;
486 struct nouveau_mc_engine mc;
487 struct nouveau_timer_engine timer;
488 struct nouveau_fb_engine fb;
489 struct nouveau_pgraph_engine graph;
490 struct nouveau_fifo_engine fifo;
c88c2e06 491 struct nouveau_display_engine display;
ee2e0131 492 struct nouveau_gpio_engine gpio;
330c5988 493 struct nouveau_pm_engine pm;
bd2e597d 494 struct nouveau_crypt_engine crypt;
6ee73861
BS		 495};
496
497struct nouveau_pll_vals {
498 union {
499 struct {
500#ifdef __BIG_ENDIAN
501 uint8_t N1, M1, N2, M2;
502#else
503 uint8_t M1, N1, M2, N2;
504#endif
505 };
506 struct {
507 uint16_t NM1, NM2;
508 } __attribute__((packed));
509 };
510 int log2P;
511
512 int refclk;
513};
514
515enum nv04_fp_display_regs {
516 FP_DISPLAY_END,
517 FP_TOTAL,
518 FP_CRTC,
519 FP_SYNC_START,
520 FP_SYNC_END,
521 FP_VALID_START,
522 FP_VALID_END
523};
524
525struct nv04_crtc_reg {
cbab95db 526 unsigned char MiscOutReg;
4a9f822f 527 uint8_t CRTC[0xa0];
6ee73861
BS		 528 uint8_t CR58[0x10];
529 uint8_t Sequencer[5];
530 uint8_t Graphics[9];
531 uint8_t Attribute[21];
cbab95db 532 unsigned char DAC[768];
6ee73861
BS		 533
534 /* PCRTC regs */
535 uint32_t fb_start;
536 uint32_t crtc_cfg;
537 uint32_t cursor_cfg;
538 uint32_t gpio_ext;
539 uint32_t crtc_830;
540 uint32_t crtc_834;
541 uint32_t crtc_850;
542 uint32_t crtc_eng_ctrl;
543
544 /* PRAMDAC regs */
545 uint32_t nv10_cursync;
546 struct nouveau_pll_vals pllvals;
547 uint32_t ramdac_gen_ctrl;
548 uint32_t ramdac_630;
549 uint32_t ramdac_634;
550 uint32_t tv_setup;
551 uint32_t tv_vtotal;
552 uint32_t tv_vskew;
553 uint32_t tv_vsync_delay;
554 uint32_t tv_htotal;
555 uint32_t tv_hskew;
556 uint32_t tv_hsync_delay;
557 uint32_t tv_hsync_delay2;
558 uint32_t fp_horiz_regs[7];
559 uint32_t fp_vert_regs[7];
560 uint32_t dither;
561 uint32_t fp_control;
562 uint32_t dither_regs[6];
563 uint32_t fp_debug_0;
564 uint32_t fp_debug_1;
565 uint32_t fp_debug_2;
566 uint32_t fp_margin_color;
567 uint32_t ramdac_8c0;
568 uint32_t ramdac_a20;
569 uint32_t ramdac_a24;
570 uint32_t ramdac_a34;
571 uint32_t ctv_regs[38];
572};
573
574struct nv04_output_reg {
575 uint32_t output;
576 int head;
577};
578
579struct nv04_mode_state {
cbab95db 580 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 581 uint32_t pllsel;
582 uint32_t sel_clk;
6ee73861
BS		 583};
584
585enum nouveau_card_type {
586 NV_04 = 0x00,
587 NV_10 = 0x10,
588 NV_20 = 0x20,
589 NV_30 = 0x30,
590 NV_40 = 0x40,
591 NV_50 = 0x50,
4b223eef 592 NV_C0 = 0xc0,
6ee73861
BS		 593};
594
595struct drm_nouveau_private {
596 struct drm_device *dev;
6ee73861
BS		 597
598 /* the card type, takes NV_* as values */
599 enum nouveau_card_type card_type;
600 /* exact chipset, derived from NV_PMC_BOOT_0 */
601 int chipset;
602 int flags;
603
604 void __iomem *mmio;
5125bfd8 605
e05d7eae 606 spinlock_t ramin_lock;
6ee73861 607 void __iomem *ramin;
5125bfd8
BS		 608 u32 ramin_size;
609 u32 ramin_base;
610 bool ramin_available;
e05d7eae
BS		 611 struct drm_mm ramin_heap;
612 struct list_head gpuobj_list;
b8c157d3 613 struct list_head classes;
6ee73861 614
ac8fb975
BS		 615 struct nouveau_bo *vga_ram;
616
35fa2f2a 617 /* interrupt handling */
8f8a5448 618 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 619 bool msi_enabled;
6ee73861
BS		 620 struct workqueue_struct *wq;
621 struct work_struct irq_work;
a5acac66 622 struct work_struct hpd_work;
6ee73861 623
ab838338
AL		 624 struct {
625 spinlock_t lock;
626 uint32_t hpd0_bits;
627 uint32_t hpd1_bits;
628 } hpd_state;
629
6ee73861
BS		 630 struct list_head vbl_waiting;
631
632 struct {
ba4420c2 633 struct drm_global_reference mem_global_ref;
6ee73861
BS		 634 struct ttm_bo_global_ref bo_global_ref;
635 struct ttm_bo_device bdev;
6ee73861
BS		 636 atomic_t validate_sequence;
637 } ttm;
638
0c6c1c2f
FJ		 639 struct {
640 spinlock_t lock;
641 struct drm_mm heap;
642 struct nouveau_bo *bo;
643 } fence;
644
cff5c133
BS		 645 struct {
646 spinlock_t lock;
647 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
648 } channels;
6ee73861
BS		 649
650 struct nouveau_engine engine;
651 struct nouveau_channel *channel;
652
ff9e5279
MM		 653 /* For PFIFO and PGRAPH. */
654 spinlock_t context_switch_lock;
655
6ee73861 656 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 657 struct nouveau_ramht *ramht;
658 struct nouveau_gpuobj *ramfc;
659 struct nouveau_gpuobj *ramro;
660
6ee73861 661 uint32_t ramin_rsvd_vram;
6ee73861 662
6ee73861
BS		 663 struct {
664 enum {
665 NOUVEAU_GART_NONE = 0,
666 NOUVEAU_GART_AGP,
667 NOUVEAU_GART_SGDMA
668 } type;
669 uint64_t aper_base;
670 uint64_t aper_size;
671 uint64_t aper_free;
672
673 struct nouveau_gpuobj *sg_ctxdma;
674 struct page *sg_dummy_page;
675 dma_addr_t sg_dummy_bus;
6ee73861
BS		 676 } gart_info;
677
a0af9add 678 /* nv10-nv40 tiling regions */
a5cf68b0
FJ		 679 struct {
680 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
681 spinlock_t lock;
682 } tile;
a0af9add 683
a76fb4e8
BS		 684 /* VRAM/fb configuration */
685 uint64_t vram_size;
686 uint64_t vram_sys_base;
6c3d7ef2 687 u32 vram_rblock_size;
a76fb4e8
BS		 688
689 uint64_t fb_phys;
690 uint64_t fb_available_size;
691 uint64_t fb_mappable_pages;
692 uint64_t fb_aper_free;
693 int fb_mtrr;
694
6ee73861
BS		 695 /* G8x/G9x virtual address space */
696 uint64_t vm_gart_base;
697 uint64_t vm_gart_size;
698 uint64_t vm_vram_base;
699 uint64_t vm_vram_size;
700 uint64_t vm_end;
701 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
702 int vm_vram_pt_nr;
6ee73861 703
04a39c57 704 struct nvbios vbios;
6ee73861
BS		 705
706 struct nv04_mode_state mode_reg;
707 struct nv04_mode_state saved_reg;
708 uint32_t saved_vga_font[4][16384];
709 uint32_t crtc_owner;
710 uint32_t dac_users[4];
711
712 struct nouveau_suspend_resume {
6ee73861 713 uint32_t *ramin_copy;
6ee73861
BS		 714 } susres;
715
716 struct backlight_device *backlight;
6ee73861
BS		 717
718 struct nouveau_channel *evo;
1e96268a 719 u32 evo_alloc;
87c0e0e5
BS		 720 struct {
721 struct dcb_entry *dcb;
722 u16 script;
723 u32 pclk;
724 } evo_irq;
6ee73861
BS		 725
726 struct {
727 struct dentry *channel_root;
728 } debugfs;
38651674 729
8be48d92 730 struct nouveau_fbdev *nfbdev;
06415c56 731 struct apertures_struct *apertures;
6ee73861
BS		 732};
733
2730723b
FJ		 734static inline struct drm_nouveau_private *
735nouveau_private(struct drm_device *dev)
736{
737 return dev->dev_private;
738}
739
6ee73861
BS		 740static inline struct drm_nouveau_private *
741nouveau_bdev(struct ttm_bo_device *bd)
742{
743 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
744}
745
746static inline int
747nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
748{
749 struct nouveau_bo *prev;
750
751 if (!pnvbo)
752 return -EINVAL;
753 prev = *pnvbo;
754
755 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
756 if (prev) {
757 struct ttm_buffer_object *bo = &prev->bo;
758
759 ttm_bo_unref(&bo);
760 }
761
762 return 0;
763}
764
6ee73861 765/* nouveau_drv.c */
de5899bd 766extern int nouveau_agpmode;
6ee73861
BS		 767extern int nouveau_duallink;
768extern int nouveau_uscript_lvds;
769extern int nouveau_uscript_tmds;
770extern int nouveau_vram_pushbuf;
771extern int nouveau_vram_notify;
772extern int nouveau_fbpercrtc;
f4053509 773extern int nouveau_tv_disable;
6ee73861
BS		 774extern char *nouveau_tv_norm;
775extern int nouveau_reg_debug;
776extern char *nouveau_vbios;
a1470890 777extern int nouveau_ignorelid;
a32ed69d
MK		 778extern int nouveau_nofbaccel;
779extern int nouveau_noaccel;
0cba1b76 780extern int nouveau_force_post;
da647d5b 781extern int nouveau_override_conntype;
6f876986
BS		 782extern char *nouveau_perflvl;
783extern int nouveau_perflvl_wr;
35fa2f2a 784extern int nouveau_msi;
6ee73861 785
6a9ee8af
DA		 786extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
787extern int nouveau_pci_resume(struct pci_dev *pdev);
788
6ee73861
BS		 789/* nouveau_state.c */
790extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
791extern int nouveau_load(struct drm_device *, unsigned long flags);
792extern int nouveau_firstopen(struct drm_device *);
793extern void nouveau_lastclose(struct drm_device *);
794extern int nouveau_unload(struct drm_device *);
795extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
796 struct drm_file *);
797extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
798 struct drm_file *);
799extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
800 uint32_t reg, uint32_t mask, uint32_t val);
801extern bool nouveau_wait_for_idle(struct drm_device *);
802extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 803
804/* nouveau_mem.c */
fbd2895e
BS		 805extern int nouveau_mem_vram_init(struct drm_device *);
806extern void nouveau_mem_vram_fini(struct drm_device *);
807extern int nouveau_mem_gart_init(struct drm_device *);
808extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 809extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 810extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 811extern void nouveau_mem_close(struct drm_device *);
a5cf68b0
FJ		 812extern struct nouveau_tile_reg *nv10_mem_set_tiling(
813 struct drm_device *dev, uint32_t addr, uint32_t size,
814 uint32_t pitch, uint32_t flags);
815extern void nv10_mem_put_tile_region(struct drm_device *dev,
816 struct nouveau_tile_reg *tile,
817 struct nouveau_fence *fence);
6ee73861
BS		 818extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
819 uint32_t size, uint32_t flags,
820 uint64_t phys);
821extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
822 uint32_t size);
823
824/* nouveau_notifier.c */
825extern int nouveau_notifier_init_channel(struct nouveau_channel *);
826extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
827extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
828 int cout, uint32_t *offset);
829extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
830extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
831 struct drm_file *);
832extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
833 struct drm_file *);
834
835/* nouveau_channel.c */
836extern struct drm_ioctl_desc nouveau_ioctls[];
837extern int nouveau_max_ioctl;
838extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 839extern int nouveau_channel_alloc(struct drm_device *dev,
840 struct nouveau_channel **chan,
841 struct drm_file *file_priv,
842 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 843extern struct nouveau_channel *
feeb0aec
FJ		 844nouveau_channel_get_unlocked(struct nouveau_channel *);
845extern struct nouveau_channel *
cff5c133 846nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 847extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 848extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 849extern void nouveau_channel_ref(struct nouveau_channel *chan,
850 struct nouveau_channel **pchan);
6ee73861
BS		 851
852/* nouveau_object.c */
b8c157d3
BS		 853#define NVOBJ_CLASS(d,c,e) do { \
854 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
855 if (ret) \
856 return ret; \
857} while(0)
858
859#define NVOBJ_MTHD(d,c,m,e) do { \
860 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
861 if (ret) \
862 return ret; \
863} while(0)
864
6ee73861
BS		 865extern int nouveau_gpuobj_early_init(struct drm_device *);
866extern int nouveau_gpuobj_init(struct drm_device *);
867extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 868extern int nouveau_gpuobj_suspend(struct drm_device *dev);
869extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
870extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 871extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
872extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
873 int (*exec)(struct nouveau_channel *,
874 u32 class, u32 mthd, u32 data));
875extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
274fec93 876extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
6ee73861
BS		 877extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
878 uint32_t vram_h, uint32_t tt_h);
879extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
880extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
881 uint32_t size, int align, uint32_t flags,
882 struct nouveau_gpuobj **);
a8eaebc6
BS		 883extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
884 struct nouveau_gpuobj **);
43efc9ce
BS		 885extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
886 u32 size, u32 flags,
a8eaebc6 887 struct nouveau_gpuobj **);
6ee73861
BS		 888extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
889 uint64_t offset, uint64_t size, int access,
890 int target, struct nouveau_gpuobj **);
891extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
892 uint64_t offset, uint64_t size,
893 int access, struct nouveau_gpuobj **,
894 uint32_t *o_ret);
895extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
896 struct nouveau_gpuobj **);
897extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
898 struct drm_file *);
899extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
900 struct drm_file *);
901
902/* nouveau_irq.c */
35fa2f2a
BS		 903extern int nouveau_irq_init(struct drm_device *);
904extern void nouveau_irq_fini(struct drm_device *);
6ee73861 905extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS		 906extern void nouveau_irq_register(struct drm_device *, int status_bit,
907 void (*)(struct drm_device *));
908extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS		 909extern void nouveau_irq_preinstall(struct drm_device *);
910extern int nouveau_irq_postinstall(struct drm_device *);
911extern void nouveau_irq_uninstall(struct drm_device *);
912
913/* nouveau_sgdma.c */
914extern int nouveau_sgdma_init(struct drm_device *);
915extern void nouveau_sgdma_takedown(struct drm_device *);
916extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
917 uint32_t *page);
918extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
919
920/* nouveau_debugfs.c */
921#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
922extern int nouveau_debugfs_init(struct drm_minor *);
923extern void nouveau_debugfs_takedown(struct drm_minor *);
924extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
925extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
926#else
927static inline int
928nouveau_debugfs_init(struct drm_minor *minor)
929{
930 return 0;
931}
932
933static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
934{
935}
936
937static inline int
938nouveau_debugfs_channel_init(struct nouveau_channel *chan)
939{
940 return 0;
941}
942
943static inline void
944nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
945{
946}
947#endif
948
949/* nouveau_dma.c */
75c99da6 950extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 951extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 952extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 953
954/* nouveau_acpi.c */
afeb3e11 955#define ROM_BIOS_PAGE 4096
2f41a7f1 956#if defined(CONFIG_ACPI)
6a9ee8af
DA		 957void nouveau_register_dsm_handler(void);
958void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 959int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
960bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 961int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 962#else
963static inline void nouveau_register_dsm_handler(void) {}
964static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 965static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
966static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 967static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 968#endif
6ee73861
BS		 969
970/* nouveau_backlight.c */
971#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
972extern int nouveau_backlight_init(struct drm_device *);
973extern void nouveau_backlight_exit(struct drm_device *);
974#else
975static inline int nouveau_backlight_init(struct drm_device *dev)
976{
977 return 0;
978}
979
980static inline void nouveau_backlight_exit(struct drm_device *dev) { }
981#endif
982
983/* nouveau_bios.c */
984extern int nouveau_bios_init(struct drm_device *);
985extern void nouveau_bios_takedown(struct drm_device *dev);
986extern int nouveau_run_vbios_init(struct drm_device *);
987extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
988 struct dcb_entry *);
989extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
990 enum dcb_gpio_tag);
991extern struct dcb_connector_table_entry *
992nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 993extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 994extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
995 struct pll_lims *);
996extern int nouveau_bios_run_display_table(struct drm_device *,
997 struct dcb_entry *,
998 uint32_t script, int pxclk);
999extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1000 int *length);
1001extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1002extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1003extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1004 bool *dl, bool *if_is_24bit);
1005extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1006 int head, int pxclk);
1007extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1008 enum LVDS_script, int pxclk);
1009
1010/* nouveau_ttm.c */
1011int nouveau_ttm_global_init(struct drm_nouveau_private *);
1012void nouveau_ttm_global_release(struct drm_nouveau_private *);
1013int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1014
1015/* nouveau_dp.c */
1016int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1017 uint8_t *data, int data_nr);
1018bool nouveau_dp_detect(struct drm_encoder *);
1019bool nouveau_dp_link_train(struct drm_encoder *);
1020
1021/* nv04_fb.c */
1022extern int nv04_fb_init(struct drm_device *);
1023extern void nv04_fb_takedown(struct drm_device *);
1024
1025/* nv10_fb.c */
1026extern int nv10_fb_init(struct drm_device *);
1027extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1028extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1029 uint32_t addr, uint32_t size,
1030 uint32_t pitch, uint32_t flags);
1031extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1032extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1033
8bded189
FJ		 1034/* nv30_fb.c */
1035extern int nv30_fb_init(struct drm_device *);
1036extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1037extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1038 uint32_t addr, uint32_t size,
1039 uint32_t pitch, uint32_t flags);
1040extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1041
6ee73861
BS		 1042/* nv40_fb.c */
1043extern int nv40_fb_init(struct drm_device *);
1044extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1045extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1046
304424e1
MK		 1047/* nv50_fb.c */
1048extern int nv50_fb_init(struct drm_device *);
1049extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1050extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1051
4b223eef
BS		 1052/* nvc0_fb.c */
1053extern int nvc0_fb_init(struct drm_device *);
1054extern void nvc0_fb_takedown(struct drm_device *);
1055
6ee73861
BS		 1056/* nv04_fifo.c */
1057extern int nv04_fifo_init(struct drm_device *);
5178d40d 1058extern void nv04_fifo_fini(struct drm_device *);
6ee73861
BS		 1059extern void nv04_fifo_disable(struct drm_device *);
1060extern void nv04_fifo_enable(struct drm_device *);
1061extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1062extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1063extern int nv04_fifo_channel_id(struct drm_device *);
1064extern int nv04_fifo_create_context(struct nouveau_channel *);
1065extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1066extern int nv04_fifo_load_context(struct nouveau_channel *);
1067extern int nv04_fifo_unload_context(struct drm_device *);
5178d40d 1068extern void nv04_fifo_isr(struct drm_device *);
6ee73861
BS		 1069
1070/* nv10_fifo.c */
1071extern int nv10_fifo_init(struct drm_device *);
1072extern int nv10_fifo_channel_id(struct drm_device *);
1073extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1074extern int nv10_fifo_load_context(struct nouveau_channel *);
1075extern int nv10_fifo_unload_context(struct drm_device *);
1076
1077/* nv40_fifo.c */
1078extern int nv40_fifo_init(struct drm_device *);
1079extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1080extern int nv40_fifo_load_context(struct nouveau_channel *);
1081extern int nv40_fifo_unload_context(struct drm_device *);
1082
1083/* nv50_fifo.c */
1084extern int nv50_fifo_init(struct drm_device *);
1085extern void nv50_fifo_takedown(struct drm_device *);
1086extern int nv50_fifo_channel_id(struct drm_device *);
1087extern int nv50_fifo_create_context(struct nouveau_channel *);
1088extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1089extern int nv50_fifo_load_context(struct nouveau_channel *);
1090extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1091extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1092
4b223eef
BS		 1093/* nvc0_fifo.c */
1094extern int nvc0_fifo_init(struct drm_device *);
1095extern void nvc0_fifo_takedown(struct drm_device *);
1096extern void nvc0_fifo_disable(struct drm_device *);
1097extern void nvc0_fifo_enable(struct drm_device *);
1098extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1099extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1100extern int nvc0_fifo_channel_id(struct drm_device *);
1101extern int nvc0_fifo_create_context(struct nouveau_channel *);
1102extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1103extern int nvc0_fifo_load_context(struct nouveau_channel *);
1104extern int nvc0_fifo_unload_context(struct drm_device *);
1105
6ee73861 1106/* nv04_graph.c */
6ee73861
BS		 1107extern int nv04_graph_init(struct drm_device *);
1108extern void nv04_graph_takedown(struct drm_device *);
1109extern void nv04_graph_fifo_access(struct drm_device *, bool);
1110extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1111extern int nv04_graph_create_context(struct nouveau_channel *);
1112extern void nv04_graph_destroy_context(struct nouveau_channel *);
1113extern int nv04_graph_load_context(struct nouveau_channel *);
1114extern int nv04_graph_unload_context(struct drm_device *);
332b242f
FJ		 1115extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1116 u32 class, u32 mthd, u32 data);
274fec93 1117extern struct nouveau_bitfield nv04_graph_nsource[];
6ee73861
BS		 1118
1119/* nv10_graph.c */
6ee73861
BS		 1120extern int nv10_graph_init(struct drm_device *);
1121extern void nv10_graph_takedown(struct drm_device *);
1122extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1123extern int nv10_graph_create_context(struct nouveau_channel *);
1124extern void nv10_graph_destroy_context(struct nouveau_channel *);
1125extern int nv10_graph_load_context(struct nouveau_channel *);
1126extern int nv10_graph_unload_context(struct drm_device *);
a5cf68b0 1127extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
274fec93
BS		 1128extern struct nouveau_bitfield nv10_graph_intr[];
1129extern struct nouveau_bitfield nv10_graph_nstatus[];
6ee73861
BS		 1130
1131/* nv20_graph.c */
6ee73861
BS		 1132extern int nv20_graph_create_context(struct nouveau_channel *);
1133extern void nv20_graph_destroy_context(struct nouveau_channel *);
1134extern int nv20_graph_load_context(struct nouveau_channel *);
1135extern int nv20_graph_unload_context(struct drm_device *);
1136extern int nv20_graph_init(struct drm_device *);
1137extern void nv20_graph_takedown(struct drm_device *);
1138extern int nv30_graph_init(struct drm_device *);
a5cf68b0 1139extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1140
1141/* nv40_graph.c */
6ee73861
BS		 1142extern int nv40_graph_init(struct drm_device *);
1143extern void nv40_graph_takedown(struct drm_device *);
1144extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1145extern int nv40_graph_create_context(struct nouveau_channel *);
1146extern void nv40_graph_destroy_context(struct nouveau_channel *);
1147extern int nv40_graph_load_context(struct nouveau_channel *);
1148extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1149extern void nv40_grctx_init(struct nouveau_grctx *);
a5cf68b0 1150extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1151
1152/* nv50_graph.c */
6ee73861
BS		 1153extern int nv50_graph_init(struct drm_device *);
1154extern void nv50_graph_takedown(struct drm_device *);
1155extern void nv50_graph_fifo_access(struct drm_device *, bool);
1156extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1157extern int nv50_graph_create_context(struct nouveau_channel *);
1158extern void nv50_graph_destroy_context(struct nouveau_channel *);
1159extern int nv50_graph_load_context(struct nouveau_channel *);
1160extern int nv50_graph_unload_context(struct drm_device *);
d5f3c90d 1161extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1162extern void nv50_graph_tlb_flush(struct drm_device *dev);
1163extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1164
4b223eef
BS		 1165/* nvc0_graph.c */
1166extern int nvc0_graph_init(struct drm_device *);
1167extern void nvc0_graph_takedown(struct drm_device *);
1168extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1169extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1170extern int nvc0_graph_create_context(struct nouveau_channel *);
1171extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1172extern int nvc0_graph_load_context(struct nouveau_channel *);
1173extern int nvc0_graph_unload_context(struct drm_device *);
1174
bd2e597d
BS		 1175/* nv84_crypt.c */
1176extern int nv84_crypt_init(struct drm_device *dev);
1177extern void nv84_crypt_fini(struct drm_device *dev);
1178extern int nv84_crypt_create_context(struct nouveau_channel *);
1179extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1180extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1181
6ee73861
BS		 1182/* nv04_instmem.c */
1183extern int nv04_instmem_init(struct drm_device *);
1184extern void nv04_instmem_takedown(struct drm_device *);
1185extern int nv04_instmem_suspend(struct drm_device *);
1186extern void nv04_instmem_resume(struct drm_device *);
1187extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1188 u32 *size, u32 align);
6ee73861
BS		 1189extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1190extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1191extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1192extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1193
1194/* nv50_instmem.c */
1195extern int nv50_instmem_init(struct drm_device *);
1196extern void nv50_instmem_takedown(struct drm_device *);
1197extern int nv50_instmem_suspend(struct drm_device *);
1198extern void nv50_instmem_resume(struct drm_device *);
1199extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1200 u32 *size, u32 align);
6ee73861
BS		 1201extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1202extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1203extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1204extern void nv50_instmem_flush(struct drm_device *);
734ee835 1205extern void nv84_instmem_flush(struct drm_device *);
63187215 1206extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1207
4b223eef
BS		 1208/* nvc0_instmem.c */
1209extern int nvc0_instmem_init(struct drm_device *);
1210extern void nvc0_instmem_takedown(struct drm_device *);
1211extern int nvc0_instmem_suspend(struct drm_device *);
1212extern void nvc0_instmem_resume(struct drm_device *);
1213extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1214 u32 *size, u32 align);
4b223eef
BS		 1215extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1216extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1217extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1218extern void nvc0_instmem_flush(struct drm_device *);
1219
6ee73861
BS		 1220/* nv04_mc.c */
1221extern int nv04_mc_init(struct drm_device *);
1222extern void nv04_mc_takedown(struct drm_device *);
1223
1224/* nv40_mc.c */
1225extern int nv40_mc_init(struct drm_device *);
1226extern void nv40_mc_takedown(struct drm_device *);
1227
1228/* nv50_mc.c */
1229extern int nv50_mc_init(struct drm_device *);
1230extern void nv50_mc_takedown(struct drm_device *);
1231
1232/* nv04_timer.c */
1233extern int nv04_timer_init(struct drm_device *);
1234extern uint64_t nv04_timer_read(struct drm_device *);
1235extern void nv04_timer_takedown(struct drm_device *);
1236
1237extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1238 unsigned long arg);
1239
1240/* nv04_dac.c */
8f1a6086 1241extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1242extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1243extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1244extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1245extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1246
1247/* nv04_dfp.c */
8f1a6086 1248extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1249extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1250extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1251 int head, bool dl);
1252extern void nv04_dfp_disable(struct drm_device *dev, int head);
1253extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1254
1255/* nv04_tv.c */
1256extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1257extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1258
1259/* nv17_tv.c */
8f1a6086 1260extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1261
1262/* nv04_display.c */
c88c2e06
FJ		 1263extern int nv04_display_early_init(struct drm_device *);
1264extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1265extern int nv04_display_create(struct drm_device *);
c88c2e06 1266extern int nv04_display_init(struct drm_device *);
6ee73861 1267extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1268
1269/* nv04_crtc.c */
1270extern int nv04_crtc_create(struct drm_device *, int index);
1271
1272/* nouveau_bo.c */
1273extern struct ttm_bo_driver nouveau_bo_driver;
1274extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1275 int size, int align, uint32_t flags,
1276 uint32_t tile_mode, uint32_t tile_flags,
1277 bool no_vm, bool mappable, struct nouveau_bo **);
1278extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1279extern int nouveau_bo_unpin(struct nouveau_bo *);
1280extern int nouveau_bo_map(struct nouveau_bo *);
1281extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1282extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1283 uint32_t busy);
6ee73861
BS		 1284extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1285extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1286extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1287extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1288extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
6ee73861
BS		 1289
1290/* nouveau_fence.c */
1291struct nouveau_fence;
0c6c1c2f
FJ		 1292extern int nouveau_fence_init(struct drm_device *);
1293extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1294extern int nouveau_fence_channel_init(struct nouveau_channel *);
1295extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1296extern void nouveau_fence_update(struct nouveau_channel *);
1297extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1298 bool emit);
1299extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1300extern void nouveau_fence_work(struct nouveau_fence *fence,
1301 void (*work)(void *priv, bool signalled),
1302 void *priv);
6ee73861 1303struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1304
1305extern bool __nouveau_fence_signalled(void *obj, void *arg);
1306extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1307extern int __nouveau_fence_flush(void *obj, void *arg);
1308extern void __nouveau_fence_unref(void **obj);
1309extern void *__nouveau_fence_ref(void *obj);
1310
1311static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1312{
1313 return __nouveau_fence_signalled(obj, NULL);
1314}
1315static inline int
1316nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1317{
1318 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1319}
2730723b 1320extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1321static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1322{
1323 return __nouveau_fence_flush(obj, NULL);
1324}
1325static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1326{
1327 __nouveau_fence_unref((void **)obj);
1328}
1329static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1330{
1331 return __nouveau_fence_ref(obj);
1332}
6ee73861
BS		 1333
1334/* nouveau_gem.c */
1335extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1336 int size, int align, uint32_t flags,
1337 uint32_t tile_mode, uint32_t tile_flags,
1338 bool no_vm, bool mappable, struct nouveau_bo **);
1339extern int nouveau_gem_object_new(struct drm_gem_object *);
1340extern void nouveau_gem_object_del(struct drm_gem_object *);
1341extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1342 struct drm_file *);
1343extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1344 struct drm_file *);
6ee73861
BS		 1345extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1346 struct drm_file *);
1347extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1348 struct drm_file *);
1349extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1350 struct drm_file *);
1351
042206c0
FJ		 1352/* nouveau_display.c */
1353int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1354void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1355int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1356 struct drm_pending_vblank_event *event);
1357int nouveau_finish_page_flip(struct nouveau_channel *,
1358 struct nouveau_page_flip_state *);
042206c0 1359
ee2e0131
BS		 1360/* nv10_gpio.c */
1361int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1362int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1363
45284162 1364/* nv50_gpio.c */
ee2e0131 1365int nv50_gpio_init(struct drm_device *dev);
2cbd4c81 1366void nv50_gpio_fini(struct drm_device *dev);
45284162
BS		 1367int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1368int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1369void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1370
e9ebb68b
BS		 1371/* nv50_calc. */
1372int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1373 int *N1, int *M1, int *N2, int *M2, int *P);
1374int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1375 int clk, int *N, int *fN, int *M, int *P);
1376
6ee73861
BS		 1377#ifndef ioread32_native
1378#ifdef __BIG_ENDIAN
1379#define ioread16_native ioread16be
1380#define iowrite16_native iowrite16be
1381#define ioread32_native ioread32be
1382#define iowrite32_native iowrite32be
1383#else /* def __BIG_ENDIAN */
1384#define ioread16_native ioread16
1385#define iowrite16_native iowrite16
1386#define ioread32_native ioread32
1387#define iowrite32_native iowrite32
1388#endif /* def __BIG_ENDIAN else */
1389#endif /* !ioread32_native */
1390
1391/* channel control reg access */
1392static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1393{
1394 return ioread32_native(chan->user + reg);
1395}
1396
1397static inline void nvchan_wr32(struct nouveau_channel *chan,
1398 unsigned reg, u32 val)
1399{
1400 iowrite32_native(val, chan->user + reg);
1401}
1402
1403/* register access */
1404static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1405{
1406 struct drm_nouveau_private *dev_priv = dev->dev_private;
1407 return ioread32_native(dev_priv->mmio + reg);
1408}
1409
1410static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1411{
1412 struct drm_nouveau_private *dev_priv = dev->dev_private;
1413 iowrite32_native(val, dev_priv->mmio + reg);
1414}
1415
2a7fdb2b 1416static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1417{
1418 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1419 nv_wr32(dev, reg, (tmp & ~mask) | val);
1420 return tmp;
49eed80a
BS		 1421}
1422
6ee73861
BS		 1423static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1424{
1425 struct drm_nouveau_private *dev_priv = dev->dev_private;
1426 return ioread8(dev_priv->mmio + reg);
1427}
1428
1429static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1430{
1431 struct drm_nouveau_private *dev_priv = dev->dev_private;
1432 iowrite8(val, dev_priv->mmio + reg);
1433}
1434
4b5c152a 1435#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1436 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1437
1438/* PRAMIN access */
1439static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1440{
1441 struct drm_nouveau_private *dev_priv = dev->dev_private;
1442 return ioread32_native(dev_priv->ramin + offset);
1443}
1444
1445static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1446{
1447 struct drm_nouveau_private *dev_priv = dev->dev_private;
1448 iowrite32_native(val, dev_priv->ramin + offset);
1449}
1450
1451/* object access */
b3beb167
BS		 1452extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1453extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1454
1455/*
1456 * Logging
1457 * Argument d is (struct drm_device *).
1458 */
1459#define NV_PRINTK(level, d, fmt, arg...) \
1460 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1461 pci_name(d->pdev), ##arg)
1462#ifndef NV_DEBUG_NOTRACE
1463#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1464 if (drm_debug & DRM_UT_DRIVER) { \
1465 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1466 __LINE__, ##arg); \
1467 } \
1468} while (0)
1469#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1470 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1471 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1472 __LINE__, ##arg); \
1473 } \
1474} while (0)
1475#else
1476#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1477 if (drm_debug & DRM_UT_DRIVER) \
1478 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1479} while (0)
1480#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1481 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1482 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1483} while (0)
1484#endif
1485#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1486#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1487#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1488#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1489#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1490
1491/* nouveau_reg_debug bitmask */
1492enum {
1493 NOUVEAU_REG_DEBUG_MC = 0x1,
1494 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1495 NOUVEAU_REG_DEBUG_FB = 0x4,
1496 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1497 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1498 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1499 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1500 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1501 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1502 NOUVEAU_REG_DEBUG_EVO = 0x200,
1503};
1504
1505#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1506 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1507 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1508} while (0)
1509
1510static inline bool
1511nv_two_heads(struct drm_device *dev)
1512{
1513 struct drm_nouveau_private *dev_priv = dev->dev_private;
1514 const int impl = dev->pci_device & 0x0ff0;
1515
1516 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1517 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1518 return true;
1519
1520 return false;
1521}
1522
1523static inline bool
1524nv_gf4_disp_arch(struct drm_device *dev)
1525{
1526 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1527}
1528
1529static inline bool
1530nv_two_reg_pll(struct drm_device *dev)
1531{
1532 struct drm_nouveau_private *dev_priv = dev->dev_private;
1533 const int impl = dev->pci_device & 0x0ff0;
1534
1535 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1536 return true;
1537 return false;
1538}
1539
acae116c
FJ		 1540static inline bool
1541nv_match_device(struct drm_device *dev, unsigned device,
1542 unsigned sub_vendor, unsigned sub_device)
1543{
1544 return dev->pdev->device == device &&
1545 dev->pdev->subsystem_vendor == sub_vendor &&
1546 dev->pdev->subsystem_device == sub_device;
1547}
1548
f03a314b
FJ		 1549#define NV_SW 0x0000506e
1550#define NV_SW_DMA_SEMAPHORE 0x00000060
1551#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1552#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1553#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1554#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1555#define NV_SW_DMA_VBLSEM 0x0000018c
1556#define NV_SW_VBLSEM_OFFSET 0x00000400
1557#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1558#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1559#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1560
1561#endif /* __NOUVEAU_DRV_H__ */
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