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drm/nouveau: Double the perf table memory clocks on pre-G71 cards.
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
6ee73861
BS		 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 138struct nouveau_gpuobj {
b3beb167 139 struct drm_device *dev;
eb9bcbdc 140 struct kref refcount;
6ee73861
BS		 141 struct list_head list;
142
b833ac26 143 struct drm_mm_node *im_pramin;
6ee73861 144 struct nouveau_bo *im_backing;
6ee73861
BS		 145 uint32_t *im_backing_suspend;
146 int im_bound;
147
148 uint32_t flags;
6ee73861 149
43efc9ce 150 u32 size;
de3a6c0a
BS		 151 u32 pinst;
152 u32 cinst;
153 u64 vinst;
154
6ee73861
BS		 155 uint32_t engine;
156 uint32_t class;
157
158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
159 void *priv;
160};
161
6ee73861
BS		 162struct nouveau_channel {
163 struct drm_device *dev;
164 int id;
165
166 /* owner of this fifo */
167 struct drm_file *file_priv;
168 /* mapping of the fifo itself */
169 struct drm_local_map *map;
170
171 /* mapping of the regs controling the fifo */
172 void __iomem *user;
173 uint32_t user_get;
174 uint32_t user_put;
175
176 /* Fencing */
177 struct {
178 /* lock protects the pending list only */
179 spinlock_t lock;
180 struct list_head pending;
181 uint32_t sequence;
182 uint32_t sequence_ack;
047d1d3c 183 atomic_t last_sequence_irq;
6ee73861
BS		 184 } fence;
185
186 /* DMA push buffer */
a8eaebc6
BS		 187 struct nouveau_gpuobj *pushbuf;
188 struct nouveau_bo *pushbuf_bo;
189 uint32_t pushbuf_base;
6ee73861
BS		 190
191 /* Notifier memory */
192 struct nouveau_bo *notifier_bo;
b833ac26 193 struct drm_mm notifier_heap;
6ee73861
BS		 194
195 /* PFIFO context */
a8eaebc6
BS		 196 struct nouveau_gpuobj *ramfc;
197 struct nouveau_gpuobj *cache;
6ee73861
BS		 198
199 /* PGRAPH context */
200 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 201 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 202 void *pgraph_ctx;
203
204 /* NV50 VM */
a8eaebc6
BS		 205 struct nouveau_gpuobj *vm_pd;
206 struct nouveau_gpuobj *vm_gart_pt;
207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 208
209 /* Objects */
a8eaebc6
BS		 210 struct nouveau_gpuobj *ramin; /* Private instmem */
211 struct drm_mm ramin_heap; /* Private PRAMIN heap */
212 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 213
214 /* GPU object info for stuff used in-kernel (mm_enabled) */
215 uint32_t m2mf_ntfy;
216 uint32_t vram_handle;
217 uint32_t gart_handle;
218 bool accel_done;
219
220 /* Push buffer state (only for drm's channel on !mm_enabled) */
221 struct {
222 int max;
223 int free;
224 int cur;
225 int put;
226 /* access via pushbuf_bo */
9a391ad8
BS		 227
228 int ib_base;
229 int ib_max;
230 int ib_free;
231 int ib_put;
6ee73861
BS		 232 } dma;
233
234 uint32_t sw_subchannel[8];
235
236 struct {
237 struct nouveau_gpuobj *vblsem;
238 uint32_t vblsem_offset;
239 uint32_t vblsem_rval;
240 struct list_head vbl_wait;
241 } nvsw;
242
243 struct {
244 bool active;
245 char name[32];
246 struct drm_info_list info;
247 } debugfs;
248};
249
250struct nouveau_instmem_engine {
251 void *priv;
252
253 int (*init)(struct drm_device *dev);
254 void (*takedown)(struct drm_device *dev);
255 int (*suspend)(struct drm_device *dev);
256 void (*resume)(struct drm_device *dev);
257
258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
259 uint32_t *size);
260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 263 void (*flush)(struct drm_device *);
6ee73861
BS		 264};
265
266struct nouveau_mc_engine {
267 int (*init)(struct drm_device *dev);
268 void (*takedown)(struct drm_device *dev);
269};
270
271struct nouveau_timer_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
274 uint64_t (*read)(struct drm_device *dev);
275};
276
277struct nouveau_fb_engine {
cb00f7c1
FJ		 278 int num_tiles;
279
6ee73861
BS		 280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 282
283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
284 uint32_t size, uint32_t pitch);
6ee73861
BS		 285};
286
287struct nouveau_fifo_engine {
6ee73861
BS		 288 int channels;
289
a8eaebc6 290 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 291 int cur_playlist;
292
6ee73861
BS		 293 int (*init)(struct drm_device *);
294 void (*takedown)(struct drm_device *);
295
296 void (*disable)(struct drm_device *);
297 void (*enable)(struct drm_device *);
298 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 299 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 300
301 int (*channel_id)(struct drm_device *);
302
303 int (*create_context)(struct nouveau_channel *);
304 void (*destroy_context)(struct nouveau_channel *);
305 int (*load_context)(struct nouveau_channel *);
306 int (*unload_context)(struct drm_device *);
307};
308
309struct nouveau_pgraph_object_method {
310 int id;
311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
312 uint32_t data);
313};
314
315struct nouveau_pgraph_object_class {
316 int id;
317 bool software;
318 struct nouveau_pgraph_object_method *methods;
319};
320
321struct nouveau_pgraph_engine {
322 struct nouveau_pgraph_object_class *grclass;
323 bool accel_blocked;
054b93e4 324 int grctx_size;
6ee73861 325
c50a5681 326 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 327 struct nouveau_gpuobj *ctx_table;
c50a5681 328
6ee73861
BS		 329 int (*init)(struct drm_device *);
330 void (*takedown)(struct drm_device *);
331
332 void (*fifo_access)(struct drm_device *, bool);
333
334 struct nouveau_channel *(*channel)(struct drm_device *);
335 int (*create_context)(struct nouveau_channel *);
336 void (*destroy_context)(struct nouveau_channel *);
337 int (*load_context)(struct nouveau_channel *);
338 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 339
340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
341 uint32_t size, uint32_t pitch);
6ee73861
BS		 342};
343
c88c2e06
FJ		 344struct nouveau_display_engine {
345 int (*early_init)(struct drm_device *);
346 void (*late_takedown)(struct drm_device *);
347 int (*create)(struct drm_device *);
348 int (*init)(struct drm_device *);
349 void (*destroy)(struct drm_device *);
350};
351
ee2e0131
BS		 352struct nouveau_gpio_engine {
353 int (*init)(struct drm_device *);
354 void (*takedown)(struct drm_device *);
355
356 int (*get)(struct drm_device *, enum dcb_gpio_tag);
357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
358
359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
360};
361
330c5988
BS		 362struct nouveau_pm_voltage_level {
363 u8 voltage;
364 u8 vid;
365};
366
367struct nouveau_pm_voltage {
368 bool supported;
369 u8 vid_mask;
370
371 struct nouveau_pm_voltage_level *level;
372 int nr_level;
373};
374
375#define NOUVEAU_PM_MAX_LEVEL 8
376struct nouveau_pm_level {
377 struct device_attribute dev_attr;
378 char name[32];
379 int id;
380
381 u32 core;
382 u32 memory;
383 u32 shader;
384 u32 unk05;
385
386 u8 voltage;
387 u8 fanspeed;
388};
389
34e9d85a
MP		 390struct nouveau_pm_temp_sensor_constants {
391 u16 offset_constant;
392 s16 offset_mult;
393 u16 offset_div;
394 u16 slope_mult;
395 u16 slope_div;
396};
397
398struct nouveau_pm_threshold_temp {
399 s16 critical;
400 s16 down_clock;
401 s16 fan_boost;
402};
403
330c5988
BS		 404struct nouveau_pm_engine {
405 struct nouveau_pm_voltage voltage;
406 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
407 int nr_perflvl;
34e9d85a
MP		 408 struct nouveau_pm_temp_sensor_constants sensor_constants;
409 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 410
411 struct nouveau_pm_level boot;
412 struct nouveau_pm_level *cur;
413
414 int (*clock_get)(struct drm_device *, u32 id);
415 void *(*clock_pre)(struct drm_device *, u32 id, int khz);
416 void (*clock_set)(struct drm_device *, void *);
417 int (*voltage_get)(struct drm_device *);
418 int (*voltage_set)(struct drm_device *, int voltage);
419 int (*fanspeed_get)(struct drm_device *);
420 int (*fanspeed_set)(struct drm_device *, int fanspeed);
421};
422
6ee73861
BS		 423struct nouveau_engine {
424 struct nouveau_instmem_engine instmem;
425 struct nouveau_mc_engine mc;
426 struct nouveau_timer_engine timer;
427 struct nouveau_fb_engine fb;
428 struct nouveau_pgraph_engine graph;
429 struct nouveau_fifo_engine fifo;
c88c2e06 430 struct nouveau_display_engine display;
ee2e0131 431 struct nouveau_gpio_engine gpio;
330c5988 432 struct nouveau_pm_engine pm;
6ee73861
BS		 433};
434
435struct nouveau_pll_vals {
436 union {
437 struct {
438#ifdef __BIG_ENDIAN
439 uint8_t N1, M1, N2, M2;
440#else
441 uint8_t M1, N1, M2, N2;
442#endif
443 };
444 struct {
445 uint16_t NM1, NM2;
446 } __attribute__((packed));
447 };
448 int log2P;
449
450 int refclk;
451};
452
453enum nv04_fp_display_regs {
454 FP_DISPLAY_END,
455 FP_TOTAL,
456 FP_CRTC,
457 FP_SYNC_START,
458 FP_SYNC_END,
459 FP_VALID_START,
460 FP_VALID_END
461};
462
463struct nv04_crtc_reg {
464 unsigned char MiscOutReg; /* */
4a9f822f 465 uint8_t CRTC[0xa0];
6ee73861
BS		 466 uint8_t CR58[0x10];
467 uint8_t Sequencer[5];
468 uint8_t Graphics[9];
469 uint8_t Attribute[21];
470 unsigned char DAC[768]; /* Internal Colorlookuptable */
471
472 /* PCRTC regs */
473 uint32_t fb_start;
474 uint32_t crtc_cfg;
475 uint32_t cursor_cfg;
476 uint32_t gpio_ext;
477 uint32_t crtc_830;
478 uint32_t crtc_834;
479 uint32_t crtc_850;
480 uint32_t crtc_eng_ctrl;
481
482 /* PRAMDAC regs */
483 uint32_t nv10_cursync;
484 struct nouveau_pll_vals pllvals;
485 uint32_t ramdac_gen_ctrl;
486 uint32_t ramdac_630;
487 uint32_t ramdac_634;
488 uint32_t tv_setup;
489 uint32_t tv_vtotal;
490 uint32_t tv_vskew;
491 uint32_t tv_vsync_delay;
492 uint32_t tv_htotal;
493 uint32_t tv_hskew;
494 uint32_t tv_hsync_delay;
495 uint32_t tv_hsync_delay2;
496 uint32_t fp_horiz_regs[7];
497 uint32_t fp_vert_regs[7];
498 uint32_t dither;
499 uint32_t fp_control;
500 uint32_t dither_regs[6];
501 uint32_t fp_debug_0;
502 uint32_t fp_debug_1;
503 uint32_t fp_debug_2;
504 uint32_t fp_margin_color;
505 uint32_t ramdac_8c0;
506 uint32_t ramdac_a20;
507 uint32_t ramdac_a24;
508 uint32_t ramdac_a34;
509 uint32_t ctv_regs[38];
510};
511
512struct nv04_output_reg {
513 uint32_t output;
514 int head;
515};
516
517struct nv04_mode_state {
518 uint32_t bpp;
519 uint32_t width;
520 uint32_t height;
521 uint32_t interlace;
522 uint32_t repaint0;
523 uint32_t repaint1;
524 uint32_t screen;
525 uint32_t scale;
526 uint32_t dither;
527 uint32_t extra;
528 uint32_t fifo;
529 uint32_t pixel;
530 uint32_t horiz;
531 int arbitration0;
532 int arbitration1;
533 uint32_t pll;
534 uint32_t pllB;
535 uint32_t vpll;
536 uint32_t vpll2;
537 uint32_t vpllB;
538 uint32_t vpll2B;
539 uint32_t pllsel;
540 uint32_t sel_clk;
541 uint32_t general;
542 uint32_t crtcOwner;
543 uint32_t head;
544 uint32_t head2;
545 uint32_t cursorConfig;
546 uint32_t cursor0;
547 uint32_t cursor1;
548 uint32_t cursor2;
549 uint32_t timingH;
550 uint32_t timingV;
551 uint32_t displayV;
552 uint32_t crtcSync;
553
554 struct nv04_crtc_reg crtc_reg[2];
555};
556
557enum nouveau_card_type {
558 NV_04 = 0x00,
559 NV_10 = 0x10,
560 NV_20 = 0x20,
561 NV_30 = 0x30,
562 NV_40 = 0x40,
563 NV_50 = 0x50,
4b223eef 564 NV_C0 = 0xc0,
6ee73861
BS		 565};
566
567struct drm_nouveau_private {
568 struct drm_device *dev;
6ee73861
BS		 569
570 /* the card type, takes NV_* as values */
571 enum nouveau_card_type card_type;
572 /* exact chipset, derived from NV_PMC_BOOT_0 */
573 int chipset;
574 int flags;
575
576 void __iomem *mmio;
5125bfd8 577
e05d7eae 578 spinlock_t ramin_lock;
6ee73861 579 void __iomem *ramin;
5125bfd8
BS		 580 u32 ramin_size;
581 u32 ramin_base;
582 bool ramin_available;
e05d7eae
BS		 583 struct drm_mm ramin_heap;
584 struct list_head gpuobj_list;
6ee73861 585
ac8fb975
BS		 586 struct nouveau_bo *vga_ram;
587
6ee73861
BS		 588 struct workqueue_struct *wq;
589 struct work_struct irq_work;
a5acac66 590 struct work_struct hpd_work;
6ee73861
BS		 591
592 struct list_head vbl_waiting;
593
594 struct {
ba4420c2 595 struct drm_global_reference mem_global_ref;
6ee73861
BS		 596 struct ttm_bo_global_ref bo_global_ref;
597 struct ttm_bo_device bdev;
6ee73861
BS		 598 atomic_t validate_sequence;
599 } ttm;
600
6ee73861
BS		 601 int fifo_alloc_count;
602 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
603
604 struct nouveau_engine engine;
605 struct nouveau_channel *channel;
606
ff9e5279
MM		 607 /* For PFIFO and PGRAPH. */
608 spinlock_t context_switch_lock;
609
6ee73861 610 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 611 struct nouveau_ramht *ramht;
612 struct nouveau_gpuobj *ramfc;
613 struct nouveau_gpuobj *ramro;
614
6ee73861 615 uint32_t ramin_rsvd_vram;
6ee73861 616
6ee73861
BS		 617 struct {
618 enum {
619 NOUVEAU_GART_NONE = 0,
620 NOUVEAU_GART_AGP,
621 NOUVEAU_GART_SGDMA
622 } type;
623 uint64_t aper_base;
624 uint64_t aper_size;
625 uint64_t aper_free;
626
627 struct nouveau_gpuobj *sg_ctxdma;
628 struct page *sg_dummy_page;
629 dma_addr_t sg_dummy_bus;
6ee73861
BS		 630 } gart_info;
631
a0af9add 632 /* nv10-nv40 tiling regions */
9f56b126 633 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 634
a76fb4e8
BS		 635 /* VRAM/fb configuration */
636 uint64_t vram_size;
637 uint64_t vram_sys_base;
6c3d7ef2 638 u32 vram_rblock_size;
a76fb4e8
BS		 639
640 uint64_t fb_phys;
641 uint64_t fb_available_size;
642 uint64_t fb_mappable_pages;
643 uint64_t fb_aper_free;
644 int fb_mtrr;
645
6ee73861
BS		 646 /* G8x/G9x virtual address space */
647 uint64_t vm_gart_base;
648 uint64_t vm_gart_size;
649 uint64_t vm_vram_base;
650 uint64_t vm_vram_size;
651 uint64_t vm_end;
652 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
653 int vm_vram_pt_nr;
6ee73861 654
04a39c57 655 struct nvbios vbios;
6ee73861
BS		 656
657 struct nv04_mode_state mode_reg;
658 struct nv04_mode_state saved_reg;
659 uint32_t saved_vga_font[4][16384];
660 uint32_t crtc_owner;
661 uint32_t dac_users[4];
662
663 struct nouveau_suspend_resume {
6ee73861 664 uint32_t *ramin_copy;
6ee73861
BS		 665 } susres;
666
667 struct backlight_device *backlight;
6ee73861
BS		 668
669 struct nouveau_channel *evo;
87c0e0e5
BS		 670 struct {
671 struct dcb_entry *dcb;
672 u16 script;
673 u32 pclk;
674 } evo_irq;
6ee73861
BS		 675
676 struct {
677 struct dentry *channel_root;
678 } debugfs;
38651674 679
8be48d92 680 struct nouveau_fbdev *nfbdev;
06415c56 681 struct apertures_struct *apertures;
34e9d85a
MP		 682
683 struct device *int_hwmon_dev;
6ee73861
BS		 684};
685
686static inline struct drm_nouveau_private *
687nouveau_bdev(struct ttm_bo_device *bd)
688{
689 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
690}
691
692static inline int
693nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
694{
695 struct nouveau_bo *prev;
696
697 if (!pnvbo)
698 return -EINVAL;
699 prev = *pnvbo;
700
701 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
702 if (prev) {
703 struct ttm_buffer_object *bo = &prev->bo;
704
705 ttm_bo_unref(&bo);
706 }
707
708 return 0;
709}
710
6ee73861
BS		 711#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
712 struct drm_nouveau_private *nv = dev->dev_private; \
713 if (!nouveau_channel_owner(dev, (cl), (id))) { \
714 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
715 DRM_CURRENTPID, (id)); \
716 return -EPERM; \
717 } \
718 (ch) = nv->fifos[(id)]; \
719} while (0)
720
721/* nouveau_drv.c */
de5899bd 722extern int nouveau_agpmode;
6ee73861
BS		 723extern int nouveau_duallink;
724extern int nouveau_uscript_lvds;
725extern int nouveau_uscript_tmds;
726extern int nouveau_vram_pushbuf;
727extern int nouveau_vram_notify;
728extern int nouveau_fbpercrtc;
f4053509 729extern int nouveau_tv_disable;
6ee73861
BS		 730extern char *nouveau_tv_norm;
731extern int nouveau_reg_debug;
732extern char *nouveau_vbios;
a1470890 733extern int nouveau_ignorelid;
a32ed69d
MK		 734extern int nouveau_nofbaccel;
735extern int nouveau_noaccel;
da647d5b 736extern int nouveau_override_conntype;
6f876986
BS		 737extern char *nouveau_perflvl;
738extern int nouveau_perflvl_wr;
6ee73861 739
6a9ee8af
DA		 740extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
741extern int nouveau_pci_resume(struct pci_dev *pdev);
742
6ee73861
BS		 743/* nouveau_state.c */
744extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
745extern int nouveau_load(struct drm_device *, unsigned long flags);
746extern int nouveau_firstopen(struct drm_device *);
747extern void nouveau_lastclose(struct drm_device *);
748extern int nouveau_unload(struct drm_device *);
749extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
750 struct drm_file *);
751extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
752 struct drm_file *);
753extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
754 uint32_t reg, uint32_t mask, uint32_t val);
755extern bool nouveau_wait_for_idle(struct drm_device *);
756extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 757
758/* nouveau_mem.c */
fbd2895e
BS		 759extern int nouveau_mem_vram_init(struct drm_device *);
760extern void nouveau_mem_vram_fini(struct drm_device *);
761extern int nouveau_mem_gart_init(struct drm_device *);
762extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 763extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 764extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 765extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 766extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
767 uint32_t addr,
768 uint32_t size,
769 uint32_t pitch);
770extern void nv10_mem_expire_tiling(struct drm_device *dev,
771 struct nouveau_tile_reg *tile,
772 struct nouveau_fence *fence);
6ee73861
BS		 773extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
774 uint32_t size, uint32_t flags,
775 uint64_t phys);
776extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
777 uint32_t size);
778
779/* nouveau_notifier.c */
780extern int nouveau_notifier_init_channel(struct nouveau_channel *);
781extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
782extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
783 int cout, uint32_t *offset);
784extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
785extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
786 struct drm_file *);
787extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
788 struct drm_file *);
789
790/* nouveau_channel.c */
791extern struct drm_ioctl_desc nouveau_ioctls[];
792extern int nouveau_max_ioctl;
793extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
794extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
795 int channel);
796extern int nouveau_channel_alloc(struct drm_device *dev,
797 struct nouveau_channel **chan,
798 struct drm_file *file_priv,
799 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
800extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 801
802/* nouveau_object.c */
803extern int nouveau_gpuobj_early_init(struct drm_device *);
804extern int nouveau_gpuobj_init(struct drm_device *);
805extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 806extern int nouveau_gpuobj_suspend(struct drm_device *dev);
807extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
808extern void nouveau_gpuobj_resume(struct drm_device *dev);
809extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
810 uint32_t vram_h, uint32_t tt_h);
811extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
812extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
813 uint32_t size, int align, uint32_t flags,
814 struct nouveau_gpuobj **);
a8eaebc6
BS		 815extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
816 struct nouveau_gpuobj **);
43efc9ce
BS		 817extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
818 u32 size, u32 flags,
a8eaebc6 819 struct nouveau_gpuobj **);
6ee73861
BS		 820extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
821 uint64_t offset, uint64_t size, int access,
822 int target, struct nouveau_gpuobj **);
823extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
824 uint64_t offset, uint64_t size,
825 int access, struct nouveau_gpuobj **,
826 uint32_t *o_ret);
827extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
828 struct nouveau_gpuobj **);
f03a314b
FJ		 829extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
830 struct nouveau_gpuobj **);
6ee73861
BS		 831extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
832 struct drm_file *);
833extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
834 struct drm_file *);
835
836/* nouveau_irq.c */
837extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
838extern void nouveau_irq_preinstall(struct drm_device *);
839extern int nouveau_irq_postinstall(struct drm_device *);
840extern void nouveau_irq_uninstall(struct drm_device *);
841
842/* nouveau_sgdma.c */
843extern int nouveau_sgdma_init(struct drm_device *);
844extern void nouveau_sgdma_takedown(struct drm_device *);
845extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
846 uint32_t *page);
847extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
848
849/* nouveau_debugfs.c */
850#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
851extern int nouveau_debugfs_init(struct drm_minor *);
852extern void nouveau_debugfs_takedown(struct drm_minor *);
853extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
854extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
855#else
856static inline int
857nouveau_debugfs_init(struct drm_minor *minor)
858{
859 return 0;
860}
861
862static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
863{
864}
865
866static inline int
867nouveau_debugfs_channel_init(struct nouveau_channel *chan)
868{
869 return 0;
870}
871
872static inline void
873nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
874{
875}
876#endif
877
878/* nouveau_dma.c */
75c99da6 879extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 880extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 881extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 882
883/* nouveau_acpi.c */
afeb3e11 884#define ROM_BIOS_PAGE 4096
2f41a7f1 885#if defined(CONFIG_ACPI)
6a9ee8af
DA		 886void nouveau_register_dsm_handler(void);
887void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 888int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
889bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 890int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 891#else
892static inline void nouveau_register_dsm_handler(void) {}
893static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 894static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
895static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 896static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 897#endif
6ee73861
BS		 898
899/* nouveau_backlight.c */
900#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
901extern int nouveau_backlight_init(struct drm_device *);
902extern void nouveau_backlight_exit(struct drm_device *);
903#else
904static inline int nouveau_backlight_init(struct drm_device *dev)
905{
906 return 0;
907}
908
909static inline void nouveau_backlight_exit(struct drm_device *dev) { }
910#endif
911
912/* nouveau_bios.c */
913extern int nouveau_bios_init(struct drm_device *);
914extern void nouveau_bios_takedown(struct drm_device *dev);
915extern int nouveau_run_vbios_init(struct drm_device *);
916extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
917 struct dcb_entry *);
918extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
919 enum dcb_gpio_tag);
920extern struct dcb_connector_table_entry *
921nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 922extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 923extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
924 struct pll_lims *);
925extern int nouveau_bios_run_display_table(struct drm_device *,
926 struct dcb_entry *,
927 uint32_t script, int pxclk);
928extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
929 int *length);
930extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
931extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
932extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
933 bool *dl, bool *if_is_24bit);
934extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
935 int head, int pxclk);
936extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
937 enum LVDS_script, int pxclk);
938
939/* nouveau_ttm.c */
940int nouveau_ttm_global_init(struct drm_nouveau_private *);
941void nouveau_ttm_global_release(struct drm_nouveau_private *);
942int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
943
944/* nouveau_dp.c */
945int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
946 uint8_t *data, int data_nr);
947bool nouveau_dp_detect(struct drm_encoder *);
948bool nouveau_dp_link_train(struct drm_encoder *);
949
950/* nv04_fb.c */
951extern int nv04_fb_init(struct drm_device *);
952extern void nv04_fb_takedown(struct drm_device *);
953
954/* nv10_fb.c */
955extern int nv10_fb_init(struct drm_device *);
956extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 957extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
958 uint32_t, uint32_t);
6ee73861 959
8bded189
FJ		 960/* nv30_fb.c */
961extern int nv30_fb_init(struct drm_device *);
962extern void nv30_fb_takedown(struct drm_device *);
963
6ee73861
BS		 964/* nv40_fb.c */
965extern int nv40_fb_init(struct drm_device *);
966extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 967extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
968 uint32_t, uint32_t);
304424e1
MK		 969/* nv50_fb.c */
970extern int nv50_fb_init(struct drm_device *);
971extern void nv50_fb_takedown(struct drm_device *);
d96773e7 972extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 973
4b223eef
BS		 974/* nvc0_fb.c */
975extern int nvc0_fb_init(struct drm_device *);
976extern void nvc0_fb_takedown(struct drm_device *);
977
6ee73861
BS		 978/* nv04_fifo.c */
979extern int nv04_fifo_init(struct drm_device *);
980extern void nv04_fifo_disable(struct drm_device *);
981extern void nv04_fifo_enable(struct drm_device *);
982extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 983extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 984extern int nv04_fifo_channel_id(struct drm_device *);
985extern int nv04_fifo_create_context(struct nouveau_channel *);
986extern void nv04_fifo_destroy_context(struct nouveau_channel *);
987extern int nv04_fifo_load_context(struct nouveau_channel *);
988extern int nv04_fifo_unload_context(struct drm_device *);
989
990/* nv10_fifo.c */
991extern int nv10_fifo_init(struct drm_device *);
992extern int nv10_fifo_channel_id(struct drm_device *);
993extern int nv10_fifo_create_context(struct nouveau_channel *);
994extern void nv10_fifo_destroy_context(struct nouveau_channel *);
995extern int nv10_fifo_load_context(struct nouveau_channel *);
996extern int nv10_fifo_unload_context(struct drm_device *);
997
998/* nv40_fifo.c */
999extern int nv40_fifo_init(struct drm_device *);
1000extern int nv40_fifo_create_context(struct nouveau_channel *);
1001extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1002extern int nv40_fifo_load_context(struct nouveau_channel *);
1003extern int nv40_fifo_unload_context(struct drm_device *);
1004
1005/* nv50_fifo.c */
1006extern int nv50_fifo_init(struct drm_device *);
1007extern void nv50_fifo_takedown(struct drm_device *);
1008extern int nv50_fifo_channel_id(struct drm_device *);
1009extern int nv50_fifo_create_context(struct nouveau_channel *);
1010extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1011extern int nv50_fifo_load_context(struct nouveau_channel *);
1012extern int nv50_fifo_unload_context(struct drm_device *);
1013
4b223eef
BS		 1014/* nvc0_fifo.c */
1015extern int nvc0_fifo_init(struct drm_device *);
1016extern void nvc0_fifo_takedown(struct drm_device *);
1017extern void nvc0_fifo_disable(struct drm_device *);
1018extern void nvc0_fifo_enable(struct drm_device *);
1019extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1020extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1021extern int nvc0_fifo_channel_id(struct drm_device *);
1022extern int nvc0_fifo_create_context(struct nouveau_channel *);
1023extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1024extern int nvc0_fifo_load_context(struct nouveau_channel *);
1025extern int nvc0_fifo_unload_context(struct drm_device *);
1026
6ee73861
BS		 1027/* nv04_graph.c */
1028extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1029extern int nv04_graph_init(struct drm_device *);
1030extern void nv04_graph_takedown(struct drm_device *);
1031extern void nv04_graph_fifo_access(struct drm_device *, bool);
1032extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1033extern int nv04_graph_create_context(struct nouveau_channel *);
1034extern void nv04_graph_destroy_context(struct nouveau_channel *);
1035extern int nv04_graph_load_context(struct nouveau_channel *);
1036extern int nv04_graph_unload_context(struct drm_device *);
1037extern void nv04_graph_context_switch(struct drm_device *);
1038
1039/* nv10_graph.c */
1040extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1041extern int nv10_graph_init(struct drm_device *);
1042extern void nv10_graph_takedown(struct drm_device *);
1043extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1044extern int nv10_graph_create_context(struct nouveau_channel *);
1045extern void nv10_graph_destroy_context(struct nouveau_channel *);
1046extern int nv10_graph_load_context(struct nouveau_channel *);
1047extern int nv10_graph_unload_context(struct drm_device *);
1048extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1049extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1050 uint32_t, uint32_t);
6ee73861
BS		 1051
1052/* nv20_graph.c */
1053extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1054extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1055extern int nv20_graph_create_context(struct nouveau_channel *);
1056extern void nv20_graph_destroy_context(struct nouveau_channel *);
1057extern int nv20_graph_load_context(struct nouveau_channel *);
1058extern int nv20_graph_unload_context(struct drm_device *);
1059extern int nv20_graph_init(struct drm_device *);
1060extern void nv20_graph_takedown(struct drm_device *);
1061extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1062extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1063 uint32_t, uint32_t);
6ee73861
BS		 1064
1065/* nv40_graph.c */
1066extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1067extern int nv40_graph_init(struct drm_device *);
1068extern void nv40_graph_takedown(struct drm_device *);
1069extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1070extern int nv40_graph_create_context(struct nouveau_channel *);
1071extern void nv40_graph_destroy_context(struct nouveau_channel *);
1072extern int nv40_graph_load_context(struct nouveau_channel *);
1073extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1074extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1075extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1076 uint32_t, uint32_t);
6ee73861
BS		 1077
1078/* nv50_graph.c */
1079extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1080extern int nv50_graph_init(struct drm_device *);
1081extern void nv50_graph_takedown(struct drm_device *);
1082extern void nv50_graph_fifo_access(struct drm_device *, bool);
1083extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1084extern int nv50_graph_create_context(struct nouveau_channel *);
1085extern void nv50_graph_destroy_context(struct nouveau_channel *);
1086extern int nv50_graph_load_context(struct nouveau_channel *);
1087extern int nv50_graph_unload_context(struct drm_device *);
1088extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1089extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1090
4b223eef
BS		 1091/* nvc0_graph.c */
1092extern int nvc0_graph_init(struct drm_device *);
1093extern void nvc0_graph_takedown(struct drm_device *);
1094extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1095extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1096extern int nvc0_graph_create_context(struct nouveau_channel *);
1097extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1098extern int nvc0_graph_load_context(struct nouveau_channel *);
1099extern int nvc0_graph_unload_context(struct drm_device *);
1100
6ee73861
BS		 1101/* nv04_instmem.c */
1102extern int nv04_instmem_init(struct drm_device *);
1103extern void nv04_instmem_takedown(struct drm_device *);
1104extern int nv04_instmem_suspend(struct drm_device *);
1105extern void nv04_instmem_resume(struct drm_device *);
1106extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1107 uint32_t *size);
1108extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1109extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1110extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1111extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1112
1113/* nv50_instmem.c */
1114extern int nv50_instmem_init(struct drm_device *);
1115extern void nv50_instmem_takedown(struct drm_device *);
1116extern int nv50_instmem_suspend(struct drm_device *);
1117extern void nv50_instmem_resume(struct drm_device *);
1118extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1119 uint32_t *size);
1120extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1121extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1122extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1123extern void nv50_instmem_flush(struct drm_device *);
734ee835 1124extern void nv84_instmem_flush(struct drm_device *);
63187215 1125extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1126
4b223eef
BS		 1127/* nvc0_instmem.c */
1128extern int nvc0_instmem_init(struct drm_device *);
1129extern void nvc0_instmem_takedown(struct drm_device *);
1130extern int nvc0_instmem_suspend(struct drm_device *);
1131extern void nvc0_instmem_resume(struct drm_device *);
1132extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1133 uint32_t *size);
1134extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1135extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1136extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1137extern void nvc0_instmem_flush(struct drm_device *);
1138
6ee73861
BS		 1139/* nv04_mc.c */
1140extern int nv04_mc_init(struct drm_device *);
1141extern void nv04_mc_takedown(struct drm_device *);
1142
1143/* nv40_mc.c */
1144extern int nv40_mc_init(struct drm_device *);
1145extern void nv40_mc_takedown(struct drm_device *);
1146
1147/* nv50_mc.c */
1148extern int nv50_mc_init(struct drm_device *);
1149extern void nv50_mc_takedown(struct drm_device *);
1150
1151/* nv04_timer.c */
1152extern int nv04_timer_init(struct drm_device *);
1153extern uint64_t nv04_timer_read(struct drm_device *);
1154extern void nv04_timer_takedown(struct drm_device *);
1155
1156extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1157 unsigned long arg);
1158
1159/* nv04_dac.c */
8f1a6086 1160extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1161extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1162extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1163extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1164extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1165
1166/* nv04_dfp.c */
8f1a6086 1167extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1168extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1169extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1170 int head, bool dl);
1171extern void nv04_dfp_disable(struct drm_device *dev, int head);
1172extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1173
1174/* nv04_tv.c */
1175extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1176extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1177
1178/* nv17_tv.c */
8f1a6086 1179extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1180
1181/* nv04_display.c */
c88c2e06
FJ		 1182extern int nv04_display_early_init(struct drm_device *);
1183extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1184extern int nv04_display_create(struct drm_device *);
c88c2e06 1185extern int nv04_display_init(struct drm_device *);
6ee73861 1186extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1187
1188/* nv04_crtc.c */
1189extern int nv04_crtc_create(struct drm_device *, int index);
1190
1191/* nouveau_bo.c */
1192extern struct ttm_bo_driver nouveau_bo_driver;
1193extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1194 int size, int align, uint32_t flags,
1195 uint32_t tile_mode, uint32_t tile_flags,
1196 bool no_vm, bool mappable, struct nouveau_bo **);
1197extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1198extern int nouveau_bo_unpin(struct nouveau_bo *);
1199extern int nouveau_bo_map(struct nouveau_bo *);
1200extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1201extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1202 uint32_t busy);
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BS		 1203extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1204extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1205extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1206extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
415e6186 1207extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
6ee73861
BS		 1208
1209/* nouveau_fence.c */
1210struct nouveau_fence;
1211extern int nouveau_fence_init(struct nouveau_channel *);
1212extern void nouveau_fence_fini(struct nouveau_channel *);
1213extern void nouveau_fence_update(struct nouveau_channel *);
1214extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1215 bool emit);
1216extern int nouveau_fence_emit(struct nouveau_fence *);
1217struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1218extern bool nouveau_fence_signalled(void *obj, void *arg);
1219extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1220extern int nouveau_fence_flush(void *obj, void *arg);
1221extern void nouveau_fence_unref(void **obj);
1222extern void *nouveau_fence_ref(void *obj);
6ee73861
BS		 1223
1224/* nouveau_gem.c */
1225extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1226 int size, int align, uint32_t flags,
1227 uint32_t tile_mode, uint32_t tile_flags,
1228 bool no_vm, bool mappable, struct nouveau_bo **);
1229extern int nouveau_gem_object_new(struct drm_gem_object *);
1230extern void nouveau_gem_object_del(struct drm_gem_object *);
1231extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1232 struct drm_file *);
1233extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1234 struct drm_file *);
6ee73861
BS		 1235extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1236 struct drm_file *);
1237extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1238 struct drm_file *);
1239extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1240 struct drm_file *);
1241
ee2e0131
BS		 1242/* nv10_gpio.c */
1243int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1244int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1245
45284162 1246/* nv50_gpio.c */
ee2e0131 1247int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1248int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1249int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1250void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1251
e9ebb68b
BS		 1252/* nv50_calc. */
1253int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1254 int *N1, int *M1, int *N2, int *M2, int *P);
1255int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1256 int clk, int *N, int *fN, int *M, int *P);
1257
6ee73861
BS		 1258#ifndef ioread32_native
1259#ifdef __BIG_ENDIAN
1260#define ioread16_native ioread16be
1261#define iowrite16_native iowrite16be
1262#define ioread32_native ioread32be
1263#define iowrite32_native iowrite32be
1264#else /* def __BIG_ENDIAN */
1265#define ioread16_native ioread16
1266#define iowrite16_native iowrite16
1267#define ioread32_native ioread32
1268#define iowrite32_native iowrite32
1269#endif /* def __BIG_ENDIAN else */
1270#endif /* !ioread32_native */
1271
1272/* channel control reg access */
1273static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1274{
1275 return ioread32_native(chan->user + reg);
1276}
1277
1278static inline void nvchan_wr32(struct nouveau_channel *chan,
1279 unsigned reg, u32 val)
1280{
1281 iowrite32_native(val, chan->user + reg);
1282}
1283
1284/* register access */
1285static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1286{
1287 struct drm_nouveau_private *dev_priv = dev->dev_private;
1288 return ioread32_native(dev_priv->mmio + reg);
1289}
1290
1291static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1292{
1293 struct drm_nouveau_private *dev_priv = dev->dev_private;
1294 iowrite32_native(val, dev_priv->mmio + reg);
1295}
1296
2a7fdb2b 1297static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1298{
1299 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1300 nv_wr32(dev, reg, (tmp & ~mask) | val);
1301 return tmp;
49eed80a
BS		 1302}
1303
6ee73861
BS		 1304static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1305{
1306 struct drm_nouveau_private *dev_priv = dev->dev_private;
1307 return ioread8(dev_priv->mmio + reg);
1308}
1309
1310static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1311{
1312 struct drm_nouveau_private *dev_priv = dev->dev_private;
1313 iowrite8(val, dev_priv->mmio + reg);
1314}
1315
4b5c152a 1316#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1317 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1318
1319/* PRAMIN access */
1320static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1321{
1322 struct drm_nouveau_private *dev_priv = dev->dev_private;
1323 return ioread32_native(dev_priv->ramin + offset);
1324}
1325
1326static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1327{
1328 struct drm_nouveau_private *dev_priv = dev->dev_private;
1329 iowrite32_native(val, dev_priv->ramin + offset);
1330}
1331
1332/* object access */
b3beb167
BS		 1333extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1334extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1335
1336/*
1337 * Logging
1338 * Argument d is (struct drm_device *).
1339 */
1340#define NV_PRINTK(level, d, fmt, arg...) \
1341 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1342 pci_name(d->pdev), ##arg)
1343#ifndef NV_DEBUG_NOTRACE
1344#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1345 if (drm_debug & DRM_UT_DRIVER) { \
1346 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1347 __LINE__, ##arg); \
1348 } \
1349} while (0)
1350#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1351 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1352 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1353 __LINE__, ##arg); \
1354 } \
1355} while (0)
1356#else
1357#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1358 if (drm_debug & DRM_UT_DRIVER) \
1359 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1360} while (0)
1361#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1362 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1363 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1364} while (0)
1365#endif
1366#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1367#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1368#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1369#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1370#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1371
1372/* nouveau_reg_debug bitmask */
1373enum {
1374 NOUVEAU_REG_DEBUG_MC = 0x1,
1375 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1376 NOUVEAU_REG_DEBUG_FB = 0x4,
1377 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1378 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1379 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1380 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1381 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1382 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1383 NOUVEAU_REG_DEBUG_EVO = 0x200,
1384};
1385
1386#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1387 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1388 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1389} while (0)
1390
1391static inline bool
1392nv_two_heads(struct drm_device *dev)
1393{
1394 struct drm_nouveau_private *dev_priv = dev->dev_private;
1395 const int impl = dev->pci_device & 0x0ff0;
1396
1397 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1398 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1399 return true;
1400
1401 return false;
1402}
1403
1404static inline bool
1405nv_gf4_disp_arch(struct drm_device *dev)
1406{
1407 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1408}
1409
1410static inline bool
1411nv_two_reg_pll(struct drm_device *dev)
1412{
1413 struct drm_nouveau_private *dev_priv = dev->dev_private;
1414 const int impl = dev->pci_device & 0x0ff0;
1415
1416 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1417 return true;
1418 return false;
1419}
1420
acae116c
FJ		 1421static inline bool
1422nv_match_device(struct drm_device *dev, unsigned device,
1423 unsigned sub_vendor, unsigned sub_device)
1424{
1425 return dev->pdev->device == device &&
1426 dev->pdev->subsystem_vendor == sub_vendor &&
1427 dev->pdev->subsystem_device == sub_device;
1428}
1429
f03a314b
FJ		 1430#define NV_SW 0x0000506e
1431#define NV_SW_DMA_SEMAPHORE 0x00000060
1432#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1433#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1434#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1435#define NV_SW_DMA_VBLSEM 0x0000018c
1436#define NV_SW_VBLSEM_OFFSET 0x00000400
1437#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1438#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1439
1440#endif /* __NOUVEAU_DRV_H__ */
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